Commit Graph

581 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
005e6656be Merge branch 'feature/add_new_pkg_and_flash_psram_efuses_v5.1' into 'release/v5.1'
feat(efuse): Add flash&psram efuses for S3 (v5.1)

See merge request espressif/esp-idf!29143
2024-03-05 10:34:18 +08:00
Darian Leung
d837836f84
refactor(hal/usb): Rename usb_fsls_phy API to match header/source names
Note: Also fixed some formatting issues in usb_wrap_struct.h
2024-02-28 16:09:52 +08:00
Darian Leung
b32a735bb0
refactor(soc/host): Update USB OTG struct fields
This commit updates the "*_struct.h" files for the USB OTG peripheral:

- Added/removed some missing/non-existing register fields
- Added "reserved" place holders for registers that are missing due to IP
configuration.
- Added "usb_dwc_cfg.h" listing the USB OTG IP configuration for each target.
- Updated LL/HAL according to register field updates. Also tidied up the include
directives in those headers.
2024-02-28 16:09:51 +08:00
KonstantinKondrashov
24f6995fb5 feat(efuse): Add flash&psram efuses for S3 2024-02-21 09:36:49 +02:00
Marius Vikhammer
40bea117e4 Merge branch 'bugfix/s3_irom_addr_v5.1' into 'release/v5.1'
soc: fix SOC_IROM_MASK_HIGH for esp32s3 (v5.1)

See merge request espressif/esp-idf!27136
2023-12-20 10:00:39 +08:00
Mahavir Jain
fa7383162f Merge branch 'fix/esp32s3_soc_drom_high_addr_v5.1' into 'release/v5.1'
fix(soc): esp32s3/Fix the DROM_HIGH_ADDR (v5.1)

See merge request espressif/esp-idf!27822
2023-12-17 16:31:41 +08:00
morris
eb7022dd06 Merge branch 'contrib/github_pr_12559_v5.1' into 'release/v5.1'
fix(spi): Correct REG_SPI_BASE(i) macro for all targets (GitHub PR) (v5.1)

See merge request espressif/esp-idf!27714
2023-12-14 11:08:03 +08:00
Aditya Patwardhan
f62e7fd4e8
fix(soc): esp32s3/Fix the DROM_DROM_HIGH limit
Previously the DROM_HIGH_ADDR for esp32s3 was 0x3D000000, which
    convers only 16 MB of address range. But esp32s3 supports 32 MB
    external memory. So this address should be 0x3E000000
2023-12-11 12:17:31 +05:30
gaoxu
6190b3f7c9 fix(adc): restore cali registers after light sleep wake up on H2 and enable test 2023-12-06 10:19:52 +00:00
wanlei
3486cf1b60 fix(spi): correct some signals and dummy bits docs 2023-12-06 16:15:23 +08:00
TD-er
8e0d64e94c fix(spi): Correct REG_SPI_BASE(i) macro for all targets
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
2023-12-06 16:13:01 +08:00
Darian Leung
411405355d refactor(soc): SOC_USB_PERIPH_NUM option
This commit refactors SOC_USB_PERIPH_NUM as follows:

- Renamed to SOC_USB_OTG_PERIPH_NUM to avoid confusion with USB Serial JTAG
- Updated to unsigned integer "1U"
- Updated some build rules to depend on SOC_USB_OTG_SUPPORTED instead
2023-11-28 22:00:30 +01:00
Jiang Jiang Jian
0e1ec38785 Merge branch 'bugfix/fix_lightsleep_current_leakage_on_usj_pad_v5.1' into 'release/v5.1'
fix(esp_hw_support): fix lightsleep current leakage on usb pad (backport v5.1)

See merge request espressif/esp-idf!27205
2023-11-21 10:51:11 +08:00
wuzhenghui
eb45eec5db
change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 2023-11-16 20:40:03 +08:00
wuzhenghui
6ae596c764
fix(esp_hw_support): fix lightsleep current leakage on usb-phy controlled pad 2023-11-16 20:03:30 +08:00
Ivan Grokhotkov
6fa2080706
fix(soc): correct SOC_IROM_MASK_HIGH for esp32s3
Fixes corrupted backtraces on S3 when a function is in ROM.

Closes https://github.com/espressif/esp-idf/issues/11512
2023-11-14 14:27:23 +01:00
Erhan Kurubas
754b2a0de1 fix(interrupts): reorder esp32s3 irq names to align with the respective irq numbers 2023-10-16 22:20:45 +02:00
alanmaxwell
9337525cdc fix(phy): Fix PHY enabled enter WiFi RX state default 2023-09-27 14:55:25 +08:00
Chen Jichang
c240a1f46b feat(MCPWM): Add mcpwm carrier clk source
The MCPWM carrier is part of the operator and can work independently
without the MCPWM timer being enabled. This commit add the MCPWM
carrier clk source.
2023-08-25 17:34:58 +08:00
Song Ruo Jing
6768f098dc change(driver/rtcio): Describe RTCIO CAPS with more accurate note 2023-08-03 16:46:55 +08:00
wuzhenghui
e0e4642ff8 Revert "fix(esp_pm): Constrains the minimum frequency of APB_MAX when the modem is working"
This reverts commit 9158cba846.
2023-07-25 13:51:37 +08:00
wuzhenghui
9158cba846 fix(esp_pm): Constrains the minimum frequency of APB_MAX when the modem is working 2023-07-15 01:56:55 +08:00
muhaidong
2f56bd8aac external coex: rename coex gpio struct field names 2023-07-13 10:37:53 +08:00
morris
a0e8f5aa03 Merge branch 'contrib/github_pr_10811_5.1' into 'release/v5.1'
i2c: introduce chip specific cmd register number(backport v5.1)

See merge request espressif/esp-idf!24694
2023-07-12 11:15:03 +08:00
Hanno
c2b8a1d95c i2c: introduce chip specific cmd register number
Merges https://github.com/espressif/esp-idf/pull/10811
2023-07-11 14:55:46 +08:00
Alexey Gerenkov
3eacf08267 fix(app_trace): Fix apptrace data corruption on ESP32-S3
Close https://github.com/espressif/esp-idf/issues/10604
diff --git a/components/soc/esp32s3/include/soc/tracemem_config.h b/components/soc/esp32s3/include/soc/tracemem_config.h
index 55c9b907dd..75fd87419b 100644
--- a/components/soc/esp32s3/include/soc/tracemem_config.h
+++ b/components/soc/esp32s3/include/soc/tracemem_config.h
@@ -10,7 +10,7 @@ extern "C" {
 #endif

 #define TRACEMEM_MUX_BLK0_NUM                   22
-#define TRACEMEM_MUX_BLK1_NUM                   23
+#define TRACEMEM_MUX_BLK1_NUM                   26

 #if (TRACEMEM_MUX_BLK0_NUM < 6) || (TRACEMEM_MUX_BLK0_NUM > 29)
 #error Invalid TRAX block 0 num!
2023-07-10 13:06:02 +03:00
morris
0e4c071519 Merge branch 'bugfix/fix_i2s_ll_cpp_compilation_failure_v5.1' into 'release/v5.1'
i2s: fixed i2s_ll compiling failure under C++ environment (v5.1)

See merge request espressif/esp-idf!24401
2023-07-04 11:03:35 +08:00
laokaiyao
13e74d5573 i2s: fixed i2s_ll compiling failure under C++ evironment
Closes: https://github.com/espressif/esp-idf/issues/11625
2023-06-26 15:42:36 +08:00
morris
f9cf8db97e drivers: fix issue reported by coverity 2023-06-07 11:42:11 +08:00
Shen Weilong
0d12613ab9 ble docs: Update the ble docs for esp32c6 and esp32h2 2023-05-19 11:03:11 +08:00
Mahavir Jain
c49dce48eb Merge branch 'fix/esp32s3_ununsed_dcache_as_dram_v5.1' into 'release/v5.1'
esp_hw_support: Update the memory ptr location/property checks to include the unused DCACHE added to DRAM (v5.1)

See merge request espressif/esp-idf!23303
2023-04-27 22:09:55 +08:00
Marius Vikhammer
0bac174058 ulp: added sleep support for lp core
Added support for running LP core while hp core sleeps, as well
as waking up the hp core.
2023-04-27 09:51:41 +08:00
morris
aedcec9be5 Merge branch 'feature/emmc_example_v5.1' into 'release/v5.1'
SDMMC Host: added an example to communicate with an eMMC chip and also a bugfix for Host timing (v5.1)

See merge request espressif/esp-idf!23283
2023-04-26 22:41:15 +08:00
morris
1b6461b9f8 Merge branch 'bugfix/bod_glitch_reset_c6_v5.1' into 'release/v5.1'
bootloader: fix BOD and glitch reset on C6 and H2 (v5.1)

See merge request espressif/esp-idf!23380
2023-04-26 13:09:32 +08:00
Laukik Hase
16f3317496 soc/esp32s3: Fix the SOC_MEM_INTERNAL_HIGH value
- As per the memory block diagram for ESP32-S3, the
  internal memory address ranges as follows:
  DRAM: 0x3FC88000 (== SOC_MEM_INTERNAL_LOW) <-> 0x3FCF0000
  IRAM: 0x40378000 <-> 0x403E0000 (== SOC_MEM_INTERNAL_HIGH)
2023-04-26 04:01:38 +00:00
Ivan Grokhotkov
5b18007d92 sdmmc: I/O phase adjustments
1. Fix incorrect meaning of SDMMC.clock bits, synchronize the names
   with the TRM.
2. Choose input and output phases to satisfy typical timing
   requirements.
3. Move use_hold_reg setting into the host driver, since it is related
   to timing.

Closes https://github.com/espressif/esp-idf/issues/8521
Related to https://github.com/espressif/esp-idf/issues/8257
2023-04-24 03:45:29 +00:00
Xiao Xufeng
ca3d871a21 bootloader: fixed super watchdog not enabled issue on C3, S3, H4 2023-04-24 11:32:23 +08:00
cje
93eeb4265c fix chip broken bug when run in monitor mode of S2 and modify voltage param to fit all sleep mode of S2/C2/C3 2023-04-24 10:37:57 +08:00
Jiang Jiang Jian
badf267022 Merge branch 'bugfix/block9_can_not_be_used_for_fe' into 'master'
efuse: Prevent burning XTS_AES and ECDSA keys into BLOCK9 (BLOCK_KEY5)

Closes IDF-7175

See merge request espressif/esp-idf!23052
2023-04-06 10:17:07 +08:00
KonstantinKondrashov
5b00d1f396 efuse: Update efuses for esp32 esp32c2 esp32c3 esp32s2 esp32s3 2023-04-04 22:32:32 +08:00
KonstantinKondrashov
3d695b9768 efuse: Prevent burning XTS_AES and ECDSA keys into BLOCK9 (BLOCK_KEY5)
eFuse module has a hardware bug.
It is related to ESP32-C3, C6, S3, H2 chips:
    - BLOCK9 (BLOCK_KEY5) can not be used by XTS_AES keys.
For H2 chips, the BLOCK9 (BLOCK_KEY5) can not be used by ECDSA keys.
S2 does not have such a hardware bug.
2023-04-04 18:45:48 +08:00
Mahavir Jain
f22daec784 Merge branch 'feature/secure_set_efuses_to_prevent_brick_chip' into 'master'
security: write-protect DIS_ICAHE and DIS_DCACHE

Closes IDF-5177

See merge request espressif/esp-idf!22640
2023-03-29 11:51:09 +08:00
KonstantinKondrashov
723b2e86e5 security: write-protect DIS_ICAHE and DIS_DCACHE
Closes IDF-5177
2023-03-29 00:02:24 +08:00
Jiang Jiang Jian
b6fda9723e Merge branch 'bugfix/fix_att_rsp_timeout' into 'master'
Fixed bluedroid host ATT Ignore wrong response error

Closes BLEQABR23-30 and BT-3224

See merge request espressif/esp-idf!22688
2023-03-23 17:10:54 +08:00
zhiweijian
7ad9e885e4 If it is not 32 chips, hide the configuration item:BT_BLE_RPA_SUPPORTED 2023-03-20 15:54:32 +08:00
Roman Leonov
0b08570ae2 usb: usb_reg.h update missing register description 2023-03-14 13:29:20 +01:00
Jiang Jiang Jian
abc43d8e94 Merge branch 'bugfix/some_small_fix_for_sleep' into 'master'
esp_hw_support/sleep: update soc caps for chips that support power down modem

Closes WIFI-4424

See merge request espressif/esp-idf!20198
2023-03-13 10:47:26 +08:00
jingli
cb0f517fe3 soc/soc_caps: update soc caps for chips that support power-down of modem hardware
Closes WIFI-4424
2023-03-10 14:15:27 +08:00
Song Ruo Jing
79f34fe524 ledc: Support gamma curve fade feature on esp32c6 and esp32h2 2023-03-10 12:42:46 +08:00
Rahul Tank
8fc0343e5a Merge branch 'bugfix/modify_configuration_for_ble_5' into 'master'
Nimble: Update example configuration to enable ext adv feature only for BLE5.0 supported chips

See merge request espressif/esp-idf!22409
2023-03-10 12:35:39 +08:00