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external coex: rename coex gpio struct field names

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This commit is contained in:
muhaidong 2023-05-08 16:22:30 +08:00
parent 5cd0b6216a
commit 2f56bd8aac
17 changed files with 288 additions and 494 deletions
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2
components/esp_coex/Kconfig
View File

@ -17,7 +17,7 @@ menu "Wireless Coexistence"
config ESP_COEX_EXTERNAL_COEXIST_ENABLE
bool "External Coexistence"
default n
depends on (!(BT_ENABLED||NIMBLE_ENABLED)&&(!IDF_TARGET_ESP32)&&(!IDF_TARGET_ESP32C6)) #JIRA FCC52
depends on (!(BT_ENABLED||NIMBLE_ENABLED)&&(!IDF_TARGET_ESP32))
help
If enabled, HW External coexistence arbitration is managed by GPIO pins.
It can support three types of wired combinations so far which are 1-wired/2-wired/3-wired.

67
components/esp_coex/include/esp_coexist.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,6 +9,7 @@
#include <stdbool.h>
#include "esp_err.h"
#include "hal/gpio_types.h"
#ifdef __cplusplus
extern "C" {
@ -46,12 +47,25 @@ typedef enum {
* @brief external coex gpio pti
*/
typedef struct {
uint32_t in_pin0;
uint32_t in_pin1;
uint32_t out_pin0;
uint32_t out_pin1;
union {
uint32_t in_pin0 __attribute__((deprecated("Use 'request' instead")));
gpio_num_t request; /**< request gpio signal from slave to master */
};
union {
uint32_t in_pin1 __attribute__((deprecated("Use 'priority' instead")));
gpio_num_t priority; /**< request gpio signal priority from slave to master */
};
union {
uint32_t out_pin0 __attribute__((deprecated("Use 'grant' instead")));
gpio_num_t grant; /**< grant gpio signal from master to slave */
};
union {
uint32_t out_pin1 __attribute__((deprecated("Use 'tx_line' instead")));
gpio_num_t tx_line; /**< tx_line gpio signal from master to slave, indicates whether the master's WiFi is transmitting or not*/
};
} esp_external_coex_gpio_set_t;
/**
* @brief external coex pti level
*/
@ -61,14 +75,6 @@ typedef enum {
EXTERN_COEX_PTI_NUM,
} esp_coex_pti_level_t;
/**
* @brief external coex follower pti
*/
typedef struct {
uint32_t pti_val1;
uint32_t pti_val2;
} esp_external_coex_follower_pti_t;
/**
* @brief external coex role
*/
@ -78,18 +84,6 @@ typedef enum {
EXTERNAL_COEX_UNKNOWN_ROLE,
} esp_extern_coex_work_mode_t;
/**
* @brief external coex wiretype & role composition
*/
typedef enum {
wire_3_leader_mode = 0,
wire_2_leader_mode,
wire_1_leader_mode,
wire_3_follower_mode,
wire_2_follower_mode,
wire_1_follower_mode,
} external_coex_classification;
/**
* @brief external coex advance setup
*/
@ -144,6 +138,13 @@ esp_err_t esp_coex_status_bit_set(esp_coex_status_type_t type, uint32_t status);
esp_err_t esp_coex_status_bit_clear(esp_coex_status_type_t type, uint32_t status);
#if CONFIG_EXTERNAL_COEX_ENABLE
/**
* @brief Configure work mode, the default work mode is leader role.
* @param work_mode : work mode.
* @return : ESP_OK - success, other - failed
*/
esp_err_t esp_external_coex_set_work_mode(esp_extern_coex_work_mode_t work_mode);
/**
* @brief Setup gpio pin and corresponding pti level, start external coex,
* the default work mode is leader role, the default output grant validate pin is high,
@ -169,8 +170,8 @@ esp_err_t esp_disable_extern_coex_gpio_pin();
* @param gpio_pin : gpio pin number to select.
* @return : ESP_OK - success, other - failed
*/
esp_err_t esp_external_coex_leader_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t in_pin0,
uint32_t in_pin1, uint32_t out_pin0, uint32_t out_pin1);
esp_err_t esp_external_coex_leader_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t request, uint32_t priority,
uint32_t grant) __attribute__((deprecated("Please use esp_external_coex_set_work_mode and esp_enable_extern_coex_gpio_pin instead")));
/**
* @brief Configure follower work mode, gpio pin correspondly and finally enable external coex,
@ -179,8 +180,8 @@ esp_err_t esp_external_coex_leader_role_set_gpio_pin(external_coex_wire_t wire_t
* @param gpio_pin : gpio pin number to select.
* @return : ESP_OK - success, other - failed
*/
esp_err_t esp_external_coex_follower_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t in_pin0, uint32_t in_pin1,
uint32_t out_pin0, uint32_t out_pin1);
esp_err_t esp_external_coex_follower_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t request, uint32_t priority,
uint32_t grant) __attribute__((deprecated("Please use esp_external_coex_set_work_mode and esp_enable_extern_coex_gpio_pin instead")));
/**
* @brief Configure output grant signal latency in delay microseconds only for leader role of external coex,
@ -199,12 +200,8 @@ esp_err_t esp_external_coex_set_grant_delay(uint8_t delay_us);
* @return : ESP_OK - success, other - failed
*/
esp_err_t esp_external_coex_set_validate_high(bool is_high_valid);
#else
esp_err_t esp_extern_coex_register_txline(uint32_t pin);
esp_err_t esp_extern_coex_unregister_txline(void);
#endif
#endif
#endif /* SOC_EXTERNAL_COEX_ADVANCE */
#endif /* CONFIG_EXTERNAL_COEX_ENABLE */
#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED
/**

18
components/esp_coex/include/esp_coexist_internal.h
View File

@ -306,26 +306,12 @@ esp_err_t esp_coex_adapter_register(coex_adapter_funcs_t *funcs);
#if CONFIG_EXTERNAL_COEX_ENABLE
/**
* @brief Force RX Anttena only in external coex situation.
*/
extern void phy_coex_force_rx_ant(void);
/**
* @brief Dismiss RX Anttena only in external coex situation.
*/
extern void phy_coex_dismiss_rx_ant(void);
/**
* @brief Set external coexistence advanced informations, like working mode and grant mode in which level.
*
* @param outpti1 Only for slave mode, external coex output priority in level1.
* @param output2 Only for slave mode, external coex output priority in level2.
* @brief Set external coexistence advanced informations, like working mode.
*
* @return
* - ESP_OK: succeed
*/
esp_err_t esp_coex_external_params(esp_external_coex_advance_t coex_info,
uint32_t out_pti1, uint32_t out_pti2);
esp_err_t esp_coex_external_params(esp_external_coex_advance_t coex_info);
/**
* @brief Set external coexistence pti level and enable it.

607
components/esp_coex/src/coexist.c
View File

@ -16,12 +16,22 @@
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "esp_attr.h"
#ifdef CONFIG_IDF_TARGET_ESP32S3
#include "esp_rom/include/esp32s3/rom/gpio.h"
#endif
#endif
//static const char* TAG = "coexist";
#if SOC_EXTERNAL_COEX_ADVANCE
#define EXTERNAL_COEX_SIGNAL_I0_IDX EXTERN_ACTIVE_I_IDX
#define EXTERNAL_COEX_SIGNAL_I1_IDX EXTERN_PRIORITY_I_IDX
#define EXTERNAL_COEX_SIGNAL_O0_IDX EXTERN_ACTIVE_O_IDX
#define EXTERNAL_COEX_SIGNAL_O1_IDX EXTERN_PRIORITY_O_IDX
#else
#define EXTERNAL_COEX_SIGNAL_I0_IDX GPIO_BT_ACTIVE_IDX
#define EXTERNAL_COEX_SIGNAL_I1_IDX GPIO_BT_PRIORITY_IDX
#define EXTERNAL_COEX_SIGNAL_O0_IDX GPIO_WLAN_ACTIVE_IDX
#endif
#if SOC_EXTERNAL_COEX_LEADER_TX_LINE
#define EXTERNAL_COEX_SIGNAL_O1_TXLINE_IDX BB_DIAG9_IDX
#endif
const char *esp_coex_version_get(void)
{
@ -35,497 +45,232 @@ esp_err_t esp_coex_preference_set(esp_coex_prefer_t prefer)
#if CONFIG_EXTERNAL_COEX_ENABLE
#define GPIO_PIN_REG(a) (GPIO_PIN0_REG + a * 0x04)
#if SOC_EXTERNAL_COEX_ADVANCE
static const char *TAG = "external_coex";
external_coex_classification s_external_coex_partner[EXTERNAL_COEX_UNKNOWN_ROLE][EXTERN_COEX_WIRE_NUM] = {
{ wire_1_leader_mode, wire_2_leader_mode, wire_3_leader_mode },
{},
{ wire_1_follower_mode, wire_2_follower_mode, wire_3_follower_mode },
};
static esp_external_coex_advance_t g_external_coex_params = { EXTERNAL_COEX_LEADER_ROLE, 0, true };
esp_external_coex_follower_pti_t g_external_coex_follower_pti_val = { 0, 0 };
esp_err_t esp_external_coex_set_work_mode(esp_extern_coex_work_mode_t work_mode)
{
g_external_coex_params.work_mode = work_mode;
if(EXTERNAL_COEX_FOLLOWER_ROLE == work_mode) {
g_external_coex_follower_pti_val.pti_val1 = 8;
g_external_coex_follower_pti_val.pti_val2 = 12;
#if !SOC_EXTERNAL_COEX_ADVANCE
if(work_mode != EXTERNAL_COEX_LEADER_ROLE)
{
return ESP_ERR_INVALID_ARG;
}
#endif
g_external_coex_params.work_mode = work_mode;
return ESP_OK;
}
bool is_legal_external_coex_gpio(external_coex_wire_t wire_type, esp_external_coex_gpio_set_t gpio_pin)
{
switch (wire_type)
{
case EXTERN_COEX_WIRE_4:
{
if(!GPIO_IS_VALID_GPIO(gpio_pin.tx_line)
|| gpio_pin.tx_line == gpio_pin.priority || gpio_pin.tx_line == gpio_pin.grant || gpio_pin.tx_line == gpio_pin.request) {
return false;
}
}
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_3:
{
if(!GPIO_IS_VALID_GPIO(gpio_pin.priority) || gpio_pin.priority == gpio_pin.grant || gpio_pin.priority == gpio_pin.request) {
return false;
}
}
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_2:
{
if(!GPIO_IS_VALID_GPIO(gpio_pin.grant) || gpio_pin.grant == gpio_pin.request) {
return false;
}
}
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_1:
{
if(!GPIO_IS_VALID_GPIO(gpio_pin.request)) {
return false;
}
break;
}
default:
return false;
}
return true;
}
#if SOC_EXTERNAL_COEX_ADVANCE
esp_err_t esp_external_coex_set_gpio_pin(esp_external_coex_gpio_set_t *gpio_pin, external_coex_wire_t wire_type, uint32_t request, uint32_t priority, uint32_t grant)
{
switch (wire_type) {
case EXTERN_COEX_WIRE_3:
gpio_pin->priority = priority;
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_2:
gpio_pin->grant = grant;
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_1:
{
gpio_pin->request = request;
break;
}
default:
{
gpio_pin->request = request;
gpio_pin->priority = priority;
gpio_pin->grant = grant;
break;
}
}
return ESP_OK;
}
esp_err_t esp_external_coex_set_grant_delay(uint8_t delay_us)
{
g_external_coex_params.delay_us = delay_us;
return ESP_OK;
}
esp_err_t esp_external_coex_set_validate_high(bool is_high_valid)
{
g_external_coex_params.is_high_valid = is_high_valid;
return ESP_OK;
}
bool is_legal_external_coex_gpio(external_coex_wire_t wire_type, esp_external_coex_gpio_set_t gpio_pin)
{
external_coex_classification external_coex_configure = s_external_coex_partner[g_external_coex_params.work_mode][wire_type];
switch (external_coex_configure)
{
case wire_3_leader_mode:
{
if(gpio_pin.in_pin0 == gpio_pin.in_pin1) {
return false;
}
if(gpio_pin.in_pin0 == gpio_pin.out_pin0) {
return false;
}
if(gpio_pin.in_pin1 == gpio_pin.out_pin0) {
return false;
}
if(gpio_pin.in_pin0 >= SOC_GPIO_PIN_COUNT) {
return false;
}
if(gpio_pin.in_pin1 >= SOC_GPIO_PIN_COUNT) {
return false;
}
if(gpio_pin.out_pin0 >= SOC_GPIO_PIN_COUNT) {
return false;
}
return true;
}
case wire_3_follower_mode:
{
if(gpio_pin.in_pin0 == gpio_pin.out_pin0) {
return false;
}
if(gpio_pin.in_pin0 == gpio_pin.out_pin1) {
return false;
}
if(gpio_pin.out_pin0 == gpio_pin.out_pin1) {
return false;
}
if(gpio_pin.in_pin0 >= SOC_GPIO_PIN_COUNT) {
return false;
}
if(gpio_pin.out_pin1 >= SOC_GPIO_PIN_COUNT) {
return false;
}
if(gpio_pin.out_pin0 >= SOC_GPIO_PIN_COUNT) {
return false;
}
return true;
}
case wire_2_leader_mode:
case wire_2_follower_mode:
{
if(gpio_pin.in_pin0 == gpio_pin.out_pin0) {
return false;
}
if(gpio_pin.in_pin0 >= SOC_GPIO_PIN_COUNT) {
return false;
}
if(gpio_pin.out_pin0 >= SOC_GPIO_PIN_COUNT) {
return false;
}
return true;
}
case wire_1_leader_mode:
{
if(gpio_pin.in_pin0 >= SOC_GPIO_PIN_COUNT) {
return false;
}
return true;
}
case wire_1_follower_mode:
{
if(gpio_pin.out_pin0 >= SOC_GPIO_PIN_COUNT) {
return false;
}
return true;
}
default:
return false;
}
}
esp_err_t esp_external_coex_leader_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t in_pin0, uint32_t in_pin1, uint32_t out_pin0, uint32_t out_pin1)
esp_err_t esp_external_coex_leader_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t request, uint32_t priority, uint32_t grant)
{
esp_external_coex_set_work_mode(EXTERNAL_COEX_LEADER_ROLE);
esp_external_coex_gpio_set_t gpio_pin;
switch (wire_type) {
case EXTERN_COEX_WIRE_4:
{
gpio_pin.in_pin0 = in_pin0;
gpio_pin.in_pin1 = in_pin1;
gpio_pin.out_pin0 = out_pin0;
gpio_pin.out_pin1 = out_pin1;
break;
}
case EXTERN_COEX_WIRE_3:
{
gpio_pin.in_pin0 = in_pin0;
gpio_pin.in_pin1 = in_pin1;
gpio_pin.out_pin0 = out_pin0;
break;
}
case EXTERN_COEX_WIRE_2:
{
gpio_pin.in_pin0 = in_pin0;
gpio_pin.out_pin0 = out_pin0;
break;
}
case EXTERN_COEX_WIRE_1:
{
gpio_pin.in_pin0 = in_pin0;
break;
}
default:
{
gpio_pin.in_pin0 = in_pin0;
gpio_pin.in_pin1 = in_pin1;
gpio_pin.out_pin0 = out_pin0;
break;
}
}
esp_external_coex_set_gpio_pin(&gpio_pin, wire_type, request, priority, grant);
return esp_enable_extern_coex_gpio_pin(wire_type, gpio_pin);
}
esp_err_t esp_external_coex_follower_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t in_pin0, uint32_t in_pin1, uint32_t out_pin0, uint32_t out_pin1)
esp_err_t esp_external_coex_follower_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t request, uint32_t priority, uint32_t grant)
{
esp_external_coex_set_work_mode(EXTERNAL_COEX_FOLLOWER_ROLE);
esp_external_coex_gpio_set_t gpio_pin;
switch (wire_type) {
case EXTERN_COEX_WIRE_4:
{
gpio_pin.in_pin0 = in_pin0;
gpio_pin.in_pin1 = in_pin1;
gpio_pin.out_pin0 = out_pin0;
gpio_pin.out_pin1 = out_pin1;
break;
}
case EXTERN_COEX_WIRE_3:
{
gpio_pin.in_pin0 = in_pin0;
gpio_pin.out_pin0 = out_pin0;
gpio_pin.out_pin1 = out_pin1;
break;
}
case EXTERN_COEX_WIRE_2:
{
gpio_pin.in_pin0 = in_pin0;
gpio_pin.out_pin0 = out_pin0;
break;
}
case EXTERN_COEX_WIRE_1:
{
gpio_pin.out_pin0 = out_pin0;
break;
}
default:
{
gpio_pin.in_pin0 = in_pin0;
gpio_pin.out_pin0 = out_pin0;
gpio_pin.out_pin1 = out_pin1;
break;
}
}
esp_external_coex_set_gpio_pin(&gpio_pin, wire_type, request, priority, grant);
return esp_enable_extern_coex_gpio_pin(wire_type, gpio_pin);
}
#endif
#endif /* SOC_EXTERNAL_COEX_ADVANCE */
esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_external_coex_gpio_set_t gpio_pin)
{
#if SOC_EXTERNAL_COEX_ADVANCE
if(false == is_legal_external_coex_gpio(wire_type, gpio_pin))
{
ESP_LOGE(TAG, "Configure external coex with unexpected gpio pin!!!\n");
return ESP_ERR_INVALID_ARG;
}
phy_coex_force_rx_ant(); // TO DO: esp32h2 /esp32c6 remove and add a common forece rx API
esp_coex_external_params(g_external_coex_params, g_external_coex_follower_pti_val.pti_val1,
g_external_coex_follower_pti_val.pti_val2);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_coex_external_params(g_external_coex_params);
#endif
switch (wire_type)
{
case EXTERN_COEX_WIRE_4:
if(EXTERNAL_COEX_LEADER_ROLE == g_external_coex_params.work_mode) {
switch (wire_type)
{
#if SOC_EXTERNAL_COEX_ADVANCE
if(EXTERNAL_COEX_LEADER_ROLE == g_external_coex_params.work_mode) {
#if SOC_EXTERNAL_COEX_LEADER_TX_LINE
case EXTERN_COEX_WIRE_4:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.tx_line], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.tx_line));
esp_rom_gpio_connect_out_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_O1_TXLINE_IDX, false, false);
}
__attribute__((fallthrough));
#endif
/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX：GPIO_BT_ACTIVE_IDX*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
#else
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
#endif
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin1], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin1, GPIO_MODE_INPUT);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, EXTERN_PRIORITY_I_IDX, false);
#else
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, GPIO_BT_PRIORITY_IDX, false);
#endif
/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
#else
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, GPIO_WLAN_ACTIVE_IDX, false, false);
#endif
#ifndef SOC_EXTERNAL_COEX_ADVANCE
esp_extern_coex_register_txline(gpio_pin.out_pin1); // For leader mode, set wifi txline
#endif
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC2_BYPASS, 2);
#if SOC_EXTERNAL_COEX_ADVANCE
}
else if(EXTERNAL_COEX_FOLLOWER_ROLE == g_external_coex_params.work_mode) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin1], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin1, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, EXTERN_PRIORITY_I_IDX, false);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin1], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin1, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin1));
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin1, EXTERN_PRIORITY_O_IDX, false, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
}
#else
#endif
int ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
if (ESP_OK != ret) {
case EXTERN_COEX_WIRE_3:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.priority], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.priority, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC2_BYPASS, 2);
}
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_2:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.grant], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.grant, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.grant));
esp_rom_gpio_connect_out_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_O0_IDX, false, false);
}
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_1:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.request], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.request, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC2_BYPASS, 2);
break;
}
default:
{
return ESP_FAIL;
}
break;
}
case EXTERN_COEX_WIRE_3:
} else if(EXTERNAL_COEX_FOLLOWER_ROLE == g_external_coex_params.work_mode) {
#if SOC_EXTERNAL_COEX_ADVANCE
switch (wire_type)
{
#if SOC_EXTERNAL_COEX_ADVANCE
if(EXTERNAL_COEX_LEADER_ROLE == g_external_coex_params.work_mode) {
#endif
/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX：GPIO_BT_ACTIVE_IDX*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
#else
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
#endif
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin1], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin1, GPIO_MODE_INPUT);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, EXTERN_PRIORITY_I_IDX, false);
#else
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, GPIO_BT_PRIORITY_IDX, false);
#endif
/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
#else
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, GPIO_WLAN_ACTIVE_IDX, false, false);
#endif
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC2_BYPASS, 2);
#if SOC_EXTERNAL_COEX_ADVANCE
}
else if(EXTERNAL_COEX_FOLLOWER_ROLE == g_external_coex_params.work_mode) {
/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX：GPIO_BT_ACTIVE_IDX*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin1], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin1, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin1));
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin1, EXTERN_PRIORITY_O_IDX, false, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
}
#else
#endif
int ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
if (ESP_OK != ret) {
case EXTERN_COEX_WIRE_4:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.tx_line], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC2_BYPASS, 2);
}
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_3:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.priority], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.priority, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.priority));
esp_rom_gpio_connect_out_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_O1_IDX, false, false);
}
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_2:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.grant], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.grant, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC2_BYPASS, 2);
}
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_1:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.request], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.request, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.request));
esp_rom_gpio_connect_out_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_O0_IDX, false, false);
break;
}
default:
{
return ESP_FAIL;
}
break;
}
case EXTERN_COEX_WIRE_2:
{
/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX：GPIO_BT_ACTIVE_IDX*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
#else
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
#endif
/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
#else
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, GPIO_WLAN_ACTIVE_IDX, false, false);
#endif
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
int ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID);
if (ESP_OK != ret) {
return ESP_FAIL;
}
break;
}
case EXTERN_COEX_WIRE_1:
{
#if SOC_EXTERNAL_COEX_ADVANCE
if(EXTERNAL_COEX_LEADER_ROLE == g_external_coex_params.work_mode) {
#endif
/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX：GPIO_BT_ACTIVE_IDX*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
#else
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
#endif
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
#if SOC_EXTERNAL_COEX_ADVANCE
}
else if(EXTERNAL_COEX_FOLLOWER_ROLE == g_external_coex_params.work_mode) {
/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
}
#else
#endif
int ret = esp_coex_external_set(EXTERN_COEX_PTI_HIGH, EXTERN_COEX_PTI_HIGH, EXTERN_COEX_PTI_HIGH);
if (ESP_OK != ret) {
return ESP_FAIL;
}
break;
}
default:
{
return ESP_FAIL;
}
#endif /* SOC_EXTERNAL_COEX_ADVANCE */
return ESP_ERR_INVALID_ARG;
}
int ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
if (ESP_OK != ret) {
return ESP_FAIL;
}
return ESP_OK;
}
esp_err_t esp_disable_extern_coex_gpio_pin()
{
#if SOC_EXTERNAL_COEX_ADVANCE
phy_coex_dismiss_rx_ant();
#endif
esp_coex_external_stop();
return ESP_OK;
}
#ifndef SOC_EXTERNAL_COEX_ADVANCE
#define ESP_EXTERN_COEX_OUTPIN_UNDEF 0xFFFF
DRAM_ATTR static uint32_t esp_extern_coex_outpin = ESP_EXTERN_COEX_OUTPIN_UNDEF;
esp_err_t esp_extern_coex_register_txline(uint32_t pin)
{
esp_extern_coex_outpin = pin;
gpio_config_t io_conf = {
//disable interrupt
.intr_type = GPIO_INTR_DISABLE,
//set as output mode
.mode = GPIO_MODE_OUTPUT,
//bit mask of the pins that you want to set,e.g.GPIO18/19
.pin_bit_mask = (1ULL << esp_extern_coex_outpin),
//disable pull-down mode
.pull_down_en = GPIO_PULLDOWN_DISABLE,
//enable pull-up mode
.pull_up_en = GPIO_PULLUP_ENABLE,
};
gpio_config(&io_conf);
ESP_LOGI(TAG, "external coex select output io %d as txline", esp_extern_coex_outpin);
esp_rom_gpio_matrix_out(esp_extern_coex_outpin, BB_DIAG9_IDX, false, false);
return ESP_OK;
}
esp_err_t esp_extern_coex_unregister_txline(void)
{
/* Do nothing here */
return ESP_OK;
}
#endif
#endif/*External Coex*/
#endif /* External Coex */
#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED
esp_err_t esp_coex_wifi_i154_enable(void)

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@ -591,6 +591,10 @@ config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

5
components/soc/esp32c2/include/soc/soc_caps.h
View File

@ -275,8 +275,9 @@
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*-------------------------- HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS -------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

8
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@ -855,6 +855,14 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default n
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

4
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -376,6 +376,10 @@
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (0) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)

8
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -1087,6 +1087,14 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

4
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -449,6 +449,10 @@
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

8
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -1063,6 +1063,14 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

4
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -443,6 +443,10 @@
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
// TODO: IDF-6337
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

8
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@ -1047,6 +1047,14 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default n
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default y
config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
bool
default y

4
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -450,6 +450,10 @@
/* ---------------------------- Compatibility ------------------------------- */
// No contents
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (0) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (1) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)

8
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -1195,6 +1195,14 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default n
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default y
config SOC_SDMMC_USE_GPIO_MATRIX
bool
default y

4
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -480,6 +480,10 @@
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (0) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (1) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*-------------------------- SDMMC CAPS -----------------------------------------*/
/* Card detect, write protect, interrupt use GPIO Matrix on all chips.

19
examples/wifi/iperf/main/cmd_wifi.c
View File

@ -173,17 +173,18 @@ void initialise_wifi(void)
#if CONFIG_EXTERNAL_COEX_ENABLE
#if SOC_EXTERNAL_COEX_ADVANCE
uint32_t in_pin0 = 1;
uint32_t in_pin1 = 2;
uint32_t out_pin0 = 3;
ESP_ERROR_CHECK( esp_external_coex_leader_role_set_gpio_pin(EXTERN_COEX_WIRE_3, in_pin0, in_pin1, out_pin0) );
uint32_t request = 1;
uint32_t priority = 2;
uint32_t grant = 3;
ESP_ERROR_CHECK(esp_external_coex_leader_role_set_gpio_pin(EXTERN_COEX_WIRE_3, request, priority, grant));
#else
esp_external_coex_gpio_set_t gpio_pin;
gpio_pin.in_pin0 = 1;
gpio_pin.in_pin1 = 2;
gpio_pin.out_pin0 = 3;
gpio_pin.out_pin1 = 4;
ESP_ERROR_CHECK( esp_enable_extern_coex_gpio_pin(EXTERN_COEX_WIRE_4, gpio_pin) );
gpio_pin.request = 1;
gpio_pin.priority = 2;
gpio_pin.grant = 3;
gpio_pin.tx_line = 4;
esp_external_coex_set_work_mode(EXTERNAL_COEX_LEADER_ROLE);
ESP_ERROR_CHECK(esp_enable_extern_coex_gpio_pin(EXTERN_COEX_WIRE_4, gpio_pin));
#endif
#endif