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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
fix(spi): correct some signals and dummy bits docs
This commit is contained in:
wanlei
parent
8e0d64e94c
commit
3486cf1b60
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,29 +12,30 @@
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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.spiclk_out = SPICLK_OUT_MUX_IDX,
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spid_out = SPID_OUT_IDX,
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.spiq_out = SPIQ_OUT_IDX,
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.spiwp_out = SPIWP_OUT_IDX,
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.spihd_out = SPIHD_OUT_IDX,
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.spid_in = SPID_IN_IDX,
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.spiq_in = SPIQ_IN_IDX,
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.spiwp_in = SPIWP_IN_IDX,
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.spihd_in = SPIHD_IN_IDX,
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.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_SPI1_INTR_SOURCE,
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// MSPI has dedicated iomux pins
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.spiclk_out = -1,
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.spiclk_in = -1,
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.spid_out = -1,
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.spiq_out = -1,
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = -1,
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.spiq_in = -1,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {-1},
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.spics_in = -1,
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = -1,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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.module = -1,
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.hw = NULL,
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.func = -1,
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}, {
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.spiclk_out = FSPICLK_OUT_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,29 +12,30 @@
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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.spiclk_out = SPICLK_OUT_MUX_IDX,
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spid_out = SPID_OUT_IDX,
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.spiq_out = SPIQ_OUT_IDX,
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.spiwp_out = SPIWP_OUT_IDX,
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.spihd_out = SPIHD_OUT_IDX,
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.spid_in = SPID_IN_IDX,
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.spiq_in = SPIQ_IN_IDX,
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.spiwp_in = SPIWP_IN_IDX,
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.spihd_in = SPIHD_IN_IDX,
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.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_SPI1_INTR_SOURCE,
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// MSPI has dedicated iomux pins
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.spiclk_out = -1,
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.spiclk_in = -1,
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.spid_out = -1,
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.spiq_out = -1,
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = -1,
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.spiq_in = -1,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {-1},
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.spics_in = -1,
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = -1,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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.module = -1,
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.hw = NULL,
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.func = -1,
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}, {
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.spiclk_out = FSPICLK_OUT_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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@ -343,7 +343,6 @@
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#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
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#define SOC_SDM_CLK_SUPPORT_XTAL 1
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// TODO: IDF-5334 (Copy from esp32c3, need check)
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 6
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,20 +12,31 @@
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_MSPI_INTR_SOURCE,
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// MSPI has dedicated iomux pins
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.spiclk_out = -1,
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.spiclk_in = -1,
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.spid_out = -1,
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.spiq_out = -1,
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = -1,
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.spiq_in = -1,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {-1},
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.spics_in = -1,
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = -1,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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}, { // TODO: IDF-5334 Need check
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.module = -1,
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.hw = NULL,
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.func = -1,
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}, {
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.spiclk_out = FSPICLK_OUT_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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.spid_out = FSPID_OUT_IDX,
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@ -339,7 +339,6 @@
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#define SOC_SDM_CLK_SUPPORT_PLL_F48M 1
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#define SOC_SDM_CLK_SUPPORT_XTAL 1
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// TODO: IDF-6245 (Copy from esp32c6, need check)
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 6
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -11,20 +11,31 @@
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Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{// ESP32H2-TODO: IDF-6245 Need check
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_MSPI_INTR_SOURCE,
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{
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// MSPI has dedicated iomux pins
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.spiclk_out = -1,
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.spiclk_in = -1,
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.spid_out = -1,
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.spiq_out = -1,
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = -1,
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.spiq_in = -1,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {-1},
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.spics_in = -1,
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = -1,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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.module = -1,
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.hw = NULL,
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.func = -1,
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}, {
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.spiclk_out = FSPICLK_OUT_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,29 +12,30 @@
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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.spiclk_out = SPICLK_OUT_IDX,
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spid_out = SPID_OUT_IDX,
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.spiq_out = SPIQ_OUT_IDX,
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.spiwp_out = SPIWP_OUT_IDX,
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.spihd_out = SPIHD_OUT_IDX,
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.spid_in = SPID_IN_IDX,
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.spiq_in = SPIQ_IN_IDX,
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.spiwp_in = SPIWP_IN_IDX,
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.spihd_in = SPIHD_IN_IDX,
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.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_SPI1_INTR_SOURCE,
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// MSPI has dedicated iomux pins
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.spiclk_out = -1,
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.spiclk_in = -1,
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.spid_out = -1,
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.spiq_out = -1,
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = -1,
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.spiq_in = -1,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {-1},
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.spics_in = -1,
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = -1,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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.module = -1,
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.hw = NULL,
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.func = -1,
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}, {
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.spiclk_out = FSPICLK_OUT_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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@ -40,9 +40,17 @@ In the half duplex mode, the master has to use the protocol defined by the slave
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For some commands (WRBUF, RDBUF), this phase specifies the address of the shared buffer to write to/read from. For other commands with this phase, they are meaningless but still have to exist in the transaction.
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- Dummy: 8-bit, floating, optional
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.. only:: esp32s2
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This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
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- Dummy: 8-bit (for 1-bit mode) or 4-bit (for 2/4-bit mode), floating, optional
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This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
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.. only:: not esp32s2
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- Dummy: 8-bit, floating, optional
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This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
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- Data: variable length, the direction is also determined by the command.
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@ -1 +1 @@
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.. include:: ../../../en/api-reference/protocols/esp_spi_slave_protocol.rst
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.. include:: ../../../en/api-reference/protocols/esp_spi_slave_protocol.rst
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