mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
Merge branch 'contrib/github_pr_12559_v5.1' into 'release/v5.1'
fix(spi): Correct REG_SPI_BASE(i) macro for all targets (GitHub PR) (v5.1) See merge request espressif/esp-idf!27714
This commit is contained in:
morris
commit
eb7022dd06
@ -30,6 +30,7 @@
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#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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//Registers Operation {{
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@ -6,12 +6,11 @@
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#ifndef _SOC_SPI_REG_H_
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#define _SOC_SPI_REG_H_
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc/soc.h"
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#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000)
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#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
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/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
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@ -16,7 +16,6 @@ PROVIDE ( LEDC = 0x60019000 );
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PROVIDE ( TIMERG0 = 0x6001F000 );
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PROVIDE ( SYSTIMER = 0x60023000 );
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PROVIDE ( GPSPI2 = 0x60024000 );
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PROVIDE ( GPSPI3 = 0x60025000 );
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PROVIDE ( SYSCON = 0x60026000 );
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PROVIDE ( APB_SARADC = 0x60040000 );
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PROVIDE ( GDMA = 0x6003F000 );
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,29 +12,30 @@
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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.spiclk_out = SPICLK_OUT_MUX_IDX,
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spid_out = SPID_OUT_IDX,
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.spiq_out = SPIQ_OUT_IDX,
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.spiwp_out = SPIWP_OUT_IDX,
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.spihd_out = SPIHD_OUT_IDX,
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.spid_in = SPID_IN_IDX,
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.spiq_in = SPIQ_IN_IDX,
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.spiwp_in = SPIWP_IN_IDX,
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.spihd_in = SPIHD_IN_IDX,
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.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_SPI1_INTR_SOURCE,
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// MSPI has dedicated iomux pins
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.spiclk_out = -1,
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.spiclk_in = -1,
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.spid_out = -1,
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.spiq_out = -1,
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = -1,
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.spiq_in = -1,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {-1},
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.spics_in = -1,
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = -1,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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.module = -1,
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.hw = NULL,
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.func = -1,
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}, {
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.spiclk_out = FSPICLK_OUT_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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@ -23,6 +23,7 @@
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#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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//Registers Operation {{
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@ -1,24 +1,16 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_SPI_REG_H_
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#define _SOC_SPI_REG_H_
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#include "soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc.h"
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#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
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/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
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@ -26,10 +26,8 @@ PROVIDE ( TIMERG0 = 0x6001F000 );
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PROVIDE ( TIMERG1 = 0x60020000 );
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PROVIDE ( SYSTIMER = 0x60023000 );
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PROVIDE ( GPSPI2 = 0x60024000 );
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PROVIDE ( GPSPI3 = 0x60025000 );
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PROVIDE ( SYSCON = 0x60026000 );
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PROVIDE ( TWAI = 0x6002B000 );
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PROVIDE ( GPSPI4 = 0x60037000 );
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PROVIDE ( APB_SARADC = 0x60040000 );
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PROVIDE ( USB_SERIAL_JTAG = 0x60043000 );
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PROVIDE ( GDMA = 0x6003F000 );
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,29 +12,30 @@
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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.spiclk_out = SPICLK_OUT_MUX_IDX,
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spid_out = SPID_OUT_IDX,
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.spiq_out = SPIQ_OUT_IDX,
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.spiwp_out = SPIWP_OUT_IDX,
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.spihd_out = SPIHD_OUT_IDX,
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.spid_in = SPID_IN_IDX,
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.spiq_in = SPIQ_IN_IDX,
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.spiwp_in = SPIWP_IN_IDX,
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.spihd_in = SPIHD_IN_IDX,
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.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_SPI1_INTR_SOURCE,
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// MSPI has dedicated iomux pins
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.spiclk_out = -1,
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.spiclk_in = -1,
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.spid_out = -1,
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.spiq_out = -1,
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = -1,
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.spiq_in = -1,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {-1},
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.spics_in = -1,
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = -1,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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.module = -1,
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.hw = NULL,
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.func = -1,
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}, {
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.spiclk_out = FSPICLK_OUT_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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@ -23,10 +23,10 @@
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#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
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#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6
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#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6
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#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6
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#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1
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#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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@ -343,7 +343,6 @@
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#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
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#define SOC_SDM_CLK_SUPPORT_XTAL 1
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// TODO: IDF-5334 (Copy from esp32c3, need check)
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 6
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,20 +12,31 @@
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_MSPI_INTR_SOURCE,
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// MSPI has dedicated iomux pins
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.spiclk_out = -1,
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.spiclk_in = -1,
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.spid_out = -1,
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.spiq_out = -1,
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = -1,
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.spiq_in = -1,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {-1},
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.spics_in = -1,
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
|
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.spiq_iomux_pin = -1,
|
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
|
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.spics0_iomux_pin = -1,
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.irq = -1,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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}, { // TODO: IDF-5334 Need check
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.module = -1,
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.hw = NULL,
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.func = -1,
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}, {
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.spiclk_out = FSPICLK_OUT_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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.spid_out = FSPID_OUT_IDX,
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@ -23,8 +23,8 @@
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#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000)
|
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#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
|
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)
|
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#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000)
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|
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
|
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@ -339,7 +339,6 @@
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#define SOC_SDM_CLK_SUPPORT_PLL_F48M 1
|
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#define SOC_SDM_CLK_SUPPORT_XTAL 1
|
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|
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// TODO: IDF-6245 (Copy from esp32c6, need check)
|
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 6
|
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|
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@ -1,5 +1,5 @@
|
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/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
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@ -11,20 +11,31 @@
|
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Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
|
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*/
|
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
|
||||
{// ESP32H2-TODO: IDF-6245 Need check
|
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.spiclk_in = 0,/* SPI clock is not an input signal*/
|
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.spics_in = 0,/* SPI cs is not an input signal*/
|
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
|
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
|
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
|
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
|
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
|
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
|
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.irq = ETS_MSPI_INTR_SOURCE,
|
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{
|
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// MSPI has dedicated iomux pins
|
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.spiclk_out = -1,
|
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.spiclk_in = -1,
|
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.spid_out = -1,
|
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.spiq_out = -1,
|
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.spiwp_out = -1,
|
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.spihd_out = -1,
|
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.spid_in = -1,
|
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.spiq_in = -1,
|
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.spiwp_in = -1,
|
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.spihd_in = -1,
|
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.spics_out = {-1},
|
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.spics_in = -1,
|
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.spiclk_iomux_pin = -1,
|
||||
.spid_iomux_pin = -1,
|
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.spiq_iomux_pin = -1,
|
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.spiwp_iomux_pin = -1,
|
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.spihd_iomux_pin = -1,
|
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.spics0_iomux_pin = -1,
|
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.irq = -1,
|
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.irq_dma = -1,
|
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.module = PERIPH_SPI_MODULE,
|
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.hw = (spi_dev_t *) &SPIMEM1,
|
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.func = SPI_FUNC_NUM,
|
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.module = -1,
|
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.hw = NULL,
|
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.func = -1,
|
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}, {
|
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.spiclk_out = FSPICLK_OUT_IDX,
|
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.spiclk_in = FSPICLK_IN_IDX,
|
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|
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@ -56,7 +56,6 @@
|
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#define DR_REG_SYSCON_BASE 0x3f426000
|
||||
#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
|
||||
#define DR_REG_I2C1_EXT_BASE 0x3f427000
|
||||
#define DR_REG_SPI4_BASE 0x3f437000
|
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#define DR_REG_USB_WRAP_BASE 0x3f439000
|
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#define DR_REG_APB_SARADC_BASE 0x3f440000
|
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#define DR_REG_USB_BASE 0x60080000
|
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|
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@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -18,14 +18,15 @@
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
|
||||
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
|
||||
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
|
||||
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
|
||||
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
|
||||
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
|
||||
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
|
||||
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
|
||||
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
|
||||
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
|
||||
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
|
||||
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
|
||||
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
|
||||
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
|
||||
|
||||
//Convenient way to replace the register ops when ulp riscv projects
|
||||
//consume this file
|
||||
|
||||
@ -1,25 +1,16 @@
|
||||
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_SPI_MEM_REG_H_
|
||||
#define _SOC_SPI_MEM_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
|
||||
|
||||
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000)
|
||||
/* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
|
||||
@ -1,25 +1,16 @@
|
||||
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_SPI_REG_H_
|
||||
#define _SOC_SPI_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 )))
|
||||
|
||||
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000)
|
||||
/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -27,14 +27,15 @@
|
||||
#define DR_REG_EXT_MEM_ENC 0x600CC000
|
||||
|
||||
|
||||
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
|
||||
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
|
||||
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
|
||||
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
|
||||
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
|
||||
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
|
||||
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
|
||||
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
|
||||
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
|
||||
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
|
||||
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
|
||||
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
|
||||
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
|
||||
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
|
||||
|
||||
//Convenient way to replace the register ops when ulp riscv projects
|
||||
//consume this file
|
||||
|
||||
@ -38,7 +38,6 @@ PROVIDE ( SYSCON = 0x60026000 );
|
||||
PROVIDE ( I2C1 = 0x60027000 );
|
||||
PROVIDE ( SDMMC = 0x60028000 );
|
||||
PROVIDE ( TWAI = 0x6002B000 );
|
||||
PROVIDE ( GPSPI4 = 0x60037000 );
|
||||
PROVIDE ( GDMA = 0x6003F000 );
|
||||
PROVIDE ( UART2 = 0x6002E000 );
|
||||
PROVIDE ( DMA = 0x6003F000 );
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -12,29 +12,30 @@
|
||||
*/
|
||||
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
|
||||
{
|
||||
.spiclk_out = SPICLK_OUT_IDX,
|
||||
.spiclk_in = 0,/* SPI clock is not an input signal*/
|
||||
.spid_out = SPID_OUT_IDX,
|
||||
.spiq_out = SPIQ_OUT_IDX,
|
||||
.spiwp_out = SPIWP_OUT_IDX,
|
||||
.spihd_out = SPIHD_OUT_IDX,
|
||||
.spid_in = SPID_IN_IDX,
|
||||
.spiq_in = SPIQ_IN_IDX,
|
||||
.spiwp_in = SPIWP_IN_IDX,
|
||||
.spihd_in = SPIHD_IN_IDX,
|
||||
.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
|
||||
.spics_in = 0,/* SPI cs is not an input signal*/
|
||||
.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
|
||||
.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
|
||||
.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
|
||||
.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
|
||||
.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
|
||||
.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
|
||||
.irq = ETS_SPI1_INTR_SOURCE,
|
||||
// MSPI has dedicated iomux pins
|
||||
.spiclk_out = -1,
|
||||
.spiclk_in = -1,
|
||||
.spid_out = -1,
|
||||
.spiq_out = -1,
|
||||
.spiwp_out = -1,
|
||||
.spihd_out = -1,
|
||||
.spid_in = -1,
|
||||
.spiq_in = -1,
|
||||
.spiwp_in = -1,
|
||||
.spihd_in = -1,
|
||||
.spics_out = {-1},
|
||||
.spics_in = -1,
|
||||
.spiclk_iomux_pin = -1,
|
||||
.spid_iomux_pin = -1,
|
||||
.spiq_iomux_pin = -1,
|
||||
.spiwp_iomux_pin = -1,
|
||||
.spihd_iomux_pin = -1,
|
||||
.spics0_iomux_pin = -1,
|
||||
.irq = -1,
|
||||
.irq_dma = -1,
|
||||
.module = PERIPH_SPI_MODULE,
|
||||
.hw = (spi_dev_t *) &SPIMEM1,
|
||||
.func = SPI_FUNC_NUM,
|
||||
.module = -1,
|
||||
.hw = NULL,
|
||||
.func = -1,
|
||||
}, {
|
||||
.spiclk_out = FSPICLK_OUT_IDX,
|
||||
.spiclk_in = FSPICLK_IN_IDX,
|
||||
|
||||
@ -40,9 +40,17 @@ In the half duplex mode, the master has to use the protocol defined by the slave
|
||||
|
||||
For some commands (WRBUF, RDBUF), this phase specifies the address of the shared buffer to write to/read from. For other commands with this phase, they are meaningless but still have to exist in the transaction.
|
||||
|
||||
- Dummy: 8-bit, floating, optional
|
||||
.. only:: esp32s2
|
||||
|
||||
This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
|
||||
- Dummy: 8-bit (for 1-bit mode) or 4-bit (for 2/4-bit mode), floating, optional
|
||||
|
||||
This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
|
||||
|
||||
.. only:: not esp32s2
|
||||
|
||||
- Dummy: 8-bit, floating, optional
|
||||
|
||||
This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
|
||||
|
||||
- Data: variable length, the direction is also determined by the command.
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
.. include:: ../../../en/api-reference/protocols/esp_spi_slave_protocol.rst
|
||||
.. include:: ../../../en/api-reference/protocols/esp_spi_slave_protocol.rst
|
||||
|
||||
@ -834,7 +834,6 @@ components/soc/esp32c3/include/soc/sensitive_struct.h
|
||||
components/soc/esp32c3/include/soc/soc_pins.h
|
||||
components/soc/esp32c3/include/soc/spi_mem_reg.h
|
||||
components/soc/esp32c3/include/soc/spi_pins.h
|
||||
components/soc/esp32c3/include/soc/spi_reg.h
|
||||
components/soc/esp32c3/include/soc/system_reg.h
|
||||
components/soc/esp32c3/include/soc/system_struct.h
|
||||
components/soc/esp32c3/include/soc/systimer_reg.h
|
||||
@ -877,9 +876,7 @@ components/soc/esp32s2/include/soc/sdmmc_pins.h
|
||||
components/soc/esp32s2/include/soc/sens_reg.h
|
||||
components/soc/esp32s2/include/soc/sensitive_reg.h
|
||||
components/soc/esp32s2/include/soc/soc_ulp.h
|
||||
components/soc/esp32s2/include/soc/spi_mem_reg.h
|
||||
components/soc/esp32s2/include/soc/spi_pins.h
|
||||
components/soc/esp32s2/include/soc/spi_reg.h
|
||||
components/soc/esp32s2/include/soc/systimer_reg.h
|
||||
components/soc/esp32s2/include/soc/systimer_struct.h
|
||||
components/soc/esp32s2/include/soc/touch_sensor_channel.h
|
||||
|
||||
Loading…
Reference in New Issue
Block a user