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Merge branch 'bugfix/fix_lightsleep_current_leakage_on_usj_pad_v5.1' into 'release/v5.1'

Browse Source 
fix(esp_hw_support): fix lightsleep current leakage on usb pad (backport v5.1)

See merge request espressif/esp-idf!27205
This commit is contained in:
Jiang Jiang Jian 2023-11-21 10:51:11 +08:00
commit 0e1ec38785
18 changed files with 394 additions and 15 deletions
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9
components/bootloader_support/src/bootloader_console.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -18,6 +18,9 @@
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_common.h"
#endif
#if SOC_USB_SERIAL_JTAG_SUPPORTED
#include "hal/usb_phy_ll.h"
#endif
#include "esp_rom_gpio.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
@ -97,6 +100,10 @@ void bootloader_console_init(void)
esp_rom_uart_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
esp_rom_uart_set_as_console(ESP_ROM_UART_USB);
esp_rom_install_channel_putc(1, bootloader_console_write_char_usb);
#if SOC_USB_SERIAL_JTAG_SUPPORTED
usb_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true);
usb_phy_ll_int_otg_enable(&USB_WRAP);
#endif
}
#endif //CONFIG_ESP_CONSOLE_USB_CDC

4
components/driver/usb_serial_jtag/usb_serial_jtag.c
View File

@ -151,6 +151,9 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se
goto _exit;
}
// Enable USB-Serial-JTAG peripheral module clock
usb_serial_jtag_ll_enable_bus_clock(true);
// Configure PHY
usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
@ -214,6 +217,7 @@ esp_err_t usb_serial_jtag_driver_uninstall(void)
return ESP_OK;
}
/* Not disable the module clock and usb_pad_enable here since the USJ stdout might still depends on it. */
//Disable tx/rx interrupt.
usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY | USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
esp_intr_free(p_usb_serial_jtag_obj->intr_handle);

1
components/esp_hw_support/CMakeLists.txt
View File

@ -27,6 +27,7 @@ if(NOT BOOTLOADER_BUILD)
"revision.c"
"rtc_module.c"
"sleep_modes.c"
"sleep_console.c"
"sleep_gpio.c"
"sleep_event.c"
"sleep_modem.c"

35
components/esp_hw_support/include/esp_private/sleep_console.h Normal file
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@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_USB_SERIAL_JTAG_SUPPORTED
typedef struct {
bool usj_clock_enabled;
bool usj_pad_enabled;
} sleep_console_usj_enable_state_t;
/**
* @brief Disable usb-serial-jtag pad during light sleep to avoid current leakage and
* backup the enable state before light sleep
*/
void sleep_console_usj_pad_backup_and_disable(void);
/**
* @brief Restore initial usb-serial-jtag pad enable state when wakeup from light sleep
*/
void sleep_console_usj_pad_restore(void);
#endif
#ifdef __cplusplus
}
#endif

2
components/esp_hw_support/linker.lf
View File

@ -23,6 +23,8 @@ entries:
rtc_time (noflash_text)
if SOC_PMU_SUPPORTED = y:
pmu_sleep (noflash)
if SOC_USB_SERIAL_JTAG_SUPPORTED = y:
sleep_console (noflash)
if PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32 = n:
sleep_modem:periph_inform_out_light_sleep_overhead (noflash)
if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y:

38
components/esp_hw_support/sleep_console.c Normal file
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@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "soc/soc_caps.h"
#include "esp_private/sleep_console.h"
#include "esp_attr.h"
#if SOC_USB_SERIAL_JTAG_SUPPORTED
#include "hal/usb_serial_jtag_ll.h"
static sleep_console_usj_enable_state_t s_usj_state = {0};
void sleep_console_usj_pad_backup_and_disable(void)
{
s_usj_state.usj_clock_enabled = usb_serial_jtag_ll_module_is_enabled();
if (!s_usj_state.usj_clock_enabled) {
// Enable USJ clock and clear reset
usb_serial_jtag_ll_enable_bus_clock(true);
usb_serial_jtag_ll_reset_register();
}
s_usj_state.usj_pad_enabled = usb_serial_jtag_ll_pad_backup_and_disable();
// Disable USJ clock
usb_serial_jtag_ll_enable_bus_clock(false);
}
void sleep_console_usj_pad_restore(void)
{
usb_serial_jtag_ll_enable_bus_clock(true);
usb_serial_jtag_ll_enable_pad(s_usj_state.usj_pad_enabled);
if (!s_usj_state.usj_clock_enabled) {
usb_serial_jtag_ll_enable_bus_clock(false);
}
}
#endif

8
components/esp_hw_support/sleep_modes.c
View File

@ -57,6 +57,7 @@
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp_private/brownout.h"
#include "esp_private/sleep_console.h"
#include "esp_private/sleep_cpu.h"
#include "esp_private/sleep_modem.h"
#include "esp_private/esp_clk.h"
@ -508,6 +509,10 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
}
}
} else {
#if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
// Only avoid USJ pad leakage here, USB OTG pad leakage is prevented through USB Host driver.
sleep_console_usj_pad_backup_and_disable();
#endif
#if CONFIG_MAC_BB_PD
mac_bb_power_down_cb_execute();
#endif
@ -536,6 +541,9 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
*/
inline static void IRAM_ATTR misc_modules_wake_prepare(void)
{
#if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
sleep_console_usj_pad_restore();
#endif
#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG
sleep_retention_do_system_retention(false);
#endif

58
components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,8 +7,11 @@
// The LL layer of the USB-serial-jtag controller
#pragma once
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
@ -168,6 +171,59 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
USB_SERIAL_JTAG.ep1_conf.wr_done=1;
}
/**
* @brief Disable usb serial jtag pad during light sleep to avoid current leakage
*
* @return Initial configuration of usb serial jtag pad enable before light sleep
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
{
bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
// Disable USB pad function
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
return pad_enabled;
}
/**
* @brief Enable the internal USJ PHY control to D+/D- pad
*
* @param enable_pad Enable the USJ PHY control to D+/D- pad
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
{
USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
}
/**
* @brief Enable the bus clock for USB Serial_JTAG module
* @param clk_en True if enable the clock of USB Serial_JTAG module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
{
SYSTEM.perip_clk_en0.reg_usb_device_clk_en = clk_en;
}
/**
* @brief Reset the usb serial jtag module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void)
{
SYSTEM.perip_rst_en0.reg_usb_device_rst = 1;
SYSTEM.perip_rst_en0.reg_usb_device_rst = 0;
}
/**
* Get the enable status USB Serial_JTAG module
*
* @return Return true if USB Serial_JTAG module is enabled
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void)
{
return (SYSTEM.perip_clk_en0.reg_usb_device_clk_en && !SYSTEM.perip_rst_en0.reg_usb_device_rst);
}
#ifdef __cplusplus
}

56
components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h
View File

@ -7,6 +7,9 @@
// The LL layer of the USB-serial-jtag controller
#pragma once
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/pcr_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
@ -169,6 +172,59 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
}
/**
* @brief Disable usb serial jtag pad during light sleep to avoid current leakage
*
* @return Initial configuration of usb serial jtag pad enable before light sleep
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
{
bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
// Disable USB pad function
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
return pad_enabled;
}
/**
* @brief Enable the internal USJ PHY control to D+/D- pad
*
* @param enable_pad Enable the USJ PHY control to D+/D- pad
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
{
USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
}
/**
* @brief Enable the bus clock for USB Serial_JTAG module
* @param clk_en True if enable the clock of USB Serial_JTAG module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
{
PCR.usb_device_conf.usb_device_clk_en = clk_en;
}
/**
* @brief Reset the usb serial jtag module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void)
{
PCR.usb_device_conf.usb_device_rst_en = 1;
PCR.usb_device_conf.usb_device_rst_en = 0;
}
/**
* Get the enable status USB Serial_JTAG module
*
* @return Return true if USB Serial_JTAG module is enabled
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void)
{
return (PCR.usb_device_conf.usb_device_clk_en && !PCR.usb_device_conf.usb_device_rst_en);
}
#ifdef __cplusplus
}
#endif

55
components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
View File

@ -7,6 +7,9 @@
// The LL layer of the USB-serial-jtag controller
#pragma once
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/pcr_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
@ -168,6 +171,58 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
USB_SERIAL_JTAG.ep1_conf.wr_done=1;
}
/**
* @brief Disable usb serial jtag pad during light sleep to avoid current leakage
*
* @return Initial configuration of usb serial jtag pad enable before light sleep
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
{
bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
// Disable USB pad function
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
return pad_enabled;
}
/**
* @brief Enable the internal USJ PHY control to D+/D- pad
*
* @param enable_pad Enable the USJ PHY control to D+/D- pad
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
{
USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
}
/**
* @brief Enable the bus clock for USB Serial_JTAG module
* @param clk_en True if enable the clock of USB Serial_JTAG module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
{
PCR.usb_device_conf.usb_device_clk_en = clk_en;
}
/**
* @brief Reset the usb serial jtag module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void)
{
PCR.usb_device_conf.usb_device_rst_en = 1;
PCR.usb_device_conf.usb_device_rst_en = 0;
}
/**
* Get the enable status USB Serial_JTAG module
*
* @return Return true if USB Serial_JTAG module is enabled
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void)
{
return (PCR.usb_device_conf.usb_device_clk_en && !PCR.usb_device_conf.usb_device_rst_en);
}
#ifdef __cplusplus
}

33
components/hal/esp32s2/include/hal/usb_phy_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,6 +7,7 @@
#pragma once
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/system_reg.h"
#include "soc/usb_wrap_struct.h"
@ -22,8 +23,6 @@ extern "C" {
*/
static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
{
//Enable internal PHY
hw->otg_conf.pad_enable = 1;
hw->otg_conf.phy_sel = 0;
}
@ -58,6 +57,16 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool
hw->otg_conf = conf;
}
/**
* @brief Enable the internal PHY control to D+/D- pad
* @param hw Start address of the USB Wrap registers
* @param pad_en Enable the PHY control to D+/D- pad
*/
static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
{
hw->otg_conf.pad_enable = pad_en;
}
/**
* @brief Enable the internal PHY's test mode
*
@ -78,6 +87,24 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
}
}
/**
* Enable the bus clock for USB Wrap module
* @param clk_en True if enable the clock of USB Wrap module
*/
FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
{
REG_SET_FIELD(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN, clk_en);
}
/**
* @brief Reset the USB Wrap module
*/
FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void)
{
REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 1);
REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 0);
}
#ifdef __cplusplus
}
#endif

34
components/hal/esp32s3/include/hal/usb_phy_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,8 +7,9 @@
#pragma once
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/system_reg.h"
#include "soc/system_struct.h"
#include "soc/usb_wrap_struct.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/usb_serial_jtag_struct.h"
@ -24,7 +25,6 @@ extern "C" {
*/
static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
{
hw->otg_conf.pad_enable = 1;
// USB_OTG use internal PHY
hw->otg_conf.phy_sel = 0;
// phy_sel is controlled by the following register value
@ -104,6 +104,16 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool
hw->otg_conf = conf;
}
/**
* @brief Enable the internal PHY control to D+/D- pad
* @param hw Start address of the USB Wrap registers
* @param pad_en Enable the PHY control to D+/D- pad
*/
static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
{
hw->otg_conf.pad_enable = pad_en;
}
/**
* @brief Enable the internal PHY's test mode
*
@ -124,6 +134,24 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
}
}
/**
* Enable the bus clock for USB Wrap module
* @param clk_en True if enable the clock of USB Wrap module
*/
FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
{
SYSTEM.perip_clk_en0.usb_clk_en = clk_en;
}
/**
* @brief Reset the USB Wrap module
*/
FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void)
{
SYSTEM.perip_rst_en0.usb_rst = 1;
SYSTEM.perip_rst_en0.usb_rst = 0;
}
#ifdef __cplusplus
}
#endif

57
components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,6 +7,9 @@
// The LL layer of the USB-serial-jtag controller
#pragma once
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/system_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
@ -165,6 +168,58 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
USB_SERIAL_JTAG.ep1_conf.wr_done=1;
}
/**
* @brief Disable usb serial jtag pad during light sleep to avoid current leakage
*
* @return Initial configuration of usb serial jtag pad enable before light sleep
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
{
bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
// Disable USB pad function
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
return pad_enabled;
}
/**
* @brief Enable the internal USJ PHY control to D+/D- pad
*
* @param enable_pad Enable the USJ PHY control to D+/D- pad
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
{
USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
}
/**
* @brief Enable the bus clock for USB Serial_JTAG module
* @param clk_en True if enable the clock of USB Serial_JTAG module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
{
SYSTEM.perip_clk_en1.usb_device_clk_en = clk_en;
}
/**
* @brief Reset the usb serial jtag module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void)
{
SYSTEM.perip_rst_en1.usb_device_rst = 1;
SYSTEM.perip_rst_en1.usb_device_rst = 0;
}
/**
* Get the enable status USB Serial_JTAG module
*
* @return Return true if USB Serial_JTAG module is enabled
*/
FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void)
{
return (SYSTEM.perip_clk_en1.usb_device_clk_en && !SYSTEM.perip_rst_en1.usb_device_rst);
}
#ifdef __cplusplus
}

1
components/hal/usb_phy_hal.c
View File

@ -20,6 +20,7 @@ void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_targe
if (phy_target == USB_PHY_TARGET_EXT) {
usb_phy_ll_ext_otg_enable(hal->wrap_dev);
} else if (phy_target == USB_PHY_TARGET_INT) {
usb_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true);
usb_phy_ll_int_otg_enable(hal->wrap_dev);
}
}

1
components/soc/esp32c2/ld/esp32c2.peripherals.ld
View File

@ -20,3 +20,4 @@ PROVIDE ( GPSPI3 = 0x60025000 );
PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( GDMA = 0x6003F000 );
PROVIDE ( SYSTEM = 0x600C0000 );

1
components/soc/esp32c3/ld/esp32c3.peripherals.ld
View File

@ -33,3 +33,4 @@ PROVIDE ( GPSPI4 = 0x60037000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( USB_SERIAL_JTAG = 0x60043000 );
PROVIDE ( GDMA = 0x6003F000 );
PROVIDE ( SYSTEM = 0x600C0000 );

1
components/soc/esp32s3/ld/esp32s3.peripherals.ld
View File

@ -49,3 +49,4 @@ PROVIDE ( USB0 = 0x60080000 );
PROVIDE ( USB_DWC = 0x60080000 );
PROVIDE ( USB_WRAP = 0x60039000 );
PROVIDE ( WORLD_CONTROLLER = 0x600D0000 );
PROVIDE ( SYSTEM = 0x600C0000 );

15
components/usb/usb_phy.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -17,6 +17,7 @@
#include "esp_rom_gpio.h"
#include "driver/gpio.h"
#include "hal/gpio_ll.h"
#include "soc/soc_caps.h"
#include "soc/usb_pins.h"
static const char *USBPHY_TAG = "usb_phy";
@ -219,9 +220,10 @@ static esp_err_t usb_phy_install(void)
portEXIT_CRITICAL(&phy_spinlock);
goto cleanup;
}
usb_phy_ll_usb_wrap_enable_bus_clock(true);
usb_phy_ll_usb_wrap_reset_register();
// Enable USB peripheral and reset the register
portEXIT_CRITICAL(&phy_spinlock);
periph_module_enable(usb_otg_periph_signal.module);
periph_module_reset(usb_otg_periph_signal.module);
return ESP_OK;
cleanup:
@ -311,8 +313,8 @@ static void phy_uninstall(void)
if (p_phy_ctrl_obj->ref_count == 0) {
p_phy_ctrl_obj_free = p_phy_ctrl_obj;
p_phy_ctrl_obj = NULL;
// Disable USB peripheral
periph_module_disable(usb_otg_periph_signal.module);
// Disable USB peripheral without reset the module
usb_phy_ll_usb_wrap_enable_bus_clock(false);
}
portEXIT_CRITICAL(&phy_spinlock);
free(p_phy_ctrl_obj_free);
@ -327,8 +329,9 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle)
if (handle->target == USB_PHY_TARGET_EXT) {
p_phy_ctrl_obj->external_phy = NULL;
} else {
// Clear pullup and pulldown loads on D+ / D-
// Clear pullup and pulldown loads on D+ / D-, and disable the pads
usb_phy_ll_int_load_conf(handle->hal_context.wrap_dev, false, false, false, false);
usb_phy_ll_usb_wrap_pad_enable(handle->hal_context.wrap_dev, false);
p_phy_ctrl_obj->internal_phy = NULL;
}
portEXIT_CRITICAL(&phy_spinlock);