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Merge branch 'bugfix/s3_irom_addr_v5.1' into 'release/v5.1'
soc: fix SOC_IROM_MASK_HIGH for esp32s3 (v5.1) See merge request espressif/esp-idf!27136
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commit
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@ -176,7 +176,7 @@
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_IROM_MASK_LOW 0x40000000
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#define SOC_IROM_MASK_HIGH 0x40064F00
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#define SOC_IROM_MASK_HIGH 0x40070000
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#define SOC_CACHE_PRO_LOW 0x40070000
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#define SOC_CACHE_PRO_HIGH 0x40078000
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#define SOC_CACHE_APP_LOW 0x40078000
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@ -159,8 +159,8 @@
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#define SOC_DROM_LOW SOC_IROM_LOW
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#define SOC_DROM_HIGH SOC_IROM_HIGH
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#define SOC_IROM_MASK_LOW 0x40000000
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#define SOC_IROM_MASK_HIGH 0x4004AC00
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#define SOC_DROM_MASK_LOW 0x4004AC00
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#define SOC_IROM_MASK_HIGH 0x40050000
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#define SOC_DROM_MASK_LOW 0x40000000
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#define SOC_DROM_MASK_HIGH 0x40050000
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#define SOC_IRAM_LOW 0x40800000
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#define SOC_IRAM_HIGH 0x40880000
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -157,8 +157,8 @@
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#define SOC_DROM_LOW SOC_IROM_LOW
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#define SOC_DROM_HIGH SOC_IROM_HIGH
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#define SOC_IROM_MASK_LOW 0x40000000
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#define SOC_IROM_MASK_HIGH 0x4001C400
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#define SOC_DROM_MASK_LOW 0x4001C400
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#define SOC_IROM_MASK_HIGH 0x40020000
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#define SOC_DROM_MASK_LOW 0x40000000
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#define SOC_DROM_MASK_HIGH 0x40020000
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#define SOC_IRAM_LOW 0x40800000
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#define SOC_IRAM_HIGH 0x40850000
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@ -187,7 +187,7 @@
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#define SOC_EXTRAM_DATA_LOW 0x3C000000
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#define SOC_EXTRAM_DATA_HIGH 0x3E000000
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#define SOC_IROM_MASK_LOW 0x40000000
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#define SOC_IROM_MASK_HIGH 0x4001A100
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#define SOC_IROM_MASK_HIGH 0x40060000
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#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
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#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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