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efuse: Update efuses for esp32 esp32c2 esp32c3 esp32s2 esp32s3
This commit is contained in:
KonstantinKondrashov
parent
ab5d8d0008
commit
5b00d1f396
File diff suppressed because it is too large
Load Diff
@ -1,95 +1,123 @@
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# field_name, | efuse_block, | bit_start, | bit_count, |comment #
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# | (EFUSE_BLK0 | (0..255) | (1..-) | #
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# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
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# | EFUSE_BLK2 | | | #
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# | EFUSE_BLK3) | | | #
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# | (EFUSE_BLK0 | (0..255) | (1-256) | #
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# | EFUSE_BLK1 | | | #
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# | ...) | | | #
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##########################################################################
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# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
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# !!!!!!!!!!! #
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# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
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# After editing this file, run the command manually "idf.py efuse-common-table"
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# Factory MAC address #
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#######################
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MAC_FACTORY, EFUSE_BLK0, 72, 8, Factory MAC addr [0]
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, EFUSE_BLK0, 64, 8, Factory MAC addr [1]
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, EFUSE_BLK0, 56, 8, Factory MAC addr [2]
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, EFUSE_BLK0, 48, 8, Factory MAC addr [3]
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, EFUSE_BLK0, 40, 8, Factory MAC addr [4]
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, EFUSE_BLK0, 32, 8, Factory MAC addr [5]
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MAC_FACTORY_CRC, EFUSE_BLK0, 80, 8, CRC8 for factory MAC address
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# This file was generated by regtools.py based on the efuses.yaml file with the version: 369d2d860d34e777c0f7d545a7dfc3c4
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# Custom MAC address #
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######################
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MAC_CUSTOM_CRC, EFUSE_BLK3, 0, 8, CRC8 for custom MAC address.
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MAC_CUSTOM, EFUSE_BLK3, 8, 48, Custom MAC
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MAC_CUSTOM_VER, EFUSE_BLK3, 184, 8, Custom MAC version
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# Security boot #
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#################
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SECURE_BOOT_KEY, EFUSE_BLK2, 0, MAX_BLK_LEN, Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128)
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ABS_DONE_0, EFUSE_BLK0, 196, 1, Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0
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ABS_DONE_1, EFUSE_BLK0, 197, 1, Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1
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# Flash encrypt #
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#################
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ENCRYPT_FLASH_KEY, EFUSE_BLK1, 0, MAX_BLK_LEN, Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128)
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ENCRYPT_CONFIG, EFUSE_BLK0, 188, 4, Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M
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DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT.
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DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT.
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DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE.
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FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT.
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# Misc Security #
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DISABLE_JTAG, EFUSE_BLK0, 198, 1, Disable JTAG. EFUSE_RD_DISABLE_JTAG.
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CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE.
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UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, Disable UART download mode. Valid for ESP32 V3 and newer, only.
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# Write protection #
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####################
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WR_DIS, EFUSE_BLK0, 0, 16, [] Efuse write disable mask
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WR_DIS.EFUSE_RD_DISABLE,EFUSE_BLK0, 0, 1, Write protection for EFUSE_RD_DISABLE
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WR_DIS.FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, Flash encrypt. Write protection FLASH_CRYPT_CNT, UART_DOWNLOAD_DIS. EFUSE_WR_DIS_FLASH_CRYPT_CNT
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WR_DIS.DIS_CACHE, EFUSE_BLK0, 3, 1, [] wr_dis of DIS_CACHE
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WR_DIS.BLK1, EFUSE_BLK0, 7, 1, Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1
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WR_DIS.BLK2, EFUSE_BLK0, 8, 1, Security boot. Write protection security key. EFUSE_WR_DIS_BLK2
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WR_DIS.BLK3, EFUSE_BLK0, 9, 1, Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3
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# Read protection #
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###################
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RD_DIS_BLK1, EFUSE_BLK0, 16, 1, Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1
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RD_DIS_BLK2, EFUSE_BLK0, 17, 1, Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2
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RD_DIS_BLK3, EFUSE_BLK0, 18, 1, Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3
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# Chip info #
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#############
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CHIP_VER_DIS_APP_CPU, EFUSE_BLK0, 96, 1, EFUSE_RD_CHIP_VER_DIS_APP_CPU
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CHIP_VER_DIS_BT, EFUSE_BLK0, 97, 1, EFUSE_RD_CHIP_VER_DIS_BT
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CHIP_VER_PKG, EFUSE_BLK0, 105, 3, EFUSE_RD_CHIP_VER_PKG least significant bits
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, EFUSE_BLK0, 98, 1, EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit
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CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, EFUSE_RD_CHIP_CPU_FREQ_LOW
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CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, EFUSE_RD_CHIP_CPU_FREQ_RATED
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CHIP_VER_REV1, EFUSE_BLK0, 111, 1, EFUSE_RD_CHIP_VER_REV1
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CHIP_VER_REV2, EFUSE_BLK0, 180, 1, EFUSE_RD_CHIP_VER_REV2
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WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, WAFER_VERSION_MINOR
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XPD_SDIO_REG, EFUSE_BLK0, 142, 1, EFUSE_RD_XPD_SDIO_REG
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SDIO_TIEH, EFUSE_BLK0, 143, 1, EFUSE_RD_SDIO_TIEH
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SDIO_FORCE, EFUSE_BLK0, 144, 1, EFUSE_RD_SDIO_FORCE
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#SDIO_DREFH, EFUSE_BLK0, 136, 2, EFUSE_RD_SDIO_DREFH
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#SDIO_DREFM, EFUSE_BLK0, 138, 2, EFUSE_RD_SDIO_DREFM
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#SDIO_DREFL, EFUSE_BLK0, 140, 2, EFUSE_RD_SDIO_DREFL
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# esp_adc_cal #
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###############
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ADC_VREF_AND_SDIO_DREF, EFUSE_BLK0, 136, 6, EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1], SDIO_DREFM[2 3], SDIO_DREFL[4 5] )
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ADC1_TP_LOW, EFUSE_BLK3, 96, 7, TP_REG EFUSE_RD_ADC1_TP_LOW
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ADC2_TP_LOW, EFUSE_BLK3, 112, 7, TP_REG EFUSE_RD_ADC2_TP_LOW
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ADC1_TP_HIGH, EFUSE_BLK3, 103, 9, TP_REG EFUSE_RD_ADC1_TP_HIGH
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ADC2_TP_HIGH, EFUSE_BLK3, 119, 9, TP_REG EFUSE_RD_ADC2_TP_HIGH
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# anti-rollback #
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#################
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SECURE_VERSION, EFUSE_BLK3, 128, 32, Secure version for anti-rollback
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WR_DIS, EFUSE_BLK0, 0, 16, [] Efuse write disable mask
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS
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WR_DIS.WR_DIS, EFUSE_BLK0, 1, 1, [] wr_dis of WR_DIS
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WR_DIS.FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of FLASH_CRYPT_CNT
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WR_DIS.UART_DOWNLOAD_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of UART_DOWNLOAD_DIS
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WR_DIS.MAC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
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WR_DIS.MAC_CRC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC
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WR_DIS.DISABLE_APP_CPU, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU
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WR_DIS.DISABLE_BT, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT
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WR_DIS.DIS_CACHE, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE
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WR_DIS.VOL_LEVEL_HP_INV, EFUSE_BLK0, 3, 1, [] wr_dis of VOL_LEVEL_HP_INV
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WR_DIS.CLK8M_FREQ, EFUSE_BLK0, 4, 1, [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ
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WR_DIS.ADC_VREF, EFUSE_BLK0, 4, 1, [] wr_dis of ADC_VREF
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WR_DIS.XPD_SDIO_REG, EFUSE_BLK0, 5, 1, [] wr_dis of XPD_SDIO_REG
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WR_DIS.XPD_SDIO_TIEH, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH
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WR_DIS.XPD_SDIO_FORCE, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE
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WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CLK
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WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_Q
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WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_D
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WR_DIS.SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CS0
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WR_DIS.BLOCK1, EFUSE_BLK0, 7, 1, [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1
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WR_DIS.BLOCK2, EFUSE_BLK0, 8, 1, [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2
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WR_DIS.BLOCK3, EFUSE_BLK0, 9, 1, [WR_DIS.BLK3] wr_dis of BLOCK3
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WR_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC
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WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC
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WR_DIS.ADC1_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_LOW
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WR_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_HIGH
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WR_DIS.ADC2_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_LOW
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WR_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_HIGH
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WR_DIS.SECURE_VERSION, EFUSE_BLK0, 9, 1, [] wr_dis of SECURE_VERSION
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WR_DIS.MAC_VERSION, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION
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WR_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 10, 1, [] wr_dis of BLK3_PART_RESERVE
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WR_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 10, 1, [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG
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WR_DIS.CODING_SCHEME, EFUSE_BLK0, 10, 1, [] wr_dis of CODING_SCHEME
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WR_DIS.KEY_STATUS, EFUSE_BLK0, 10, 1, [] wr_dis of KEY_STATUS
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WR_DIS.ABS_DONE_0, EFUSE_BLK0, 12, 1, [] wr_dis of ABS_DONE_0
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WR_DIS.ABS_DONE_1, EFUSE_BLK0, 13, 1, [] wr_dis of ABS_DONE_1
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WR_DIS.JTAG_DISABLE, EFUSE_BLK0, 14, 1, [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE
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WR_DIS.CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 15, 1, [] wr_dis of CONSOLE_DEBUG_DISABLE
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WR_DIS.DISABLE_DL_ENCRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_ENCRYPT
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WR_DIS.DISABLE_DL_DECRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_DECRYPT
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WR_DIS.DISABLE_DL_CACHE, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_CACHE
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RD_DIS, EFUSE_BLK0, 16, 4, [] Disable reading from BlOCK1-3
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RD_DIS.BLOCK1, EFUSE_BLK0, 16, 1, [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1
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RD_DIS.BLOCK2, EFUSE_BLK0, 17, 1, [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2
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RD_DIS.BLOCK3, EFUSE_BLK0, 18, 1, [RD_DIS.BLK3] rd_dis of BLOCK3
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RD_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC
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RD_DIS.CUSTOM_MAC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC
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RD_DIS.ADC1_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_LOW
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RD_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_HIGH
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RD_DIS.ADC2_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_LOW
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RD_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_HIGH
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RD_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] rd_dis of SECURE_VERSION
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RD_DIS.MAC_VERSION, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION
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RD_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 19, 1, [] rd_dis of BLK3_PART_RESERVE
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RD_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 19, 1, [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG
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RD_DIS.CODING_SCHEME, EFUSE_BLK0, 19, 1, [] rd_dis of CODING_SCHEME
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RD_DIS.KEY_STATUS, EFUSE_BLK0, 19, 1, [] rd_dis of KEY_STATUS
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FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, [] Flash encryption is enabled if this field has an odd number of bits set
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UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, [] Disable UART download mode. Valid for ESP32 V3 and newer; only
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MAC, EFUSE_BLK0, 72, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK0, 64, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK0, 56, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK0, 48, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK0, 40, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK0, 32, 8, [MAC_FACTORY] MAC address
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MAC_CRC, EFUSE_BLK0, 80, 8, [MAC_FACTORY_CRC] CRC8 for MAC address
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DISABLE_APP_CPU, EFUSE_BLK0, 96, 1, [CHIP_VER_DIS_APP_CPU] Disables APP CPU
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DISABLE_BT, EFUSE_BLK0, 97, 1, [CHIP_VER_DIS_BT] Disables Bluetooth
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CHIP_PACKAGE_4BIT, EFUSE_BLK0, 98, 1, [CHIP_VER_PKG_4BIT] Chip package identifier #4bit
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DIS_CACHE, EFUSE_BLK0, 99, 1, [CHIP_VER_DIS_CACHE] Disables cache
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SPI_PAD_CONFIG_HD, EFUSE_BLK0, 100, 5, [] read for SPI_pad_config_hd
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CHIP_PACKAGE, EFUSE_BLK0, 105, 3, [CHIP_VER_PKG] Chip package identifier
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CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise
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CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, [] If set; the ESP32's maximum CPU frequency has been rated
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BLK3_PART_RESERVE, EFUSE_BLK0, 110, 1, [] BLOCK3 partially served for ADC calibration data
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CHIP_VER_REV1, EFUSE_BLK0, 111, 1, [] bit is set to 1 for rev1 silicon
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CLK8M_FREQ, EFUSE_BLK0, 128, 8, [CK8M_FREQ] 8MHz clock freq override
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ADC_VREF, EFUSE_BLK0, 136, 5, [] True ADC reference voltage
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XPD_SDIO_REG, EFUSE_BLK0, 142, 1, [] read for XPD_SDIO_REG
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XPD_SDIO_TIEH, EFUSE_BLK0, 143, 1, [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"}
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XPD_SDIO_FORCE, EFUSE_BLK0, 144, 1, [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset
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SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 160, 5, [] Override SD_CLK pad (GPIO6/SPICLK)
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SPI_PAD_CONFIG_Q, EFUSE_BLK0, 165, 5, [] Override SD_DATA_0 pad (GPIO7/SPIQ)
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SPI_PAD_CONFIG_D, EFUSE_BLK0, 170, 5, [] Override SD_DATA_1 pad (GPIO8/SPID)
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SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 175, 5, [] Override SD_CMD pad (GPIO11/SPICS0)
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CHIP_VER_REV2, EFUSE_BLK0, 180, 1, []
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VOL_LEVEL_HP_INV, EFUSE_BLK0, 182, 2, [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
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WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, []
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FLASH_CRYPT_CONFIG, EFUSE_BLK0, 188, 4, [ENCRYPT_CONFIG] Flash encryption config (key tweak bits)
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CODING_SCHEME, EFUSE_BLK0, 192, 2, [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"}
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CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, [] Disable ROM BASIC interpreter fallback
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DISABLE_SDIO_HOST, EFUSE_BLK0, 195, 1, []
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ABS_DONE_0, EFUSE_BLK0, 196, 1, [] Secure boot V1 is enabled for bootloader image
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ABS_DONE_1, EFUSE_BLK0, 197, 1, [] Secure boot V2 is enabled for bootloader image
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JTAG_DISABLE, EFUSE_BLK0, 198, 1, [DISABLE_JTAG] Disable JTAG
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DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, [] Disable flash encryption in UART bootloader
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DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, [] Disable flash decryption in UART bootloader
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DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, [] Disable flash cache in UART bootloader
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KEY_STATUS, EFUSE_BLK0, 202, 1, [] Usage of efuse block 3 (reserved)
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BLOCK1, EFUSE_BLK1, 0, MAX_BLK_LEN, [ENCRYPT_FLASH_KEY] Flash encryption key
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BLOCK2, EFUSE_BLK2, 0, MAX_BLK_LEN, [SECURE_BOOT_KEY] Security boot key
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CUSTOM_MAC_CRC, EFUSE_BLK3, 0, 8, [MAC_CUSTOM_CRC] CRC8 for custom MAC address
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MAC_CUSTOM, EFUSE_BLK3, 8, 48, [MAC_CUSTOM] Custom MAC address
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ADC1_TP_LOW, EFUSE_BLK3, 96, 7, [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
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ADC1_TP_HIGH, EFUSE_BLK3, 103, 9, [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
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ADC2_TP_LOW, EFUSE_BLK3, 112, 7, [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
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ADC2_TP_HIGH, EFUSE_BLK3, 119, 9, [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
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SECURE_VERSION, EFUSE_BLK3, 128, 32, [] Secure version for anti-rollback
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MAC_VERSION, EFUSE_BLK3, 184, 8, [MAC_CUSTOM_VER] Version of the MAC field {1: "Custom MAC in BLOCK3"}
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Can't render this file because it contains an unexpected character in line 7 and column 87.
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@ -10,57 +10,163 @@ extern "C" {
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#include "esp_efuse.h"
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// md5_digest_table c5ac3aa2d3a97d98ced4f4fccf48c328
|
||||
// md5_digest_table 2e197b7b14eec62fa5bdf94c6d71e87a
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY_CRC[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_CRC[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_VER[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
#define ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE ESP_EFUSE_WR_DIS_RD_DIS
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_DOWNLOAD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_CRC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY_CRC ESP_EFUSE_WR_DIS_MAC_CRC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_APP_CPU[];
|
||||
#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_APP_CPU ESP_EFUSE_WR_DIS_DISABLE_APP_CPU
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BT[];
|
||||
#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_BT ESP_EFUSE_WR_DIS_DISABLE_BT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_CACHE[];
|
||||
#define ESP_EFUSE_WR_DIS_CHIP_VER_DIS_CACHE ESP_EFUSE_WR_DIS_DIS_CACHE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VOL_LEVEL_HP_INV[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CLK8M_FREQ[];
|
||||
#define ESP_EFUSE_WR_DIS_CK8M_FREQ ESP_EFUSE_WR_DIS_CLK8M_FREQ
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_VREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_REG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_TIEH[];
|
||||
#define ESP_EFUSE_WR_DIS_SDIO_TIEH ESP_EFUSE_WR_DIS_XPD_SDIO_TIEH
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XPD_SDIO_FORCE[];
|
||||
#define ESP_EFUSE_WR_DIS_SDIO_FORCE ESP_EFUSE_WR_DIS_XPD_SDIO_FORCE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK1[];
|
||||
#define ESP_EFUSE_WR_DIS_ENCRYPT_FLASH_KEY ESP_EFUSE_WR_DIS_BLOCK1
|
||||
#define ESP_EFUSE_WR_DIS_BLK1 ESP_EFUSE_WR_DIS_BLOCK1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK2[];
|
||||
#define ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY ESP_EFUSE_WR_DIS_BLOCK2
|
||||
#define ESP_EFUSE_WR_DIS_BLK2 ESP_EFUSE_WR_DIS_BLOCK2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK3[];
|
||||
#define ESP_EFUSE_WR_DIS_BLK3 ESP_EFUSE_WR_DIS_BLOCK3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC_CRC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM_CRC ESP_EFUSE_WR_DIS_CUSTOM_MAC_CRC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_TP_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_TP_HIGH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_TP_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_TP_HIGH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_VERSION[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM_VER ESP_EFUSE_WR_DIS_MAC_VERSION
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3_PART_RESERVE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CONFIG[];
|
||||
#define ESP_EFUSE_WR_DIS_ENCRYPT_CONFIG ESP_EFUSE_WR_DIS_FLASH_CRYPT_CONFIG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CODING_SCHEME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_STATUS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ABS_DONE_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ABS_DONE_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_DISABLE[];
|
||||
#define ESP_EFUSE_WR_DIS_DISABLE_JTAG ESP_EFUSE_WR_DIS_JTAG_DISABLE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CONSOLE_DEBUG_DISABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_DECRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_DL_CACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK1[];
|
||||
#define ESP_EFUSE_RD_DIS_ENCRYPT_FLASH_KEY ESP_EFUSE_RD_DIS_BLOCK1
|
||||
#define ESP_EFUSE_RD_DIS_BLK1 ESP_EFUSE_RD_DIS_BLOCK1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK2[];
|
||||
#define ESP_EFUSE_RD_DIS_SECURE_BOOT_KEY ESP_EFUSE_RD_DIS_BLOCK2
|
||||
#define ESP_EFUSE_RD_DIS_BLK2 ESP_EFUSE_RD_DIS_BLOCK2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK3[];
|
||||
#define ESP_EFUSE_RD_DIS_BLK3 ESP_EFUSE_RD_DIS_BLOCK3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CUSTOM_MAC_CRC[];
|
||||
#define ESP_EFUSE_RD_DIS_MAC_CUSTOM_CRC ESP_EFUSE_RD_DIS_CUSTOM_MAC_CRC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_RD_DIS_MAC_CUSTOM ESP_EFUSE_RD_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_TP_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_TP_HIGH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_TP_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_TP_HIGH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_MAC_VERSION[];
|
||||
#define ESP_EFUSE_RD_DIS_MAC_CUSTOM_VER ESP_EFUSE_RD_DIS_MAC_VERSION
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3_PART_RESERVE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_FLASH_CRYPT_CONFIG[];
|
||||
#define ESP_EFUSE_RD_DIS_ENCRYPT_CONFIG ESP_EFUSE_RD_DIS_FLASH_CRYPT_CONFIG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_CODING_SCHEME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY_STATUS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CRC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY_CRC ESP_EFUSE_MAC_CRC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_APP_CPU[];
|
||||
#define ESP_EFUSE_CHIP_VER_DIS_APP_CPU ESP_EFUSE_DISABLE_APP_CPU
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BT[];
|
||||
#define ESP_EFUSE_CHIP_VER_DIS_BT ESP_EFUSE_DISABLE_BT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_PACKAGE_4BIT[];
|
||||
#define ESP_EFUSE_CHIP_VER_PKG_4BIT ESP_EFUSE_CHIP_PACKAGE_4BIT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CACHE[];
|
||||
#define ESP_EFUSE_CHIP_VER_DIS_CACHE ESP_EFUSE_DIS_CACHE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_PACKAGE[];
|
||||
#define ESP_EFUSE_CHIP_VER_PKG ESP_EFUSE_CHIP_PACKAGE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK3_PART_RESERVE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[];
|
||||
#define ESP_EFUSE_CK8M_FREQ ESP_EFUSE_CLK8M_FREQ
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_TIEH[];
|
||||
#define ESP_EFUSE_SDIO_TIEH ESP_EFUSE_XPD_SDIO_TIEH
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_FORCE[];
|
||||
#define ESP_EFUSE_SDIO_FORCE ESP_EFUSE_XPD_SDIO_FORCE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VOL_LEVEL_HP_INV[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CONFIG[];
|
||||
#define ESP_EFUSE_ENCRYPT_CONFIG ESP_EFUSE_FLASH_CRYPT_CONFIG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CODING_SCHEME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_SDIO_HOST[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_FLASH_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_DISABLE[];
|
||||
#define ESP_EFUSE_DISABLE_JTAG ESP_EFUSE_JTAG_DISABLE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_CACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_APP_CPU[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_STATUS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1[];
|
||||
#define ESP_EFUSE_ENCRYPT_FLASH_KEY ESP_EFUSE_BLOCK1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2[];
|
||||
#define ESP_EFUSE_SECURE_BOOT_KEY ESP_EFUSE_BLOCK2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CUSTOM_MAC_CRC[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM_CRC ESP_EFUSE_CUSTOM_MAC_CRC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_HIGH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_HIGH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_VERSION[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM_VER ESP_EFUSE_MAC_VERSION
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,99 +1,112 @@
|
||||
|
||||
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
|
||||
# | EFUSE_BLK1 | | | #
|
||||
# | EFUSE_BLK3) | | | #
|
||||
# | ...) | | | #
|
||||
##########################################################################
|
||||
# !!!!!!!!!!! #
|
||||
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
|
||||
# After editing this file, run the command manually "idf.py efuse-common-table"
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA BLOCK #
|
||||
##############################
|
||||
# EFUSE_RD_WR_DIS_REG #
|
||||
WR_DIS, EFUSE_BLK0, 0, 8, Write protection
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS
|
||||
WR_DIS.GROUP_1, EFUSE_BLK0, 1, 1, Write protection for WDT_DELAY DIS_PAD_JTAG DIS_DOWNLOAD_ICACHE
|
||||
WR_DIS.GROUP_2, EFUSE_BLK0, 2, 1, Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT SPI_BOOT_CRYPT_CNT XTS_KEY_LENGTH_256 SECURE_BOOT_EN
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 2, 1, Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT [SPI_BOOT_CRYPT_CNT] XTS_KEY_LENGTH_256 SECURE_BOOT_EN
|
||||
WR_DIS.GROUP_3, EFUSE_BLK0, 3, 1, Write protection for UART_PRINT_CONTROL FORCE_SEND_RESUME DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT ENABLE_SECURITY_DOWNLOAD FLASH_TPUW
|
||||
WR_DIS.BLK0_RESERVED, EFUSE_BLK0, 4, 1, Write protection for BLK0_RESERVED
|
||||
WR_DIS.SYS_DATA_PART0, EFUSE_BLK0, 5, 1, Write protection for EFUSE_BLK1. SYS_DATA_PART0
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 6, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART2
|
||||
WR_DIS.KEY0, EFUSE_BLK0, 7, 1, Write protection for EFUSE_BLK3. whole KEY0
|
||||
# EFUSE_RD_REPEAT_DATA0_REG #
|
||||
RD_DIS, EFUSE_BLK0, 32, 2, Read protection
|
||||
RD_DIS.KEY0, EFUSE_BLK0, 32, 2, Read protection for EFUSE_BLK3. KEY0
|
||||
RD_DIS.KEY0.LOW, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK3. KEY0 lower 128-bit key
|
||||
RD_DIS.KEY0.HI, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK3. KEY0 higher 128-bit key
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 897499b0349a608b895d467abbcf006b
|
||||
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 34, 2, RTC WDT timeout threshold
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 36, 1, Hardware Disable JTAG permanently
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 37, 1, Disable ICache in Download mode
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 38, 1, Disable flash encryption in Download boot mode
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 39, 3, Enable SPI boot encrypt/decrypt. Odd number: enable; even number: disable
|
||||
XTS_KEY_LENGTH_256, EFUSE_BLK0, 42, 1, Select XTS_AES key length. 1: 256-bit of whole block3; 0: Lower 128-bit of block3
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 43, 2, Set UART boot message output mode. 00: Force print; 01: Low-level print controlled by GPIO 8; 10: High-level print controlled by GPIO 8; 11: Print force disabled
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 45, 1, Force ROM code to send an SPI flash resume command during SPI boot
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 46, 1, Disable all download boot modes
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 47, 1, Disable direct_boot mode
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 48, 1, Enable secure UART download mode
|
||||
FLASH_TPUW, EFUSE_BLK0, 49, 4, Configure flash startup delay after SoC being powered up (the unit is ms/2). When the value is 15 delay will be 7.5 ms
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 53, 1, Enable secure boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 54, 4, Secure version for anti-rollback
|
||||
ENABLE_CUSTOM_MAC, EFUSE_BLK0, 58, 1, True if MAC_CUSTOM is burned
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 59, 1, Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 60, 1, Disables check of blk version major
|
||||
|
||||
|
||||
# USER_DATA BLOCK# - System configuration
|
||||
#######################
|
||||
USER_DATA, EFUSE_BLK1, 0, 88, User data block
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK1, 0, 48, Custom MAC addr
|
||||
|
||||
|
||||
# SYS_DATA_PART1 BLOCK# - System configuration
|
||||
#######################
|
||||
# EFUSE_RD_BLK2_DATA0_REG
|
||||
MAC_FACTORY, EFUSE_BLK2, 40, 8, Factory MAC addr [0]
|
||||
, EFUSE_BLK2, 32, 8, Factory MAC addr [1]
|
||||
, EFUSE_BLK2, 24, 8, Factory MAC addr [2]
|
||||
, EFUSE_BLK2, 16, 8, Factory MAC addr [3]
|
||||
, EFUSE_BLK2, 8, 8, Factory MAC addr [4]
|
||||
, EFUSE_BLK2, 0, 8, Factory MAC addr [5]
|
||||
|
||||
# EFUSE_RD_BLK2_DATA1_REG
|
||||
# mac_id_high 16 bits
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK2, 48, 4, WAFER_VERSION_MINOR
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK2, 52, 2, WAFER_VERSION_MAJOR
|
||||
PKG_VERSION, EFUSE_BLK2, 54, 3, EFUSE_PKG_VERSION
|
||||
BLK_VERSION_MINOR, EFUSE_BLK2, 57, 3, BLK_VERSION_MINOR
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 60, 2, BLK_VERSION_MAJOR
|
||||
|
||||
# EFUSE_RD_BLK2_DATA2_REG
|
||||
|
||||
|
||||
################
|
||||
KEY0, EFUSE_BLK3, 0, 256, [256bit FE key] or [128bit FE key and 128key SB key] or [user data]
|
||||
KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [256bit FE key]
|
||||
KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [128bit FE key]
|
||||
KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [128bit SB key]
|
||||
|
||||
# AUTO CONFIG DIG&RTC DBIAS#
|
||||
################
|
||||
OCODE, EFUSE_BLK2, 62, 7, OCode
|
||||
TEMP_CALIB, EFUSE_BLK2, 69, 9, Temperature calibration data
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 78, 8, ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 86, 5, ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 91, 8, ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 99, 6, ADC1 calibration voltage at atten3
|
||||
DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, BLOCK2 digital dbias when hvt
|
||||
DIG_LDO_SLP_DBIAS2, EFUSE_BLK2, 110, 7, BLOCK2 DIG_LDO_DBG0_DBIAS2
|
||||
DIG_LDO_SLP_DBIAS26, EFUSE_BLK2, 117, 8, BLOCK2 DIG_LDO_DBG0_DBIAS26
|
||||
DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, BLOCK2 DIG_LDO_ACT_DBIAS26
|
||||
DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, BLOCK2 DIG_LDO_ACT_STEPD10
|
||||
RTC_LDO_SLP_DBIAS13, EFUSE_BLK2, 135, 7, BLOCK2 DIG_LDO_SLP_DBIAS13
|
||||
RTC_LDO_SLP_DBIAS29, EFUSE_BLK2, 142, 9, BLOCK2 DIG_LDO_SLP_DBIAS29
|
||||
RTC_LDO_SLP_DBIAS31, EFUSE_BLK2, 151, 6, BLOCK2 DIG_LDO_SLP_DBIAS31
|
||||
RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, BLOCK2 DIG_LDO_ACT_DBIAS31
|
||||
RTC_LDO_ACT_DBIAS13, EFUSE_BLK2, 163, 8, BLOCK2 DIG_LDO_ACT_DBIAS13
|
||||
WR_DIS, EFUSE_BLK0, 0, 8, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 1, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 1, 1, [] wr_dis of DIS_PAD_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 1, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.XTS_KEY_LENGTH_256, EFUSE_BLK0, 2, 1, [] wr_dis of XTS_KEY_LENGTH_256
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 3, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 3, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 3, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 3, 1, [] wr_dis of DIS_DIRECT_BOOT
|
||||
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 3, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 3, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 4, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.CUSTOM_MAC_USED, EFUSE_BLK0, 4, 1, [WR_DIS.ENABLE_CUSTOM_MAC] wr_dis of CUSTOM_MAC_USED
|
||||
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 4, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 4, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 5, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.MAC, EFUSE_BLK0, 6, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 6, 1, [] wr_dis of WAFER_VERSION_MINOR
|
||||
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 6, 1, [] wr_dis of WAFER_VERSION_MAJOR
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 6, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 6, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 6, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 6, 1, [] wr_dis of OCODE
|
||||
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 6, 1, [] wr_dis of TEMP_CALIB
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
|
||||
WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_DBIAS_HVT
|
||||
WR_DIS.DIG_LDO_SLP_DBIAS2, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_SLP_DBIAS2
|
||||
WR_DIS.DIG_LDO_SLP_DBIAS26, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_SLP_DBIAS26
|
||||
WR_DIS.DIG_LDO_ACT_DBIAS26, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_ACT_DBIAS26
|
||||
WR_DIS.DIG_LDO_ACT_STEPD10, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_ACT_STEPD10
|
||||
WR_DIS.RTC_LDO_SLP_DBIAS13, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS13
|
||||
WR_DIS.RTC_LDO_SLP_DBIAS29, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS29
|
||||
WR_DIS.RTC_LDO_SLP_DBIAS31, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS31
|
||||
WR_DIS.RTC_LDO_ACT_DBIAS31, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_ACT_DBIAS31
|
||||
WR_DIS.RTC_LDO_ACT_DBIAS13, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_ACT_DBIAS13
|
||||
WR_DIS.ADC_CALIBRATION_3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC_CALIBRATION_3
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 7, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
RD_DIS, EFUSE_BLK0, 32, 2, [] Disable reading from BlOCK3
|
||||
RD_DIS.KEY0, EFUSE_BLK0, 32, 2, [] Read protection for EFUSE_BLK3. KEY0
|
||||
RD_DIS.KEY0.LOW, EFUSE_BLK0, 32, 1, [] Read protection for EFUSE_BLK3. KEY0 lower 128-bit key
|
||||
RD_DIS.KEY0.HI, EFUSE_BLK0, 33, 1, [] Read protection for EFUSE_BLK3. KEY0 higher 128-bit key
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 34, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 36, 1, [] Set this bit to disable pad jtag
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 37, 1, [] The bit be set to disable icache in download mode
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 38, 1, [] The bit be set to disable manual encryption
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 39, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
XTS_KEY_LENGTH_256, EFUSE_BLK0, 42, 1, [] Flash encryption key length {0: "128 bits key"; 1: "256 bits key"}
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 43, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 45, 1, [] Set this bit to force ROM code to send a resume command during SPI boot
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 46, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7)
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 47, 1, [] This bit set means disable direct_boot mode
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 48, 1, [] Set this bit to enable secure UART download mode
|
||||
FLASH_TPUW, EFUSE_BLK0, 49, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 53, 1, [] The bit be set to enable secure boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 54, 4, [] Secure version for anti-rollback
|
||||
CUSTOM_MAC_USED, EFUSE_BLK0, 58, 1, [ENABLE_CUSTOM_MAC] True if MAC_CUSTOM is burned
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 59, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 60, 1, [] Disables check of blk version major
|
||||
USER_DATA, EFUSE_BLK1, 0, 88, [] User data block
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK1, 0, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC address
|
||||
MAC, EFUSE_BLK2, 40, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK2, 32, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK2, 24, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK2, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK2, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK2, 0, 8, [MAC_FACTORY] MAC address
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK2, 48, 4, [] WAFER_VERSION_MINOR
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK2, 52, 2, [] WAFER_VERSION_MAJOR
|
||||
PKG_VERSION, EFUSE_BLK2, 54, 3, [] EFUSE_PKG_VERSION
|
||||
BLK_VERSION_MINOR, EFUSE_BLK2, 57, 3, [] Minor version of BLOCK2 {0: "No calib"; 1: "With calib"}
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 60, 2, [] Major version of BLOCK2
|
||||
OCODE, EFUSE_BLK2, 62, 7, [] OCode
|
||||
TEMP_CALIB, EFUSE_BLK2, 69, 9, [] Temperature calibration data
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 78, 8, [] ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 86, 5, [] ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 91, 8, [] ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 99, 6, [] ADC1 calibration voltage at atten3
|
||||
DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, [] BLOCK2 digital dbias when hvt
|
||||
DIG_LDO_SLP_DBIAS2, EFUSE_BLK2, 110, 7, [] BLOCK2 DIG_LDO_DBG0_DBIAS2
|
||||
DIG_LDO_SLP_DBIAS26, EFUSE_BLK2, 117, 8, [] BLOCK2 DIG_LDO_DBG0_DBIAS26
|
||||
DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, [] BLOCK2 DIG_LDO_ACT_DBIAS26
|
||||
DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, [] BLOCK2 DIG_LDO_ACT_STEPD10
|
||||
RTC_LDO_SLP_DBIAS13, EFUSE_BLK2, 135, 7, [] BLOCK2 DIG_LDO_SLP_DBIAS13
|
||||
RTC_LDO_SLP_DBIAS29, EFUSE_BLK2, 142, 9, [] BLOCK2 DIG_LDO_SLP_DBIAS29
|
||||
RTC_LDO_SLP_DBIAS31, EFUSE_BLK2, 151, 6, [] BLOCK2 DIG_LDO_SLP_DBIAS31
|
||||
RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, [] BLOCK2 DIG_LDO_ACT_DBIAS31
|
||||
RTC_LDO_ACT_DBIAS13, EFUSE_BLK2, 163, 8, [] BLOCK2 DIG_LDO_ACT_DBIAS13
|
||||
ADC_CALIBRATION_3, EFUSE_BLK2, 192, 11, [] Store the bit [86:96] of ADC calibration data
|
||||
KEY0, EFUSE_BLK3, 0, 256, [BLOCK_KEY0] BLOCK_BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption
|
||||
KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [] 256bit FE key
|
||||
KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [] 128bit FE key
|
||||
KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [] 128bit SB key
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 2216d0ff3e0f4e8803f85711b5cc2829
|
||||
// md5_digest_table 439495cbc35dc68d7566e05ac3dbb248
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -19,14 +19,53 @@ extern "C" {
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK0_RESERVED[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC_USED[];
|
||||
#define ESP_EFUSE_WR_DIS_ENABLE_CUSTOM_MAC ESP_EFUSE_WR_DIS_CUSTOM_MAC_USED
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_SLP_DBIAS2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_SLP_DBIAS26[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_ACT_DBIAS26[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_LDO_ACT_STEPD10[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS13[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS29[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_SLP_DBIAS31[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_ACT_DBIAS31[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTC_LDO_ACT_DBIAS13[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_CALIBRATION_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0_LOW[];
|
||||
@ -45,21 +84,21 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_CUSTOM_MAC[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CUSTOM_MAC_USED[];
|
||||
#define ESP_EFUSE_ENABLE_CUSTOM_MAC ESP_EFUSE_CUSTOM_MAC_USED
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_256BIT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_128BIT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
|
||||
@ -76,6 +115,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS29[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS31[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS31[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS13[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_256BIT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_128BIT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,178 +1,192 @@
|
||||
|
||||
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1..-) | #
|
||||
# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
|
||||
# | ... | | | #
|
||||
# | EFUSE_BLK10)| | | #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
|
||||
# | EFUSE_BLK1 | | | #
|
||||
# | ...) | | | #
|
||||
##########################################################################
|
||||
# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
|
||||
# !!!!!!!!!!! #
|
||||
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
|
||||
# After editing this file, run the command manually "idf.py efuse-common-table"
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA BLOCK #
|
||||
##############################
|
||||
# EFUSE_RD_WR_DIS_REG #
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
|
||||
WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
|
||||
WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
|
||||
WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
|
||||
WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
|
||||
WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
|
||||
WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
|
||||
WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
|
||||
WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
|
||||
WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
|
||||
WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
|
||||
WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
|
||||
WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
|
||||
WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: a85f874ae2b6538ca48b7c3db4a79531
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA0_REG #
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, Read protection
|
||||
RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
|
||||
RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
|
||||
RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
|
||||
RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
|
||||
RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
|
||||
RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
|
||||
RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode
|
||||
DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
|
||||
DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function
|
||||
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently.
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes.
|
||||
USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
|
||||
USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
|
||||
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio
|
||||
BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio
|
||||
POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function
|
||||
POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA1_REG #
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA2_REG #
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA3_REG #
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Disable download through USB-Serial-JTAG
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
|
||||
ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check.
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA4_REG #
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
|
||||
|
||||
|
||||
# MAC_SPI_SYS BLOCK#
|
||||
#######################
|
||||
# RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2
|
||||
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
|
||||
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
|
||||
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
|
||||
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
|
||||
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
|
||||
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
|
||||
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
|
||||
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
|
||||
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
|
||||
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
|
||||
|
||||
# RD_MAC_SPI_SYS_3
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
|
||||
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
|
||||
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
|
||||
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
|
||||
|
||||
# RD_MAC_SPI_SYS_5
|
||||
# WAFER_VERSION_MINOR most significant bit
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
|
||||
|
||||
# SYS_DATA_PART1 BLOCK# - System configuration
|
||||
#######################
|
||||
# RD_SYS_PART1_DATA0 - rd_sys_part1_data3
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
|
||||
|
||||
# RD_SYS_PART1_DATA4
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2
|
||||
TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 140, 8, ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1
|
||||
|
||||
# RD_SYS_PART1_DATA5
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3
|
||||
|
||||
################
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
|
||||
|
||||
################
|
||||
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
|
||||
|
||||
# AUTO CONFIG DIG&RTC DBIAS#
|
||||
################
|
||||
K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO
|
||||
K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO
|
||||
V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20
|
||||
V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20
|
||||
DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt
|
||||
THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG
|
||||
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
|
||||
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
|
||||
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
|
||||
WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
|
||||
WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
|
||||
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
|
||||
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
|
||||
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.ERR_RST_ENABLE, EFUSE_BLK0, 19, 1, [] wr_dis of ERR_RST_ENABLE
|
||||
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK
|
||||
WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q
|
||||
WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D
|
||||
WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS
|
||||
WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD
|
||||
WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP
|
||||
WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS
|
||||
WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4
|
||||
WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5
|
||||
WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6
|
||||
WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7
|
||||
WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO
|
||||
WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO
|
||||
WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20
|
||||
WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20
|
||||
WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT
|
||||
WR_DIS.THRES_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of THRES_HVT
|
||||
WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI
|
||||
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
|
||||
WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
|
||||
WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
|
||||
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
|
||||
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
|
||||
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
|
||||
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
|
||||
WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO
|
||||
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
|
||||
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
|
||||
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
|
||||
RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
|
||||
RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
|
||||
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
|
||||
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
|
||||
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
|
||||
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, [DIS_USB_DEVICE] USB-Serial-JTAG {0: "Enable"; 1: "Disable"}
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function
|
||||
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins
|
||||
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Set this bit to vdd spi pin function as gpio
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value; Otherwise; the waiting time is twice the configurable value
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Disable UART download mode through USB-Serial-JTAG
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature)
|
||||
ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, [] Use BLOCK0 to check error record registers {0: "without check"; 1: "with check"}
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major
|
||||
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI PAD CLK
|
||||
SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI PAD Q(D1)
|
||||
SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI PAD D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI PAD CS
|
||||
SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI PAD HD(D3)
|
||||
SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI PAD WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI PAD DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI PAD D4
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI PAD D5
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI PAD D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI PAD D7
|
||||
WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits
|
||||
PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR
|
||||
K_RTC_LDO, EFUSE_BLK1, 135, 7, [] BLOCK1 K_RTC_LDO
|
||||
K_DIG_LDO, EFUSE_BLK1, 142, 7, [] BLOCK1 K_DIG_LDO
|
||||
V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, [] BLOCK1 voltage of rtc dbias20
|
||||
V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, [] BLOCK1 voltage of digital dbias20
|
||||
DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, [] BLOCK1 digital dbias when hvt
|
||||
THRES_HVT, EFUSE_BLK1, 170, 10, [] BLOCK1 pvt threshold when hvt
|
||||
WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calibration"; 1: "With calibration"}
|
||||
TEMP_CALIB, EFUSE_BLK2, 131, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 140, 8, [] ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, [] ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, [] ADC1 init code at atten1
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, [] ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, [] ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, [] ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, [] ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, [] ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, [] ADC1 calibration voltage at atten3
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC address
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 87.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 2bf0cfccdc9e055a493d80400a248794
|
||||
// md5_digest_table 661eec06c4c442af5baa0c947029db74
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -20,74 +20,166 @@ extern "C" {
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ERR_RST_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_THRES_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
|
||||
#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
@ -95,21 +187,29 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
@ -124,20 +224,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
|
||||
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,163 +1,212 @@
|
||||
|
||||
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1..-) | #
|
||||
# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
|
||||
# | ... | | | #
|
||||
# | EFUSE_BLK10)| | | #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
|
||||
# | EFUSE_BLK1 | | | #
|
||||
# | ...) | | | #
|
||||
##########################################################################
|
||||
# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
|
||||
# !!!!!!!!!!! #
|
||||
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
|
||||
# After editing this file, run the command manually "idf.py efuse-common-table"
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA BLOCK #
|
||||
##############################
|
||||
# EFUSE_RD_WR_DIS_REG #
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS.KEY0 RD_DIS.KEY1 RD_DIS.KEY2 RD_DIS.KEY3 RD_DIS.KEY4 RD_DIS.KEY5 RD_DIS.SYS_DATA_PART2
|
||||
WR_DIS.DIS_RTC_RAM_BOOT, EFUSE_BLK0, 1, 1, Write protection for DIS_RTC_RAM_BOOT
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS.JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
|
||||
WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
|
||||
WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
|
||||
WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
|
||||
WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
|
||||
WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
|
||||
WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
|
||||
WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
|
||||
WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
|
||||
WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
|
||||
WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
|
||||
WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
|
||||
WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
|
||||
WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 888a61f6f500d9c7ee0aa32016b0bee7
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA0_REG #
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, Read protection
|
||||
RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
|
||||
RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
|
||||
RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
|
||||
RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
|
||||
RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
|
||||
RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
|
||||
RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
|
||||
DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7
|
||||
DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
|
||||
DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function
|
||||
DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function
|
||||
DIS_BOOT_REMAP, EFUSE_BLK0, 47, 1, Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 49, 1, Software disable jtag jtag can be activated again by hmac module
|
||||
HARD_DIS_JTAG, EFUSE_BLK0, 50, 1, Hardware disable jtag permanently disable jtag function
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 51, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 56, 1, Exchange D+ D- pins
|
||||
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 57, 1, Enable external PHY
|
||||
BLOCK0_VERSION, EFUSE_BLK0, 59, 2, BLOCK0 efuse version
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA1_REG #
|
||||
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up
|
||||
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda
|
||||
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA2_REG #
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA3_REG #
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
|
||||
DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
|
||||
UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, 0: UART0. 1: UART1
|
||||
DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
|
||||
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
|
||||
FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 138, 1, Force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 139, 16, Secure version for anti-rollback
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA4_REG #
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
|
||||
|
||||
|
||||
# MAC_SPI_8M_SYS BLOCK#
|
||||
#######################
|
||||
# RD_MAC_SPI_8M_0 - RD_MAC_SPI_8M_2
|
||||
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
|
||||
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
|
||||
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
|
||||
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
|
||||
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
|
||||
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
|
||||
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
|
||||
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
|
||||
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
|
||||
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
|
||||
|
||||
# RD_MAC_SPI_8M_3
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, WAFER_VERSION_MAJOR
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 132, 3, WAFER_VERSION_MINOR least significant bits
|
||||
, EFUSE_BLK1, 116, 1, WAFER_VERSION_MINOR most significant bit
|
||||
# WAFER_VERSION_MINOR least significant bits is from RD_MAC_SPI_8M_4
|
||||
FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, BLK_VERSION_MAJOR
|
||||
PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version
|
||||
|
||||
# RD_MAC_SPI_8M_4
|
||||
PKG_VERSION, EFUSE_BLK1, 128, 4, Package version
|
||||
# WAFER_VERSION_MINOR least significant bits
|
||||
|
||||
# SYS_DATA_PART1 BLOCK# - System configuration
|
||||
#######################
|
||||
# RD_SYS_DATA0 - RD_SYS_DATA3
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
|
||||
|
||||
# RD_SYS_DATA4
|
||||
BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
|
||||
|
||||
################
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
|
||||
|
||||
################
|
||||
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE
|
||||
WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
|
||||
WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE
|
||||
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
WR_DIS.DIS_USB, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB
|
||||
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
|
||||
WR_DIS.DIS_BOOT_REMAP, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_BOOT_REMAP
|
||||
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of SOFT_DIS_JTAG
|
||||
WR_DIS.HARD_DIS_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of HARD_DIS_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD
|
||||
WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH
|
||||
WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
|
||||
WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
|
||||
WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
|
||||
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
|
||||
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
|
||||
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_LEGACY_SPI_BOOT
|
||||
WR_DIS.UART_PRINT_CHANNEL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CHANNEL
|
||||
WR_DIS.DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_DOWNLOAD_MODE
|
||||
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION
|
||||
WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK
|
||||
WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q
|
||||
WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D
|
||||
WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS
|
||||
WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD
|
||||
WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP
|
||||
WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS
|
||||
WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4
|
||||
WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5
|
||||
WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6
|
||||
WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7
|
||||
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
|
||||
WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI
|
||||
WR_DIS.FLASH_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VERSION
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.PSRAM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VERSION
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.ADC_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of ADC_CALIB
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB
|
||||
WR_DIS.RTCCALIB_V1IDX_A10H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A10H
|
||||
WR_DIS.RTCCALIB_V1IDX_A11H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A11H
|
||||
WR_DIS.RTCCALIB_V1IDX_A12H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A12H
|
||||
WR_DIS.RTCCALIB_V1IDX_A13H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A13H
|
||||
WR_DIS.RTCCALIB_V1IDX_A20H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A20H
|
||||
WR_DIS.RTCCALIB_V1IDX_A21H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A21H
|
||||
WR_DIS.RTCCALIB_V1IDX_A22H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A22H
|
||||
WR_DIS.RTCCALIB_V1IDX_A23H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A23H
|
||||
WR_DIS.RTCCALIB_V1IDX_A10L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A10L
|
||||
WR_DIS.RTCCALIB_V1IDX_A11L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A11L
|
||||
WR_DIS.RTCCALIB_V1IDX_A12L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A12L
|
||||
WR_DIS.RTCCALIB_V1IDX_A13L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A13L
|
||||
WR_DIS.RTCCALIB_V1IDX_A20L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A20L
|
||||
WR_DIS.RTCCALIB_V1IDX_A21L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A21L
|
||||
WR_DIS.RTCCALIB_V1IDX_A22L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A22L
|
||||
WR_DIS.RTCCALIB_V1IDX_A23L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A23L
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
|
||||
WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
|
||||
WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
|
||||
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
|
||||
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
|
||||
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
|
||||
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
|
||||
WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE
|
||||
WR_DIS.USB_FORCE_NOPERSIST, EFUSE_BLK0, 30, 1, [] wr_dis of USB_FORCE_NOPERSIST
|
||||
WR_DIS.BLOCK0_VERSION, EFUSE_BLK0, 30, 1, [] wr_dis of BLOCK0_VERSION
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
|
||||
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
|
||||
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
|
||||
RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
|
||||
RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
|
||||
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
|
||||
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
|
||||
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache
|
||||
DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Disables Icache when SoC is in Download mode
|
||||
DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Disables Dcache when SoC is in Download mode
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode
|
||||
DIS_USB, EFUSE_BLK0, 45, 1, [] Set this bit to disable USB OTG function
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable the TWAI Controller function
|
||||
DIS_BOOT_REMAP, EFUSE_BLK0, 47, 1, [] Disables capability to Remap RAM to ROM address space
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 49, 1, [] Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral
|
||||
HARD_DIS_JTAG, EFUSE_BLK0, 50, 1, [] Hardware disables JTAG permanently
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 51, 1, [] Disables flash encryption when in download boot modes
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 56, 1, [] Set this bit to exchange USB D+ and D- pins
|
||||
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 57, 1, [EXT_PHY_ENABLE] Set this bit to enable external USB PHY
|
||||
USB_FORCE_NOPERSIST, EFUSE_BLK0, 58, 1, [] If set; forces USB BVALID to 1
|
||||
BLOCK0_VERSION, EFUSE_BLK0, 59, 2, [] BLOCK0 efuse version
|
||||
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on
|
||||
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}
|
||||
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of KEY0
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of KEY1
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of KEY2
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of KEY3
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of KEY4
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of KEY5
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable aggressive secure boot key revocation mode
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable all download boot modes
|
||||
DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, [] Set this bit to disable Legacy SPI boot mode
|
||||
UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, [] Selects the default UART for printing boot messages {0: "UART0"; 1: "UART1"}
|
||||
DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Set this bit to disable use of USB OTG in UART download boot mode
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode (read/write flash only)
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}
|
||||
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}
|
||||
FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 138, 1, [] If set; forces ROM code to send an SPI flash resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 139, 16, [] Secure version (used by ESP-IDF anti-rollback feature)
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major
|
||||
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK
|
||||
SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1)
|
||||
SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS
|
||||
SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3)
|
||||
SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, [] WAFER_VERSION_MAJOR
|
||||
WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 116, 1, [] WAFER_VERSION_MINOR most significant bit
|
||||
FLASH_VERSION, EFUSE_BLK1, 117, 4, [] Flash version
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, [] BLK_VERSION_MAJOR
|
||||
PSRAM_VERSION, EFUSE_BLK1, 124, 4, [] PSRAM version
|
||||
PKG_VERSION, EFUSE_BLK1, 128, 4, [] Package version
|
||||
WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 132, 3, [] WAFER_VERSION_MINOR least significant bits
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
ADC_CALIB, EFUSE_BLK2, 128, 4, [] 4 bit of ADC calibration
|
||||
BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, [] BLK_VERSION_MINOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"; 2: "ADC calib V2"}
|
||||
TEMP_CALIB, EFUSE_BLK2, 135, 9, [] Temperature calibration data
|
||||
RTCCALIB_V1IDX_A10H, EFUSE_BLK2, 144, 8, []
|
||||
RTCCALIB_V1IDX_A11H, EFUSE_BLK2, 152, 8, []
|
||||
RTCCALIB_V1IDX_A12H, EFUSE_BLK2, 160, 8, []
|
||||
RTCCALIB_V1IDX_A13H, EFUSE_BLK2, 168, 8, []
|
||||
RTCCALIB_V1IDX_A20H, EFUSE_BLK2, 176, 8, []
|
||||
RTCCALIB_V1IDX_A21H, EFUSE_BLK2, 184, 8, []
|
||||
RTCCALIB_V1IDX_A22H, EFUSE_BLK2, 192, 8, []
|
||||
RTCCALIB_V1IDX_A23H, EFUSE_BLK2, 200, 8, []
|
||||
RTCCALIB_V1IDX_A10L, EFUSE_BLK2, 208, 6, []
|
||||
RTCCALIB_V1IDX_A11L, EFUSE_BLK2, 214, 6, []
|
||||
RTCCALIB_V1IDX_A12L, EFUSE_BLK2, 220, 6, []
|
||||
RTCCALIB_V1IDX_A13L, EFUSE_BLK2, 226, 6, []
|
||||
RTCCALIB_V1IDX_A20L, EFUSE_BLK2, 232, 6, []
|
||||
RTCCALIB_V1IDX_A21L, EFUSE_BLK2, 238, 6, []
|
||||
RTCCALIB_V1IDX_A22L, EFUSE_BLK2, 244, 6, []
|
||||
RTCCALIB_V1IDX_A23L, EFUSE_BLK2, 250, 6, []
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 87.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 10aa3ea5c0748be491a49b2b2d889166
|
||||
// md5_digest_table 42c79ddff54c8f03645a832a69f60af2
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -19,56 +19,148 @@ extern "C" {
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_BOOT_REMAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HARD_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[];
|
||||
#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_FORCE_NOPERSIST[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK0_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[];
|
||||
#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_FORCE_NOPERSIST[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK0_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[];
|
||||
@ -79,11 +171,17 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
@ -99,35 +197,65 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23L[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,194 +1,232 @@
|
||||
|
||||
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1..256) | #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
|
||||
# | EFUSE_BLK1 | | | #
|
||||
# | ... | | | #
|
||||
# | EFUSE_BLK10)| | | #
|
||||
# | ...) | | | #
|
||||
##########################################################################
|
||||
# !!!!!!!!!!! #
|
||||
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
|
||||
# After editing this file, run the command manually "idf.py efuse-common-table"
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA BLOCK #
|
||||
##############################
|
||||
# EFUSE_RD_WR_DIS_REG #
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
|
||||
WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
|
||||
WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
|
||||
WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
|
||||
WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
|
||||
WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
|
||||
WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
|
||||
WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
|
||||
WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
|
||||
WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
|
||||
WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
|
||||
WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
|
||||
WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
|
||||
WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 6925129eca795b8b087d31be539740ec
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA0_REG #
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, Read protection
|
||||
RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
|
||||
RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
|
||||
RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
|
||||
RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
|
||||
RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
|
||||
RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
|
||||
RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
|
||||
DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7
|
||||
DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
|
||||
DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function
|
||||
DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function
|
||||
DIS_APP_CPU, EFUSE_BLK0, 47, 1, Disables APP CPU
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral
|
||||
HARD_DIS_JTAG, EFUSE_BLK0, 51, 1, Hardware disable jtag permanently disable jtag function
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
|
||||
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, Enable external PHY
|
||||
BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enables BTLC GPIO
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA1_REG #
|
||||
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up
|
||||
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda
|
||||
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA2_REG #
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 118, 1, Set to disable usb_serial_jtag-to-jtag function
|
||||
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, Set to disable usb_serial_jtag module
|
||||
STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, Enable selection between usb_to_jtag or pad_to_jtag through gpio10
|
||||
USB_PHY_SEL, EFUSE_BLK0, 121, 1, Select internal/external PHY for USB OTG and usb_serial_jtag
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA3_REG #
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot
|
||||
FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Set this bit to disable download through USB-Serial-JTAG
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
|
||||
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
|
||||
FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line
|
||||
FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Sets the size of flash page
|
||||
FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enables ECC in Flash boot mode
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
|
||||
DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, Set this bit to disable download through USB-OTG
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA4_REG #
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
|
||||
|
||||
|
||||
# MAC_SPI_8M_SYS BLOCK#
|
||||
#######################
|
||||
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
|
||||
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
|
||||
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
|
||||
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
|
||||
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
|
||||
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
|
||||
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
|
||||
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
|
||||
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
|
||||
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
|
||||
|
||||
# RD_MAC_SPI_SYS_3
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
|
||||
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
|
||||
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
|
||||
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
|
||||
|
||||
# RD_MAC_SPI_SYS_5
|
||||
# WAFER_VERSION_MINOR most significant bit
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
|
||||
ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, ADC2 calibration voltage at atten3
|
||||
|
||||
|
||||
# SYS_DATA_PART1 BLOCK# - System configuration
|
||||
#######################
|
||||
# RD_SYS_PART1_DATA0
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
|
||||
|
||||
# RD_SYS_PART1_DATA4
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
|
||||
TEMP_CALIB, EFUSE_BLK2, 132, 9, Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 141, 8, ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, ADC1 init code at atten1
|
||||
|
||||
# RD_SYS_PART1_DATA5
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, ADC1 init code at atten3
|
||||
ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, ADC2 init code at atten0
|
||||
ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, ADC2 init code at atten1
|
||||
ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, ADC2 init code at atten2
|
||||
ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, ADC2 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, ADC1 calibration voltage at atten3
|
||||
ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, ADC2 calibration voltage at atten0
|
||||
ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, ADC2 calibration voltage at atten1
|
||||
ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, ADC2 calibration voltage at atten2
|
||||
|
||||
################
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
|
||||
|
||||
################
|
||||
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
|
||||
|
||||
# AUTO CONFIG DIG&RTC DBIAS#
|
||||
################
|
||||
K_RTC_LDO, EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO
|
||||
K_DIG_LDO, EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO
|
||||
V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20
|
||||
V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20
|
||||
DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE
|
||||
WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
|
||||
WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE
|
||||
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
WR_DIS.DIS_USB_OTG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG
|
||||
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
|
||||
WR_DIS.DIS_APP_CPU, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_APP_CPU
|
||||
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG
|
||||
WR_DIS.STRAP_JTAG_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of STRAP_JTAG_SEL
|
||||
WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of USB_PHY_SEL
|
||||
WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD
|
||||
WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH
|
||||
WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
|
||||
WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
|
||||
WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
|
||||
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
|
||||
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
|
||||
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
WR_DIS.FLASH_ECC_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_MODE
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION
|
||||
WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE
|
||||
WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE
|
||||
WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 19, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
|
||||
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK
|
||||
WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q
|
||||
WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D
|
||||
WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS
|
||||
WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD
|
||||
WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP
|
||||
WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS
|
||||
WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4
|
||||
WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5
|
||||
WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6
|
||||
WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7
|
||||
WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO
|
||||
WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO
|
||||
WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20
|
||||
WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20
|
||||
WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT
|
||||
WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI
|
||||
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
|
||||
WR_DIS.ADC2_CAL_VOL_ATTEN3, EFUSE_BLK0, 20, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN3
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
|
||||
WR_DIS.ADC2_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN0
|
||||
WR_DIS.ADC2_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN1
|
||||
WR_DIS.ADC2_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN2
|
||||
WR_DIS.ADC2_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN3
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
|
||||
WR_DIS.ADC2_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN0
|
||||
WR_DIS.ADC2_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN1
|
||||
WR_DIS.ADC2_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN2
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
|
||||
WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
|
||||
WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
|
||||
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
|
||||
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
|
||||
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
|
||||
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
|
||||
WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE
|
||||
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
|
||||
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
|
||||
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
|
||||
RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
|
||||
RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
|
||||
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
|
||||
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
|
||||
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache
|
||||
DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
|
||||
DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode
|
||||
DIS_USB_OTG, EFUSE_BLK0, 45, 1, [DIS_USB] Set this bit to disable USB function
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function
|
||||
DIS_APP_CPU, EFUSE_BLK0, 47, 1, [] Disable app cpu
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins
|
||||
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, [EXT_PHY_ENABLE] Set this bit to enable external PHY
|
||||
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] SPI regulator power up signal
|
||||
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}
|
||||
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 118, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device
|
||||
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, [DIS_USB_DEVICE] Set this bit to disable usb device
|
||||
STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0
|
||||
USB_PHY_SEL, EFUSE_BLK0, 121, 1, [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"}
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}
|
||||
FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"}
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}
|
||||
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}
|
||||
FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}
|
||||
FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, [] Set Flash page size
|
||||
FLASH_ECC_EN, EFUSE_BLK0, 140, 1, [] Set 1 to enable ECC for flash boot
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature)
|
||||
DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, [] Set this bit to disable download through USB-OTG
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major
|
||||
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK
|
||||
SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1)
|
||||
SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS
|
||||
SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3)
|
||||
SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7
|
||||
WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits
|
||||
PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR
|
||||
K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO
|
||||
K_DIG_LDO, EFUSE_BLK1, 148, 7, [] BLOCK1 K_DIG_LDO
|
||||
V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, [] BLOCK1 voltage of rtc dbias20
|
||||
V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, [] BLOCK1 voltage of digital dbias20
|
||||
DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, [] BLOCK1 digital dbias when hvt
|
||||
WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR
|
||||
ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, [] ADC2 calibration voltage at atten3
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"}
|
||||
TEMP_CALIB, EFUSE_BLK2, 132, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 141, 8, [] ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, [] ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, [] ADC1 init code at atten1
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, [] ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, [] ADC1 init code at atten3
|
||||
ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, [] ADC2 init code at atten0
|
||||
ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, [] ADC2 init code at atten1
|
||||
ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, [] ADC2 init code at atten2
|
||||
ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, [] ADC2 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, [] ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, [] ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, [] ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, [] ADC1 calibration voltage at atten3
|
||||
ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, [] ADC2 calibration voltage at atten0
|
||||
ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, [] ADC2 calibration voltage at atten1
|
||||
ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, [] ADC2 calibration voltage at atten2
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 770b2130715648e4649be150765d72f9
|
||||
// md5_digest_table 7f80667718451ae522bb4d60ced03d49
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -20,54 +20,165 @@ extern "C" {
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB ESP_EFUSE_WR_DIS_DIS_USB_OTG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_APP_CPU[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
#define ESP_EFUSE_WR_DIS_HARD_DIS_JTAG ESP_EFUSE_WR_DIS_DIS_PAD_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_STRAP_JTAG_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[];
|
||||
#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG[];
|
||||
#define ESP_EFUSE_DIS_USB ESP_EFUSE_DIS_USB_OTG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
#define ESP_EFUSE_HARD_DIS_JTAG ESP_EFUSE_DIS_PAD_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[];
|
||||
#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[];
|
||||
@ -77,23 +188,33 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
|
||||
#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
|
||||
@ -105,21 +226,28 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
@ -142,19 +270,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
||||
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@ -23,97 +23,95 @@ extern "C" {
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT);
|
||||
return EFUSE.blk0_rdata0.rd_flash_crypt_cnt;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
|
||||
{
|
||||
return REG_READ(EFUSE_BLK0_RDATA1_REG);
|
||||
return EFUSE.blk0_rdata1.rd_mac;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA2_REG, EFUSE_RD_WIFI_MAC_CRC_HIGH) & 0x0000FFFF;
|
||||
return EFUSE.blk0_rdata2.rd_mac_1;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v1_en(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_0);
|
||||
return EFUSE.blk0_rdata6.rd_abs_done_0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_1);
|
||||
return EFUSE.blk0_rdata6.rd_abs_done_1;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_FORCE);
|
||||
return EFUSE.blk0_rdata4.rd_xpd_sdio_force;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_xpd_sdio(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_XPD_SDIO_REG);
|
||||
return EFUSE.blk0_rdata4.rd_xpd_sdio_reg;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_TIEH);
|
||||
return EFUSE.blk0_rdata4.rd_xpd_sdio_tieh;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFH);
|
||||
return (EFUSE.blk0_rdata4.val >> 8) & 0x3;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFM);
|
||||
return (EFUSE.blk0_rdata4.val >> 10) & 0x3;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFL);
|
||||
return (EFUSE.blk0_rdata4.val >> 12) & 0x3;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_blk3_part_reserve(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE);
|
||||
return EFUSE.blk0_rdata3.rd_blk3_part_reserve;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_rated(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED);
|
||||
return EFUSE.blk0_rdata3.rd_chip_cpu_freq_rated;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_low(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW);
|
||||
return EFUSE.blk0_rdata3.rd_chip_cpu_freq_low;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
|
||||
{
|
||||
uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
|
||||
uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT);
|
||||
return (pkg_version_4bit << 3) | pkg_version;
|
||||
return (EFUSE.blk0_rdata3.rd_chip_package_4bit << 3) | EFUSE.blk0_rdata3.rd_chip_package;
|
||||
}
|
||||
|
||||
// use efuse_hal_get_major_chip_version() to get full major chip version
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev1(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_REV1);
|
||||
return EFUSE.blk0_rdata3.rd_chip_ver_rev1;
|
||||
}
|
||||
|
||||
// use efuse_hal_get_major_chip_version() to get full major chip version
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev2(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_CHIP_VER_REV2);
|
||||
return EFUSE.blk0_rdata5.rd_chip_ver_rev2;
|
||||
}
|
||||
|
||||
// use efuse_hal_get_minor_chip_version() to get minor chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_WAFER_VERSION_MINOR);
|
||||
return EFUSE.blk0_rdata5.rd_wafer_version_minor;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
|
||||
@ -123,47 +121,47 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_coding_scheme(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME);
|
||||
return EFUSE.blk0_rdata6.rd_coding_scheme;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_app_cpu(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU);
|
||||
return EFUSE.blk0_rdata3.rd_disable_app_cpu;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_bt(void)
|
||||
{
|
||||
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_BT);
|
||||
return EFUSE.blk0_rdata3.rd_disable_bt;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_vol_level_hp_inv(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV);
|
||||
return EFUSE.blk0_rdata5.rd_vol_level_hp_inv;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc_vref(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_ADC_VREF);
|
||||
return EFUSE.blk0_rdata4.rd_adc_vref;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_low(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_LOW);
|
||||
return EFUSE.blk3_rdata3.rd_adc1_tp_low;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_low(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_LOW);
|
||||
return EFUSE.blk3_rdata3.rd_adc2_tp_low;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_high(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_HIGH);
|
||||
return EFUSE.blk3_rdata3.rd_adc1_tp_high;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_high(void)
|
||||
{
|
||||
return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_HIGH);
|
||||
return EFUSE.blk3_rdata3.rd_adc2_tp_high;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsigned block)
|
||||
@ -171,7 +169,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsi
|
||||
if (block == 0 || block > 4) {
|
||||
return false;
|
||||
}
|
||||
uint32_t error_reg = REG_GET_FIELD(EFUSE_DEC_STATUS_REG, EFUSE_DEC_WARNINGS);
|
||||
uint32_t error_reg = EFUSE.dec_status.dec_warnings;
|
||||
return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block - 1) != 0;
|
||||
}
|
||||
|
||||
@ -179,42 +177,42 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_dec_warnings(unsi
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_cmd(void)
|
||||
{
|
||||
return REG_READ(EFUSE_CMD_REG);
|
||||
return EFUSE.cmd.val;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
|
||||
{
|
||||
REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD);
|
||||
EFUSE.cmd.read_cmd = 1;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(void)
|
||||
{
|
||||
REG_WRITE(EFUSE_CMD_REG, EFUSE_PGM_CMD);
|
||||
EFUSE.cmd.pgm_cmd = 1;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
|
||||
{
|
||||
REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE);
|
||||
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
|
||||
{
|
||||
REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE);
|
||||
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint32_t value)
|
||||
{
|
||||
REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, value);
|
||||
EFUSE.dac_conf.dac_clk_div = value;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel0(uint32_t value)
|
||||
{
|
||||
REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, value);
|
||||
EFUSE.clk.clk_sel0 = value;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel1(uint32_t value)
|
||||
{
|
||||
REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, value);
|
||||
EFUSE.clk.clk_sel1 = value;
|
||||
}
|
||||
|
||||
/******************* eFuse control functions *************************/
|
||||
|
||||
@ -22,7 +22,7 @@ extern "C" {
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data0.spi_boot_encrypt_decrypt_cnt;
|
||||
return EFUSE.rd_repeat_data0.spi_boot_crypt_cnt;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
|
||||
@ -32,12 +32,12 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
|
||||
{
|
||||
return EFUSE.rd_blk2_data0.blk2_data0;
|
||||
return EFUSE.rd_blk2_data0.mac;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
|
||||
{
|
||||
return EFUSE.rd_blk2_data1.mac_id_high;
|
||||
return EFUSE.rd_blk2_data1.mac_1;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
|
||||
@ -85,7 +85,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void)
|
||||
{
|
||||
// OCODE, EFUSE_BLK2, 62, 7, OCode
|
||||
return (EFUSE.rd_blk2_data2.ocode_hi << 2) + EFUSE.rd_blk2_data1.ocode_low;
|
||||
return (EFUSE.rd_blk2_data2.ocode_1 << 2) + EFUSE.rd_blk2_data1.ocode;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void)
|
||||
@ -109,7 +109,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_slp_d
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_act_dbias26(void)
|
||||
{
|
||||
// DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, BLOCK2 DIG_LDO_ACT_DBIAS26
|
||||
return (EFUSE.rd_blk2_data4.dig_ldo_act_dbias26_hi << 3) + EFUSE.rd_blk2_data3.dig_ldo_act_dbias26_low;
|
||||
return (EFUSE.rd_blk2_data4.dig_ldo_act_dbias26_1 << 3) + EFUSE.rd_blk2_data3.dig_ldo_act_dbias26;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_act_stepd10(void)
|
||||
@ -139,7 +139,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_slp_d
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_act_dbias31(void)
|
||||
{
|
||||
// RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, BLOCK2 DIG_LDO_ACT_DBIAS31
|
||||
return (EFUSE.rd_blk2_data5.rtc_ldo_act_dbias31_hi << 3) + EFUSE.rd_blk2_data4.rtc_ldo_act_dbias31_low;
|
||||
return (EFUSE.rd_blk2_data5.rtc_ldo_act_dbias31_1 << 3) + EFUSE.rd_blk2_data4.rtc_ldo_act_dbias31;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_act_dbias13(void)
|
||||
|
||||
@ -32,7 +32,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
|
||||
{
|
||||
return EFUSE.rd_mac_spi_sys_0;
|
||||
return EFUSE.rd_mac_spi_sys_0.mac_0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
|
||||
@ -59,7 +59,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_ve
|
||||
// use efuse_hal_get_minor_chip_version() to get minor chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
|
||||
{
|
||||
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
|
||||
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_lo;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
|
||||
@ -114,7 +114,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void)
|
||||
{
|
||||
// EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20
|
||||
return (EFUSE.rd_mac_spi_sys_5.v_dig_dbias20_hi << 3) + EFUSE.rd_mac_spi_sys_4.v_dig_dbias20_low;
|
||||
return (EFUSE.rd_mac_spi_sys_5.v_dig_dbias20_1 << 3) + EFUSE.rd_mac_spi_sys_4.v_dig_dbias20;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void)
|
||||
|
||||
@ -32,12 +32,12 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
|
||||
{
|
||||
return EFUSE.rd_mac_spi_8m_0;
|
||||
return EFUSE.rd_mac_spi_sys_0.mac_0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
|
||||
{
|
||||
return EFUSE.rd_mac_spi_8m_1.mac_1;
|
||||
return EFUSE.rd_mac_spi_sys_1.mac_1;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
|
||||
@ -48,13 +48,13 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
|
||||
// use efuse_hal_get_major_chip_version() to get major chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
|
||||
{
|
||||
return EFUSE.rd_mac_spi_8m_3.wafer_version_major;
|
||||
return EFUSE.rd_mac_spi_sys_3.wafer_version_major;
|
||||
}
|
||||
|
||||
// use efuse_hal_get_minor_chip_version() to get minor chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
|
||||
{
|
||||
return (EFUSE.rd_mac_spi_8m_3.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_8m_4.wafer_version_minor_low;
|
||||
return (EFUSE.rd_mac_spi_sys_3.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_4.wafer_version_minor_lo;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
|
||||
@ -64,12 +64,12 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
|
||||
{
|
||||
return EFUSE.rd_mac_spi_8m_3.blk_version_major;
|
||||
return EFUSE.rd_mac_spi_sys_3.blk_version_major;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
|
||||
{
|
||||
return EFUSE.rd_sys_data4.blk_version_minor;
|
||||
return EFUSE.rd_sys_part1_data4.blk_version_minor;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
|
||||
@ -79,37 +79,37 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_versi
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
|
||||
{
|
||||
return EFUSE.rd_mac_spi_8m_4.pkg_version;
|
||||
return EFUSE.rd_mac_spi_sys_4.pkg_version;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data1.sdio_force;
|
||||
return EFUSE.rd_repeat_data1.vdd_spi_force;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data1.sdio_tieh;
|
||||
return EFUSE.rd_repeat_data1.vdd_spi_tieh;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_xpd(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data1.sdio_xpd;
|
||||
return EFUSE.rd_repeat_data1.vdd_spi_xpd;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data1.sdio_drefl;
|
||||
return EFUSE.rd_repeat_data1.vdd_spi_drefl;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data1.sdio_drefm;
|
||||
return EFUSE.rd_repeat_data1.vdd_spi_drefm;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data0.sdio_drefh;
|
||||
return EFUSE.rd_repeat_data0.vdd_spi_drefh;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void)
|
||||
@ -117,7 +117,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void)
|
||||
// OCODE1, BLOCK2, 128, 4, (#4 reg, pos 0)
|
||||
// OCODE2, BLOCK2, 144, 3, (#4 reg, pos 16)
|
||||
// OCODE = (ocode2 << 4) + ocode1
|
||||
return (EFUSE.rd_sys_data4.ocode_hi << 4) + EFUSE.rd_sys_data4.ocode_low;
|
||||
return (((EFUSE.rd_sys_part1_data4.val >> 16) & 0x7) << 4) + (EFUSE.rd_sys_part1_data4.val & 0xF);
|
||||
}
|
||||
|
||||
/******************* eFuse control functions *************************/
|
||||
|
||||
@ -22,32 +22,32 @@ extern "C" {
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data1.reg_spi_boot_crypt_cnt;
|
||||
return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data1.reg_wdt_delay_sel;
|
||||
return EFUSE.rd_repeat_data1.wdt_delay_sel;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data3.reg_flash_type;
|
||||
return EFUSE.rd_repeat_data3.flash_type;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
|
||||
{
|
||||
return EFUSE.rd_mac_spi_sys_0;
|
||||
return EFUSE.rd_mac_spi_sys_0.mac_0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
|
||||
{
|
||||
return EFUSE.rd_mac_spi_sys_1.reg_mac_1;
|
||||
return EFUSE.rd_mac_spi_sys_1.mac_1;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
|
||||
{
|
||||
return EFUSE.rd_repeat_data2.reg_secure_boot_en;
|
||||
return EFUSE.rd_repeat_data2.secure_boot_en;
|
||||
}
|
||||
|
||||
// use efuse_hal_get_major_chip_version() to get major chip version
|
||||
@ -59,7 +59,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_ve
|
||||
// use efuse_hal_get_minor_chip_version() to get minor chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
|
||||
{
|
||||
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
|
||||
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_lo;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
|
||||
@ -108,7 +108,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_dig_ldo(voi
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20(void)
|
||||
{
|
||||
// EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20
|
||||
return (EFUSE.rd_mac_spi_sys_5.v_rtc_dbias20_hi << 5) + EFUSE.rd_mac_spi_sys_4.v_rtc_dbias20_low;
|
||||
return (EFUSE.rd_mac_spi_sys_5.v_rtc_dbias20_1 << 5) + EFUSE.rd_mac_spi_sys_4.v_rtc_dbias20;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void)
|
||||
|
||||
51
components/soc/esp32/include/soc/efuse_defs.h
Normal file
51
components/soc/esp32/include/soc/efuse_defs.h
Normal file
@ -0,0 +1,51 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||
|
||||
/* Write disable bits */
|
||||
#define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */
|
||||
#define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */
|
||||
#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2)
|
||||
#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */
|
||||
#define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */
|
||||
#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */
|
||||
#define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */
|
||||
#define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */
|
||||
#define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */
|
||||
#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */
|
||||
#define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */
|
||||
#define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */
|
||||
#define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */
|
||||
#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */
|
||||
|
||||
/* Read disable bits for efuse blocks 1-3 */
|
||||
#define EFUSE_RD_DIS_BLK1 (1<<16)
|
||||
#define EFUSE_RD_DIS_BLK2 (1<<17)
|
||||
#define EFUSE_RD_DIS_BLK3 (1<<18)
|
||||
|
||||
#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0
|
||||
#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1
|
||||
#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2
|
||||
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */
|
||||
#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4
|
||||
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5
|
||||
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6
|
||||
#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7
|
||||
|
||||
#define EFUSE_CODING_SCHEME_VAL_NONE 0x0
|
||||
#define EFUSE_CODING_SCHEME_VAL_34 0x1
|
||||
#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
17
components/soc/esp32c2/include/soc/efuse_defs.h
Normal file
17
components/soc/esp32c2/include/soc/efuse_defs.h
Normal file
@ -0,0 +1,17 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -7,6 +7,7 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "efuse_defs.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@ -154,6 +155,11 @@ extern "C" {
|
||||
#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
|
||||
#define EFUSE_WR_DIS_V 0x000000FFU
|
||||
#define EFUSE_WR_DIS_S 0
|
||||
/** EFUSE_RESERVED_0_8 : RW; bitpos: [31:8]; default: 0; */
|
||||
#define EFUSE_RESERVED_0_8 0x00FFFFFFU
|
||||
#define EFUSE_RESERVED_0_8_M (EFUSE_RESERVED_0_8_V << EFUSE_RESERVED_0_8_S)
|
||||
#define EFUSE_RESERVED_0_8_V 0x00FFFFFFU
|
||||
#define EFUSE_RESERVED_0_8_S 8
|
||||
|
||||
/** EFUSE_RD_REPEAT_DATA0_REG register
|
||||
* BLOCK0 data register 1.
|
||||
@ -195,14 +201,14 @@ extern "C" {
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 6
|
||||
/** EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT : RO; bitpos: [9:7]; default: 0;
|
||||
/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [9:7]; default: 0;
|
||||
* These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
|
||||
* number of 1: disable.
|
||||
*/
|
||||
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT 0x00000007U
|
||||
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_M (EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V << EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S)
|
||||
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V 0x00000007U
|
||||
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S 7
|
||||
#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U
|
||||
#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
|
||||
#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U
|
||||
#define EFUSE_SPI_BOOT_CRYPT_CNT_S 7
|
||||
/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [10]; default: 0;
|
||||
* The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise,
|
||||
* XTS_AES use 128-bit eFuse data in BLOCK3.
|
||||
@ -262,37 +268,72 @@ extern "C" {
|
||||
#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
|
||||
#define EFUSE_SECURE_BOOT_EN_V 0x00000001U
|
||||
#define EFUSE_SECURE_BOOT_EN_S 21
|
||||
/** EFUSE_RPT4_RESERVED : RO; bitpos: [31:22]; default: 0;
|
||||
* Reserved (used for four backups method).
|
||||
/** EFUSE_SECURE_VERSION : R; bitpos: [25:22]; default: 0;
|
||||
* Secure version for anti-rollback
|
||||
*/
|
||||
#define EFUSE_RPT4_RESERVED 0x000003FFU
|
||||
#define EFUSE_RPT4_RESERVED_M (EFUSE_RPT4_RESERVED_V << EFUSE_RPT4_RESERVED_S)
|
||||
#define EFUSE_RPT4_RESERVED_V 0x000003FFU
|
||||
#define EFUSE_RPT4_RESERVED_S 22
|
||||
#define EFUSE_SECURE_VERSION 0x0000000FU
|
||||
#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
|
||||
#define EFUSE_SECURE_VERSION_V 0x0000000FU
|
||||
#define EFUSE_SECURE_VERSION_S 22
|
||||
/** EFUSE_CUSTOM_MAC_USED : R; bitpos: [26]; default: 0;
|
||||
* True if MAC_CUSTOM is burned
|
||||
*/
|
||||
#define EFUSE_CUSTOM_MAC_USED (BIT(26))
|
||||
#define EFUSE_CUSTOM_MAC_USED_M (EFUSE_CUSTOM_MAC_USED_V << EFUSE_CUSTOM_MAC_USED_S)
|
||||
#define EFUSE_CUSTOM_MAC_USED_V 0x00000001U
|
||||
#define EFUSE_CUSTOM_MAC_USED_S 26
|
||||
/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [27]; default: 0;
|
||||
* Disables check of wafer version major
|
||||
*/
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(27))
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 27
|
||||
/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [28]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(28))
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 28
|
||||
/** EFUSE_RESERVED_0_61 : R; bitpos: [31:29]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_0_61 0x00000007U
|
||||
#define EFUSE_RESERVED_0_61_M (EFUSE_RESERVED_0_61_V << EFUSE_RESERVED_0_61_S)
|
||||
#define EFUSE_RESERVED_0_61_V 0x00000007U
|
||||
#define EFUSE_RESERVED_0_61_S 29
|
||||
|
||||
/** EFUSE_RD_BLK1_DATA0_REG register
|
||||
* BLOCK1 data register 0.
|
||||
*/
|
||||
#define EFUSE_RD_BLK1_DATA0_REG (DR_REG_EFUSE_BASE + 0x34)
|
||||
/** EFUSE_SYSTEM_DATA0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the bits [0:31] of system data.
|
||||
/** EFUSE_CUSTOM_MAC : R; bitpos: [31:0]; default: 0;
|
||||
* Custom MAC address
|
||||
*/
|
||||
#define EFUSE_SYSTEM_DATA0 0xFFFFFFFFU
|
||||
#define EFUSE_SYSTEM_DATA0_M (EFUSE_SYSTEM_DATA0_V << EFUSE_SYSTEM_DATA0_S)
|
||||
#define EFUSE_SYSTEM_DATA0_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYSTEM_DATA0_S 0
|
||||
#define EFUSE_CUSTOM_MAC 0xFFFFFFFFU
|
||||
#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
|
||||
#define EFUSE_CUSTOM_MAC_V 0xFFFFFFFFU
|
||||
#define EFUSE_CUSTOM_MAC_S 0
|
||||
|
||||
/** EFUSE_RD_BLK1_DATA1_REG register
|
||||
* BLOCK1 data register 1.
|
||||
*/
|
||||
#define EFUSE_RD_BLK1_DATA1_REG (DR_REG_EFUSE_BASE + 0x38)
|
||||
/** EFUSE_SYSTEM_DATA1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the bits [32:63] of system data.
|
||||
/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [15:0]; default: 0;
|
||||
* Custom MAC address
|
||||
*/
|
||||
#define EFUSE_SYSTEM_DATA1 0xFFFFFFFFU
|
||||
#define EFUSE_SYSTEM_DATA1_M (EFUSE_SYSTEM_DATA1_V << EFUSE_SYSTEM_DATA1_S)
|
||||
#define EFUSE_SYSTEM_DATA1_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYSTEM_DATA1_S 0
|
||||
#define EFUSE_CUSTOM_MAC_1 0x0000FFFFU
|
||||
#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
|
||||
#define EFUSE_CUSTOM_MAC_1_V 0x0000FFFFU
|
||||
#define EFUSE_CUSTOM_MAC_1_S 0
|
||||
/** EFUSE_RESERVED_1_48 : R; bitpos: [31:16]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_48 0x0000FFFFU
|
||||
#define EFUSE_RESERVED_1_48_M (EFUSE_RESERVED_1_48_V << EFUSE_RESERVED_1_48_S)
|
||||
#define EFUSE_RESERVED_1_48_V 0x0000FFFFU
|
||||
#define EFUSE_RESERVED_1_48_S 16
|
||||
|
||||
/** EFUSE_RD_BLK1_DATA2_REG register
|
||||
* BLOCK1 data register 2.
|
||||
@ -310,122 +351,227 @@ extern "C" {
|
||||
* Register 0 of BLOCK2.
|
||||
*/
|
||||
#define EFUSE_RD_BLK2_DATA0_REG (DR_REG_EFUSE_BASE + 0x40)
|
||||
/** EFUSE_BLK2_DATA0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Store the bit [0:31] of MAC.
|
||||
/** EFUSE_MAC : R; bitpos: [31:0]; default: 0;
|
||||
* MAC address
|
||||
*/
|
||||
#define EFUSE_BLK2_DATA0 0xFFFFFFFFU
|
||||
#define EFUSE_BLK2_DATA0_M (EFUSE_BLK2_DATA0_V << EFUSE_BLK2_DATA0_S)
|
||||
#define EFUSE_BLK2_DATA0_V 0xFFFFFFFFU
|
||||
#define EFUSE_BLK2_DATA0_S 0
|
||||
#define EFUSE_MAC 0xFFFFFFFFU
|
||||
#define EFUSE_MAC_M (EFUSE_MAC_V << EFUSE_MAC_S)
|
||||
#define EFUSE_MAC_V 0xFFFFFFFFU
|
||||
#define EFUSE_MAC_S 0
|
||||
|
||||
/** EFUSE_RD_BLK2_DATA1_REG register
|
||||
* Register 1 of BLOCK2.
|
||||
*/
|
||||
#define EFUSE_RD_BLK2_DATA1_REG (DR_REG_EFUSE_BASE + 0x44)
|
||||
/** EFUSE_MAC_ID_HIGH : RO; bitpos: [15:0]; default: 0;
|
||||
* Store the bit [31:47] of MAC.
|
||||
/** EFUSE_MAC_1 : R; bitpos: [15:0]; default: 0;
|
||||
* MAC address
|
||||
*/
|
||||
#define EFUSE_MAC_ID_HIGH 0x0000FFFFU
|
||||
#define EFUSE_MAC_ID_HIGH_M (EFUSE_MAC_ID_HIGH_V << EFUSE_MAC_ID_HIGH_S)
|
||||
#define EFUSE_MAC_ID_HIGH_V 0x0000FFFFU
|
||||
#define EFUSE_MAC_ID_HIGH_S 0
|
||||
/** EFUSE_WAFER_VERSION : RO; bitpos: [18:16]; default: 0;
|
||||
* Store wafer version.
|
||||
#define EFUSE_MAC_1 0x0000FFFFU
|
||||
#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
|
||||
#define EFUSE_MAC_1_V 0x0000FFFFU
|
||||
#define EFUSE_MAC_1_S 0
|
||||
/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [19:16]; default: 0;
|
||||
* WAFER_VERSION_MINOR
|
||||
*/
|
||||
#define EFUSE_WAFER_VERSION 0x00000007U
|
||||
#define EFUSE_WAFER_VERSION_M (EFUSE_WAFER_VERSION_V << EFUSE_WAFER_VERSION_S)
|
||||
#define EFUSE_WAFER_VERSION_V 0x00000007U
|
||||
#define EFUSE_WAFER_VERSION_S 16
|
||||
/** EFUSE_PKG_VERSION : RO; bitpos: [21:19]; default: 0;
|
||||
* Store package version.
|
||||
#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU
|
||||
#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
|
||||
#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU
|
||||
#define EFUSE_WAFER_VERSION_MINOR_S 16
|
||||
/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [21:20]; default: 0;
|
||||
* WAFER_VERSION_MAJOR
|
||||
*/
|
||||
#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_S 20
|
||||
/** EFUSE_PKG_VERSION : R; bitpos: [24:22]; default: 0;
|
||||
* EFUSE_PKG_VERSION
|
||||
*/
|
||||
#define EFUSE_PKG_VERSION 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
|
||||
#define EFUSE_PKG_VERSION_V 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_S 19
|
||||
/** EFUSE_BLK2_EFUSE_VERSION : RO; bitpos: [24:22]; default: 0;
|
||||
* Store efuse version.
|
||||
#define EFUSE_PKG_VERSION_S 22
|
||||
/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [27:25]; default: 0;
|
||||
* Minor version of BLOCK2
|
||||
*/
|
||||
#define EFUSE_BLK2_EFUSE_VERSION 0x00000007U
|
||||
#define EFUSE_BLK2_EFUSE_VERSION_M (EFUSE_BLK2_EFUSE_VERSION_V << EFUSE_BLK2_EFUSE_VERSION_S)
|
||||
#define EFUSE_BLK2_EFUSE_VERSION_V 0x00000007U
|
||||
#define EFUSE_BLK2_EFUSE_VERSION_S 22
|
||||
/** EFUSE_RF_REF_I_BIAS_CONFIG : RO; bitpos: [28:25]; default: 0;
|
||||
* Store rf configuration parameters.
|
||||
#define EFUSE_BLK_VERSION_MINOR 0x00000007U
|
||||
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
|
||||
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
|
||||
#define EFUSE_BLK_VERSION_MINOR_S 25
|
||||
/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [29:28]; default: 0;
|
||||
* Major version of BLOCK2
|
||||
*/
|
||||
#define EFUSE_RF_REF_I_BIAS_CONFIG 0x0000000FU
|
||||
#define EFUSE_RF_REF_I_BIAS_CONFIG_M (EFUSE_RF_REF_I_BIAS_CONFIG_V << EFUSE_RF_REF_I_BIAS_CONFIG_S)
|
||||
#define EFUSE_RF_REF_I_BIAS_CONFIG_V 0x0000000FU
|
||||
#define EFUSE_RF_REF_I_BIAS_CONFIG_S 25
|
||||
/** EFUSE_LDO_VOL_BIAS_CONFIG_LOW : RO; bitpos: [31:29]; default: 0;
|
||||
* Store the bit [0:2] of ido configuration parameters.
|
||||
#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
|
||||
#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
|
||||
#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
|
||||
#define EFUSE_BLK_VERSION_MAJOR_S 28
|
||||
/** EFUSE_OCODE : R; bitpos: [31:30]; default: 0;
|
||||
* OCode
|
||||
*/
|
||||
#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW 0x00000007U
|
||||
#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_M (EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V << EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S)
|
||||
#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V 0x00000007U
|
||||
#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S 29
|
||||
#define EFUSE_OCODE 0x00000003U
|
||||
#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
|
||||
#define EFUSE_OCODE_V 0x00000003U
|
||||
#define EFUSE_OCODE_S 30
|
||||
|
||||
/** EFUSE_RD_BLK2_DATA2_REG register
|
||||
* Register 2 of BLOCK2.
|
||||
*/
|
||||
#define EFUSE_RD_BLK2_DATA2_REG (DR_REG_EFUSE_BASE + 0x48)
|
||||
/** EFUSE_LDO_VOL_BIAS_CONFIG_HIGH : RO; bitpos: [26:0]; default: 0;
|
||||
* Store the bit [3:29] of ido configuration parameters.
|
||||
/** EFUSE_OCODE_1 : R; bitpos: [4:0]; default: 0;
|
||||
* OCode
|
||||
*/
|
||||
#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH 0x07FFFFFFU
|
||||
#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_M (EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V << EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S)
|
||||
#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V 0x07FFFFFFU
|
||||
#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S 0
|
||||
/** EFUSE_PVT_LOW : RO; bitpos: [31:27]; default: 0;
|
||||
* Store the bit [0:4] of pvt.
|
||||
#define EFUSE_OCODE_1 0x0000001FU
|
||||
#define EFUSE_OCODE_1_M (EFUSE_OCODE_1_V << EFUSE_OCODE_1_S)
|
||||
#define EFUSE_OCODE_1_V 0x0000001FU
|
||||
#define EFUSE_OCODE_1_S 0
|
||||
/** EFUSE_TEMP_CALIB : R; bitpos: [13:5]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
#define EFUSE_PVT_LOW 0x0000001FU
|
||||
#define EFUSE_PVT_LOW_M (EFUSE_PVT_LOW_V << EFUSE_PVT_LOW_S)
|
||||
#define EFUSE_PVT_LOW_V 0x0000001FU
|
||||
#define EFUSE_PVT_LOW_S 27
|
||||
#define EFUSE_TEMP_CALIB 0x000001FFU
|
||||
#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
|
||||
#define EFUSE_TEMP_CALIB_V 0x000001FFU
|
||||
#define EFUSE_TEMP_CALIB_S 5
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [21:14]; default: 0;
|
||||
* ADC1 init code at atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000000FFU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000000FFU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_S 14
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [26:22]; default: 0;
|
||||
* ADC1 init code at atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN3 0x0000001FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x0000001FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN3_S 22
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:27]; default: 0;
|
||||
* ADC1 calibration voltage at atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0 0x0000001FU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x0000001FU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_S 27
|
||||
|
||||
/** EFUSE_RD_BLK2_DATA3_REG register
|
||||
* Register 3 of BLOCK2.
|
||||
*/
|
||||
#define EFUSE_RD_BLK2_DATA3_REG (DR_REG_EFUSE_BASE + 0x4c)
|
||||
/** EFUSE_PVT_HIGH : RO; bitpos: [9:0]; default: 0;
|
||||
* Store the bit [5:14] of pvt.
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* ADC1 calibration voltage at atten0
|
||||
*/
|
||||
#define EFUSE_PVT_HIGH 0x000003FFU
|
||||
#define EFUSE_PVT_HIGH_M (EFUSE_PVT_HIGH_V << EFUSE_PVT_HIGH_S)
|
||||
#define EFUSE_PVT_HIGH_V 0x000003FFU
|
||||
#define EFUSE_PVT_HIGH_S 0
|
||||
/** EFUSE_ADC_CALIBRATION_0 : RO; bitpos: [31:10]; default: 0;
|
||||
* Store the bit [0:21] of ADC calibration data.
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_1 0x00000007U
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V 0x00000007U
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S 0
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:3]; default: 0;
|
||||
* ADC1 calibration voltage at atten3
|
||||
*/
|
||||
#define EFUSE_ADC_CALIBRATION_0 0x003FFFFFU
|
||||
#define EFUSE_ADC_CALIBRATION_0_M (EFUSE_ADC_CALIBRATION_0_V << EFUSE_ADC_CALIBRATION_0_S)
|
||||
#define EFUSE_ADC_CALIBRATION_0_V 0x003FFFFFU
|
||||
#define EFUSE_ADC_CALIBRATION_0_S 10
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3 0x0000003FU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x0000003FU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_S 3
|
||||
/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [13:9]; default: 0;
|
||||
* BLOCK2 digital dbias when hvt
|
||||
*/
|
||||
#define EFUSE_DIG_DBIAS_HVT 0x0000001FU
|
||||
#define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
|
||||
#define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU
|
||||
#define EFUSE_DIG_DBIAS_HVT_S 9
|
||||
/** EFUSE_DIG_LDO_SLP_DBIAS2 : R; bitpos: [20:14]; default: 0;
|
||||
* BLOCK2 DIG_LDO_DBG0_DBIAS2
|
||||
*/
|
||||
#define EFUSE_DIG_LDO_SLP_DBIAS2 0x0000007FU
|
||||
#define EFUSE_DIG_LDO_SLP_DBIAS2_M (EFUSE_DIG_LDO_SLP_DBIAS2_V << EFUSE_DIG_LDO_SLP_DBIAS2_S)
|
||||
#define EFUSE_DIG_LDO_SLP_DBIAS2_V 0x0000007FU
|
||||
#define EFUSE_DIG_LDO_SLP_DBIAS2_S 14
|
||||
/** EFUSE_DIG_LDO_SLP_DBIAS26 : R; bitpos: [28:21]; default: 0;
|
||||
* BLOCK2 DIG_LDO_DBG0_DBIAS26
|
||||
*/
|
||||
#define EFUSE_DIG_LDO_SLP_DBIAS26 0x000000FFU
|
||||
#define EFUSE_DIG_LDO_SLP_DBIAS26_M (EFUSE_DIG_LDO_SLP_DBIAS26_V << EFUSE_DIG_LDO_SLP_DBIAS26_S)
|
||||
#define EFUSE_DIG_LDO_SLP_DBIAS26_V 0x000000FFU
|
||||
#define EFUSE_DIG_LDO_SLP_DBIAS26_S 21
|
||||
/** EFUSE_DIG_LDO_ACT_DBIAS26 : R; bitpos: [31:29]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS26
|
||||
*/
|
||||
#define EFUSE_DIG_LDO_ACT_DBIAS26 0x00000007U
|
||||
#define EFUSE_DIG_LDO_ACT_DBIAS26_M (EFUSE_DIG_LDO_ACT_DBIAS26_V << EFUSE_DIG_LDO_ACT_DBIAS26_S)
|
||||
#define EFUSE_DIG_LDO_ACT_DBIAS26_V 0x00000007U
|
||||
#define EFUSE_DIG_LDO_ACT_DBIAS26_S 29
|
||||
|
||||
/** EFUSE_RD_BLK2_DATA4_REG register
|
||||
* Register 4 of BLOCK2.
|
||||
*/
|
||||
#define EFUSE_RD_BLK2_DATA4_REG (DR_REG_EFUSE_BASE + 0x50)
|
||||
/** EFUSE_ADC_CALIBRATION_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Store the bit [22:53] of ADC calibration data.
|
||||
/** EFUSE_DIG_LDO_ACT_DBIAS26_1 : R; bitpos: [2:0]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS26
|
||||
*/
|
||||
#define EFUSE_ADC_CALIBRATION_1 0xFFFFFFFFU
|
||||
#define EFUSE_ADC_CALIBRATION_1_M (EFUSE_ADC_CALIBRATION_1_V << EFUSE_ADC_CALIBRATION_1_S)
|
||||
#define EFUSE_ADC_CALIBRATION_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_ADC_CALIBRATION_1_S 0
|
||||
#define EFUSE_DIG_LDO_ACT_DBIAS26_1 0x00000007U
|
||||
#define EFUSE_DIG_LDO_ACT_DBIAS26_1_M (EFUSE_DIG_LDO_ACT_DBIAS26_1_V << EFUSE_DIG_LDO_ACT_DBIAS26_1_S)
|
||||
#define EFUSE_DIG_LDO_ACT_DBIAS26_1_V 0x00000007U
|
||||
#define EFUSE_DIG_LDO_ACT_DBIAS26_1_S 0
|
||||
/** EFUSE_DIG_LDO_ACT_STEPD10 : R; bitpos: [6:3]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_STEPD10
|
||||
*/
|
||||
#define EFUSE_DIG_LDO_ACT_STEPD10 0x0000000FU
|
||||
#define EFUSE_DIG_LDO_ACT_STEPD10_M (EFUSE_DIG_LDO_ACT_STEPD10_V << EFUSE_DIG_LDO_ACT_STEPD10_S)
|
||||
#define EFUSE_DIG_LDO_ACT_STEPD10_V 0x0000000FU
|
||||
#define EFUSE_DIG_LDO_ACT_STEPD10_S 3
|
||||
/** EFUSE_RTC_LDO_SLP_DBIAS13 : R; bitpos: [13:7]; default: 0;
|
||||
* BLOCK2 DIG_LDO_SLP_DBIAS13
|
||||
*/
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS13 0x0000007FU
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS13_M (EFUSE_RTC_LDO_SLP_DBIAS13_V << EFUSE_RTC_LDO_SLP_DBIAS13_S)
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS13_V 0x0000007FU
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS13_S 7
|
||||
/** EFUSE_RTC_LDO_SLP_DBIAS29 : R; bitpos: [22:14]; default: 0;
|
||||
* BLOCK2 DIG_LDO_SLP_DBIAS29
|
||||
*/
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS29 0x000001FFU
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS29_M (EFUSE_RTC_LDO_SLP_DBIAS29_V << EFUSE_RTC_LDO_SLP_DBIAS29_S)
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS29_V 0x000001FFU
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS29_S 14
|
||||
/** EFUSE_RTC_LDO_SLP_DBIAS31 : R; bitpos: [28:23]; default: 0;
|
||||
* BLOCK2 DIG_LDO_SLP_DBIAS31
|
||||
*/
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS31 0x0000003FU
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS31_M (EFUSE_RTC_LDO_SLP_DBIAS31_V << EFUSE_RTC_LDO_SLP_DBIAS31_S)
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS31_V 0x0000003FU
|
||||
#define EFUSE_RTC_LDO_SLP_DBIAS31_S 23
|
||||
/** EFUSE_RTC_LDO_ACT_DBIAS31 : R; bitpos: [31:29]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS31
|
||||
*/
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS31 0x00000007U
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS31_M (EFUSE_RTC_LDO_ACT_DBIAS31_V << EFUSE_RTC_LDO_ACT_DBIAS31_S)
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS31_V 0x00000007U
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS31_S 29
|
||||
|
||||
/** EFUSE_RD_BLK2_DATA5_REG register
|
||||
* Register 5 of BLOCK2.
|
||||
*/
|
||||
#define EFUSE_RD_BLK2_DATA5_REG (DR_REG_EFUSE_BASE + 0x54)
|
||||
/** EFUSE_ADC_CALIBRATION_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Store the bit [54:85] of ADC calibration data.
|
||||
/** EFUSE_RTC_LDO_ACT_DBIAS31_1 : R; bitpos: [2:0]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS31
|
||||
*/
|
||||
#define EFUSE_ADC_CALIBRATION_2 0xFFFFFFFFU
|
||||
#define EFUSE_ADC_CALIBRATION_2_M (EFUSE_ADC_CALIBRATION_2_V << EFUSE_ADC_CALIBRATION_2_S)
|
||||
#define EFUSE_ADC_CALIBRATION_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_ADC_CALIBRATION_2_S 0
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS31_1 0x00000007U
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS31_1_M (EFUSE_RTC_LDO_ACT_DBIAS31_1_V << EFUSE_RTC_LDO_ACT_DBIAS31_1_S)
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS31_1_V 0x00000007U
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS31_1_S 0
|
||||
/** EFUSE_RTC_LDO_ACT_DBIAS13 : R; bitpos: [10:3]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS13
|
||||
*/
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS13 0x000000FFU
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS13_M (EFUSE_RTC_LDO_ACT_DBIAS13_V << EFUSE_RTC_LDO_ACT_DBIAS13_S)
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS13_V 0x000000FFU
|
||||
#define EFUSE_RTC_LDO_ACT_DBIAS13_S 3
|
||||
/** EFUSE_RESERVED_2_171 : R; bitpos: [31:11]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_171 0x001FFFFFU
|
||||
#define EFUSE_RESERVED_2_171_M (EFUSE_RESERVED_2_171_V << EFUSE_RESERVED_2_171_S)
|
||||
#define EFUSE_RESERVED_2_171_V 0x001FFFFFU
|
||||
#define EFUSE_RESERVED_2_171_S 11
|
||||
|
||||
/** EFUSE_RD_BLK2_DATA6_REG register
|
||||
* Register 6 of BLOCK2.
|
||||
@ -749,9 +895,6 @@ extern "C" {
|
||||
#define EFUSE_CLK_EN_V 0x00000001U
|
||||
#define EFUSE_CLK_EN_S 16
|
||||
|
||||
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||
|
||||
/** EFUSE_CONF_REG register
|
||||
* eFuse operation mode configuraiton register
|
||||
*/
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -165,7 +165,8 @@ typedef union {
|
||||
* Disable programming of individual eFuses.
|
||||
*/
|
||||
uint32_t wr_dis:8;
|
||||
uint32_t reserved_8:24;
|
||||
/** reserved_0_8 : RW; bitpos: [31:8]; default: 0; */
|
||||
uint32_t reserved_0_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_wr_dis_reg_t;
|
||||
@ -196,11 +197,11 @@ typedef union {
|
||||
* The bit be set to disable manual encryption.
|
||||
*/
|
||||
uint32_t dis_download_manual_encrypt:1;
|
||||
/** spi_boot_encrypt_decrypt_cnt : RO; bitpos: [9:7]; default: 0;
|
||||
/** spi_boot_crypt_cnt : RO; bitpos: [9:7]; default: 0;
|
||||
* These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
|
||||
* number of 1: disable.
|
||||
*/
|
||||
uint32_t spi_boot_encrypt_decrypt_cnt:3;
|
||||
uint32_t spi_boot_crypt_cnt:3;
|
||||
/** xts_key_length_256 : RO; bitpos: [10]; default: 0;
|
||||
* The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise,
|
||||
* XTS_AES use 128-bit eFuse data in BLOCK3.
|
||||
@ -236,26 +237,26 @@ typedef union {
|
||||
* The bit be set to enable secure boot.
|
||||
*/
|
||||
uint32_t secure_boot_en:1;
|
||||
/** secure_version : RO; bitpos: [25:22]; default: 0;
|
||||
* Secure version for anti-rollback.
|
||||
/** secure_version : R; bitpos: [25:22]; default: 0;
|
||||
* Secure version for anti-rollback
|
||||
*/
|
||||
uint32_t secure_version:4;
|
||||
/** enable_custom_mac : RO; bitpos: [26]; default: 0;
|
||||
* True if custom_mac is burned.
|
||||
/** custom_mac_used : R; bitpos: [26]; default: 0;
|
||||
* True if MAC_CUSTOM is burned
|
||||
*/
|
||||
uint32_t enable_custom_mac:1;
|
||||
/** disable_wafer_version_major : RO; bitpos: [27]; default: 0;
|
||||
* Disables check of wafer version major.
|
||||
uint32_t custom_mac_used:1;
|
||||
/** disable_wafer_version_major : R; bitpos: [27]; default: 0;
|
||||
* Disables check of wafer version major
|
||||
*/
|
||||
uint32_t disable_wafer_version_major:1;
|
||||
/** disable_blk_version_major : RO; bitpos: [28]; default: 0;
|
||||
* Disables check of blk version major.
|
||||
/** disable_blk_version_major : R; bitpos: [28]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
uint32_t disable_blk_version_major:1;
|
||||
/** rpt4_reserved : RO; bitpos: [31:29]; default: 0;
|
||||
* Reserved (used for four backups method).
|
||||
/** reserved_0_61 : R; bitpos: [31:29]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t rpt4_reserved:3;
|
||||
uint32_t reserved_0_61:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_repeat_data0_reg_t;
|
||||
@ -265,10 +266,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** system_data0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the bits [0:31] of system data.
|
||||
/** custom_mac : R; bitpos: [31:0]; default: 0;
|
||||
* Custom MAC address
|
||||
*/
|
||||
uint32_t system_data0:32;
|
||||
uint32_t custom_mac:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_blk1_data0_reg_t;
|
||||
@ -278,10 +279,14 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** system_data1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the bits [32:63] of system data.
|
||||
/** custom_mac_1 : R; bitpos: [15:0]; default: 0;
|
||||
* Custom MAC address
|
||||
*/
|
||||
uint32_t system_data1:32;
|
||||
uint32_t custom_mac_1:16;
|
||||
/** reserved_1_48 : R; bitpos: [31:16]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_48:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_blk1_data1_reg_t;
|
||||
@ -305,10 +310,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** blk2_data0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Store the bit [0:31] of MAC.
|
||||
/** mac : R; bitpos: [31:0]; default: 0;
|
||||
* MAC address
|
||||
*/
|
||||
uint32_t blk2_data0:32;
|
||||
uint32_t mac:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_blk2_data0_reg_t;
|
||||
@ -318,34 +323,34 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mac_id_high : RO; bitpos: [15:0]; default: 0;
|
||||
* Store the bit [31:47] of MAC.
|
||||
/** mac_1 : R; bitpos: [15:0]; default: 0;
|
||||
* MAC address
|
||||
*/
|
||||
uint32_t mac_id_high:16;
|
||||
/** wafer_version_minor : RO; bitpos: [19:16]; default: 0;
|
||||
* Store wafer version minor.
|
||||
uint32_t mac_1:16;
|
||||
/** wafer_version_minor : R; bitpos: [19:16]; default: 0;
|
||||
* WAFER_VERSION_MINOR
|
||||
*/
|
||||
uint32_t wafer_version_minor:4;
|
||||
/** wafer_version_major : RO; bitpos: [21:20]; default: 0;
|
||||
* Store wafer version major.
|
||||
/** wafer_version_major : R; bitpos: [21:20]; default: 0;
|
||||
* WAFER_VERSION_MAJOR
|
||||
*/
|
||||
uint32_t wafer_version_major:2;
|
||||
/** pkg_version : RO; bitpos: [24:22]; default: 0;
|
||||
* Store package version.
|
||||
/** pkg_version : R; bitpos: [24:22]; default: 0;
|
||||
* EFUSE_PKG_VERSION
|
||||
*/
|
||||
uint32_t pkg_version:3;
|
||||
/** blk_version_minor : RO; bitpos: [27:25]; default: 0;
|
||||
* Store blk 2 efuse version minor.
|
||||
/** blk_version_minor : R; bitpos: [27:25]; default: 0;
|
||||
* Minor version of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_minor:3;
|
||||
/** blk_version_major : RO; bitpos: [29:28]; default: 0;
|
||||
* Store blk 2 efuse version major.
|
||||
/** blk_version_major : R; bitpos: [29:28]; default: 0;
|
||||
* Major version of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_major:2;
|
||||
/** ocode_lo : RO; bitpos: [31:30];
|
||||
* Store ocode.
|
||||
/** ocode : R; bitpos: [31:30]; default: 0;
|
||||
* OCode
|
||||
*/
|
||||
uint32_t ocode_low:2;
|
||||
uint32_t ocode:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_blk2_data1_reg_t;
|
||||
@ -355,18 +360,26 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ocode_hi : RO; bitpos: [4:0];
|
||||
* Store ocode.
|
||||
/** ocode_1 : R; bitpos: [4:0]; default: 0;
|
||||
* OCode
|
||||
*/
|
||||
uint32_t ocode_hi:5;
|
||||
/** ldo_vol_bias_config_high : RO; bitpos: [26:5]; default: 0;
|
||||
* ido configuration parameters.
|
||||
uint32_t ocode_1:5;
|
||||
/** temp_calib : R; bitpos: [13:5]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
uint32_t ldo_vol_bias_config_high:22;
|
||||
/** pvt_low : RO; bitpos: [31:27]; default: 0;
|
||||
* Store the bit [0:4] of pvt.
|
||||
uint32_t temp_calib:9;
|
||||
/** adc1_init_code_atten0 : R; bitpos: [21:14]; default: 0;
|
||||
* ADC1 init code at atten0
|
||||
*/
|
||||
uint32_t pvt_low:5;
|
||||
uint32_t adc1_init_code_atten0:8;
|
||||
/** adc1_init_code_atten3 : R; bitpos: [26:22]; default: 0;
|
||||
* ADC1 init code at atten3
|
||||
*/
|
||||
uint32_t adc1_init_code_atten3:5;
|
||||
/** adc1_cal_vol_atten0 : R; bitpos: [31:27]; default: 0;
|
||||
* ADC1 calibration voltage at atten0
|
||||
*/
|
||||
uint32_t adc1_cal_vol_atten0:5;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_blk2_data2_reg_t;
|
||||
@ -376,11 +389,30 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved1:9;
|
||||
/** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* ADC1 calibration voltage at atten0
|
||||
*/
|
||||
uint32_t adc1_cal_vol_atten0_1:3;
|
||||
/** adc1_cal_vol_atten3 : R; bitpos: [8:3]; default: 0;
|
||||
* ADC1 calibration voltage at atten3
|
||||
*/
|
||||
uint32_t adc1_cal_vol_atten3:6;
|
||||
/** dig_dbias_hvt : R; bitpos: [13:9]; default: 0;
|
||||
* BLOCK2 digital dbias when hvt
|
||||
*/
|
||||
uint32_t dig_dbias_hvt:5;
|
||||
/** dig_ldo_slp_dbias2 : R; bitpos: [20:14]; default: 0;
|
||||
* BLOCK2 DIG_LDO_DBG0_DBIAS2
|
||||
*/
|
||||
uint32_t dig_ldo_slp_dbias2:7;
|
||||
/** dig_ldo_slp_dbias26 : R; bitpos: [28:21]; default: 0;
|
||||
* BLOCK2 DIG_LDO_DBG0_DBIAS26
|
||||
*/
|
||||
uint32_t dig_ldo_slp_dbias26:8;
|
||||
uint32_t dig_ldo_act_dbias26_low:3;
|
||||
/** dig_ldo_act_dbias26 : R; bitpos: [31:29]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS26
|
||||
*/
|
||||
uint32_t dig_ldo_act_dbias26:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_blk2_data3_reg_t;
|
||||
@ -390,12 +422,30 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t dig_ldo_act_dbias26_hi:3;
|
||||
/** dig_ldo_act_dbias26_1 : R; bitpos: [2:0]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS26
|
||||
*/
|
||||
uint32_t dig_ldo_act_dbias26_1:3;
|
||||
/** dig_ldo_act_stepd10 : R; bitpos: [6:3]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_STEPD10
|
||||
*/
|
||||
uint32_t dig_ldo_act_stepd10:4;
|
||||
/** rtc_ldo_slp_dbias13 : R; bitpos: [13:7]; default: 0;
|
||||
* BLOCK2 DIG_LDO_SLP_DBIAS13
|
||||
*/
|
||||
uint32_t rtc_ldo_slp_dbias13:7;
|
||||
/** rtc_ldo_slp_dbias29 : R; bitpos: [22:14]; default: 0;
|
||||
* BLOCK2 DIG_LDO_SLP_DBIAS29
|
||||
*/
|
||||
uint32_t rtc_ldo_slp_dbias29:9;
|
||||
/** rtc_ldo_slp_dbias31 : R; bitpos: [28:23]; default: 0;
|
||||
* BLOCK2 DIG_LDO_SLP_DBIAS31
|
||||
*/
|
||||
uint32_t rtc_ldo_slp_dbias31:6;
|
||||
uint32_t rtc_ldo_act_dbias31_low:3;
|
||||
/** rtc_ldo_act_dbias31 : R; bitpos: [31:29]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS31
|
||||
*/
|
||||
uint32_t rtc_ldo_act_dbias31:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_blk2_data4_reg_t;
|
||||
@ -405,9 +455,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t rtc_ldo_act_dbias31_hi:3;
|
||||
/** rtc_ldo_act_dbias31_1 : R; bitpos: [2:0]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS31
|
||||
*/
|
||||
uint32_t rtc_ldo_act_dbias31_1:3;
|
||||
/** rtc_ldo_act_dbias13 : R; bitpos: [10:3]; default: 0;
|
||||
* BLOCK2 DIG_LDO_ACT_DBIAS13
|
||||
*/
|
||||
uint32_t rtc_ldo_act_dbias13:8;
|
||||
uint32_t reserved2:21;
|
||||
/** reserved_2_171 : R; bitpos: [31:11]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_171:21;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_blk2_data5_reg_t;
|
||||
|
||||
17
components/soc/esp32c3/include/soc/efuse_defs.h
Normal file
17
components/soc/esp32c3/include/soc/efuse_defs.h
Normal file
@ -0,0 +1,17 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
17
components/soc/esp32s2/include/soc/efuse_defs.h
Normal file
17
components/soc/esp32s2/include/soc/efuse_defs.h
Normal file
@ -0,0 +1,17 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
39
components/soc/esp32s3/include/soc/efuse_defs.h
Normal file
39
components/soc/esp32s3/include/soc/efuse_defs.h
Normal file
@ -0,0 +1,39 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||
|
||||
/** EFUSE_RD_MAC_SPI_SYS_2_REG register
|
||||
* BLOCK1 data register 2.
|
||||
*/
|
||||
// #define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
|
||||
/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: Stores the first part of SPI_PAD_CONF..*/
|
||||
#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF
|
||||
#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S))
|
||||
#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF
|
||||
#define EFUSE_SPI_PAD_CONF_1_S 0
|
||||
|
||||
/** EFUSE_RD_MAC_SPI_SYS_3_REG register
|
||||
* BLOCK1 data register 3.
|
||||
*/
|
||||
//#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
|
||||
/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
|
||||
/*description: Stores the second part of SPI_PAD_CONF..*/
|
||||
#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF
|
||||
#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S))
|
||||
#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF
|
||||
#define EFUSE_SPI_PAD_CONF_2_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user