Commit Graph

57 Commits

Author SHA1 Message Date
Konstantin Kondrashov
8d6562d1f1 Merge branch 'feature/c5_c61_efuse_update' into 'master'
feat(efuse): Update efuses for C5 and C61

Closes IDF-8629 and IDF-8674

See merge request espressif/esp-idf!29627
2024-03-22 18:02:37 +08:00
Kevin (Lao Kaiyao)
4cd30f9b8f Merge branch 'feature/esp32c5_mp_bringup' into 'master'
feat(esp32c5): bringup esp32c5 mp (Stage 7/7: hello world)

See merge request espressif/esp-idf!29093
2024-03-22 11:18:52 +08:00
Konstantin Kondrashov
25bc10e143 feat(efuse): Update efuses for C5 and C61 2024-03-21 18:37:46 +02:00
laokaiyao
c9d6a11d1d feat(esp32c5mp): support to run hello world on esp32c5 mp 2024-03-21 16:18:03 +08:00
nilesh.kale
ef3b40c5f1 feat: enable RSA support for c5
This commit enables RSA peripheral support for ESP32-C5.
2024-03-19 13:46:49 +05:30
Marius Vikhammer
4700f709ca Merge branch 'feature/c5_ulp' into 'master'
feat(ulp): add basic support for running lp core on C5

Closes IDF-8637

See merge request espressif/esp-idf!29496
2024-03-19 11:33:51 +08:00
Armando
5efcd8979e feat(cache mmu): c5 support 2024-03-18 11:31:10 +08:00
laokaiyao
8de41350eb feat(esp32c5mp): support to build g0 components 2024-03-14 15:09:22 +08:00
morris
9b8fd65221 feat(rmt): basic driver support on esp32c5 2024-03-13 17:37:47 +08:00
Marius Vikhammer
a32fb07e7b feat(ulp): add basic support for running lp core on C5 2024-03-13 17:37:29 +08:00
laokaiyao
b1a3e92f2a fix(esp32c5mp): fix public headers 2024-03-11 20:45:09 +08:00
laokaiyao
71257c6ef4 feat(esp32c5mp): update hal files for esp32c5 mp 2024-03-11 17:23:43 +08:00
laokaiyao
881782f83d feat(esp32c5mp): add soc files part 2 2024-03-08 10:48:25 +08:00
wanlei
0cf11e5b87 feat(spi): add esp32c5 spi support 2024-03-07 18:11:48 +08:00
Kevin (Lao Kaiyao)
413c53d39a Merge branch 'feature/support_esp32c5_mp_target' into 'master'
feat(esp32c5mp): add soc files (stage 2/8, part 1/2)

See merge request espressif/esp-idf!29369
2024-03-06 14:19:40 +08:00
laokaiyao
a56b575535 feat(esp32c5mp): add soc files part 1
The files in this part are auto generated
2024-03-05 16:18:02 +08:00
laokaiyao
cfc1584594 feat(esp32c5): support to set esp32c5 mp target in Kconfig 2024-03-05 16:17:53 +08:00
Guillaume Souchere
0b9f01ac20 feat(soc): Add soc_caps macros for sleep support
- modify console example to use the new SOC_LIGHT_SLEEP_SUPPORTED
and SOC_DEEP_SLEEP_SUPPORTED macros when registering sleep commands

- remove exclusion of esp32p4 in basic and advanced example in
.build-test-rules.yml

- replace exclusion of esp32p4 for deep and light sleep tests with newly introduced macro

- remove the temporary disable check for esp32p4 and uses the
SOC_LIGHT_SLEEP_SUPPORTED maccro instead.
2024-03-05 07:05:40 +01:00
gaoxu
7075b61a6a docs(uart): update lp uart and p4/c5 uart programming guide 2024-03-01 16:21:22 +08:00
laokaiyao
01e3c85322 refactor(esp32c5): change beta3 path in esp_system and bootloader 2024-03-01 11:12:36 +08:00
laokaiyao
db2435fd14 feat(soc_cap_kconfig): support to search recursively 2024-03-01 10:17:17 +08:00
laokaiyao
319e30ac38 refactor(esp32c5): change beta3 path in soc 2024-03-01 10:16:14 +08:00
C.S.M
1360f1b0a9 Merge branch 'feature/i2c_support_esp32c5' into 'master'
feat(i2c): Add I2C support on ESP32C5

Closes IDF-8694 and IDF-8696

See merge request espressif/esp-idf!29196
2024-02-29 21:51:45 +08:00
gaoxu
f9109beda2 feat(uart): add HP/LP uart support on ESP32C5 2024-02-29 14:12:51 +08:00
Cao Sen Miao
ddb0c21d4c feat(i2c): Add I2C support on ESP32C5 2024-02-29 12:13:39 +08:00
Song Ruo Jing
98d9f04b00 feat(gdma): add GDMA support for ESP32C5 2024-02-28 12:38:02 +08:00
Cao Sen Miao
cf521b60ea feat(i2c): Support i2c sleep retention on esp32c6/h2 2024-02-23 11:28:14 +08:00
Mahavir Jain
b44387fd9b Merge branch 'feature/enable_ecc_support_for_c5' into 'master'
feat: added ecc peripheral support for esp32c5

Closes IDF-8625

See merge request espressif/esp-idf!29053
2024-02-22 16:36:30 +08:00
Marius Vikhammer
c3ecd6d1f7 Merge branch 'bugfix/reset_reasons' into 'master'
Update reset reasons for C6, H2, P4 and C5

Closes IDF-5719 and IDF-8660

See merge request espressif/esp-idf!28999
2024-02-22 11:02:29 +08:00
nilesh.kale
747ee60dd5 feat: added ecc peripheral support for esp32c5
This commits adds support for ECC peripheral for ESP32C5
This is tested on mbedtls and hal testapps.
2024-02-21 14:52:56 +05:30
Marius Vikhammer
4ce4af61ad fix(system): update reset reasons for P4 and C5 2024-02-21 11:59:28 +08:00
gaoxu
3ac736bc95 feat(gpio): add gpio support on ESP32C5 2024-02-20 14:57:25 +08:00
morris
49e7228be9 feat(gptimer): basic driver support on esp32c5 2024-02-19 10:27:18 +08:00
Song Ruo Jing
95133c179f feat(clk): preliminary clock tree support for ESP32C5 2024-02-07 14:38:15 +08:00
laokaiyao
c0c6af99e9 fix(esp32c5): fixed the lack of crosscore ll on c5 2024-02-05 12:39:35 +08:00
Wu Zheng Hui
5454d37d49 Merge branch 'feature/support_gdma_retention' into 'master'
feature: support gdma retention in pd_top lightsleep

Closes IDF-7704 and IDFGH-11389

See merge request espressif/esp-idf!27246
2024-02-04 20:17:02 +08:00
wuzhenghui
0c2f811ca8
feat(esp_hw_support): support gdma register context sleep retention 2024-02-02 11:21:40 +08:00
Marius Vikhammer
4d28524bdb docs(esp32c5): add support for building C5 docs 2024-02-01 10:06:41 +08:00
Song Ruo Jing
cf93777077 refactor(rtc): move soc/rtc.h from soc to esp_hw_support component
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
2024-01-25 19:15:33 +08:00
Wu Zheng Hui
55f04b3326 Merge branch 'feature/clean_up_retention_context_definitions' into 'master'
refactor(esp_hw_support): move sleep retention context definition to soc target folder

Closes PM-10

See merge request espressif/esp-idf!26753
2024-01-24 20:24:02 +08:00
wuzhenghui
f3f12e973c
refactor(esp_hw_support): separate different chip system peripheral regs context defs to target folder 2024-01-23 13:30:01 +08:00
wuzhenghui
9b3dc69908
refactor(esp_hw_support): move regdma structure defination to soc components 2024-01-23 11:51:44 +08:00
Mahavir Jain
9ecd2fd7e3 fix(soc): change debug addr range to CPU subsystem range
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-22 13:34:32 +08:00
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
laokaiyao
d0a8f3e5c4 feat(esp32c5): support esptool on esp32c5 beta3 2024-01-09 13:11:11 +08:00
laokaiyao
3d459e423a feat(esp32c5): support esp32c5 beta3 48M xtal 2024-01-09 13:11:11 +08:00
laokaiyao
96a4ead083 feat(esp32c5): support to run hello world on esp32c5 beta3 2024-01-09 13:11:11 +08:00
laokaiyao
11e19f40b9 feat(esp32c5): support to build hello world on esp32c5 beta3 2024-01-09 13:11:11 +08:00
Song Ruo Jing
7f2b85b82b feat(clk): add basic clock support for esp32p4
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
2023-12-29 00:37:26 +08:00
laokaiyao
fcc9293f66 change(esp32c5): update soc files for esp32c5 beta3 2023-12-28 10:23:15 +08:00