alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

feat(esp32c5mp): update hal files for esp32c5 mp

Browse Source
This commit is contained in:
laokaiyao 2024-03-11 10:30:36 +08:00
parent 0bbee51829
commit 71257c6ef4
14 changed files with 612 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
components/hal/esp32c5/clk_tree_hal.c
View File

@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h" // TODO: IDF-9197
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/assert.h"
@ -16,10 +17,15 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
switch (cpu_clk_src) {
case SOC_CPU_CLK_SRC_XTAL:
return clk_hal_xtal_get_freq_mhz();
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_CPU_CLK_SRC_PLL_F160M:
return CLK_LL_PLL_160M_FREQ_MHZ;
case SOC_CPU_CLK_SRC_PLL_F240M:
return CLK_LL_PLL_240M_FREQ_MHZ;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_CPU_CLK_SRC_PLL:
return clk_ll_bbpll_get_freq_mhz();
#endif
case SOC_CPU_CLK_SRC_RC_FAST:
return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
default:
@ -32,14 +38,22 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
uint32_t clk_hal_cpu_get_freq_hz(void)
{
soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t divider = clk_ll_cpu_get_divider();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_cpu_get_hs_divider() : clk_ll_cpu_get_ls_divider();
#endif
return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
}
uint32_t clk_hal_ahb_get_freq_hz(void)
{
soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t divider = clk_ll_ahb_get_divider();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_ahb_get_hs_divider() : clk_ll_ahb_get_ls_divider();
#endif
return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
}
@ -51,8 +65,10 @@ uint32_t clk_hal_apb_get_freq_hz(void)
uint32_t clk_hal_lp_slow_get_freq_hz(void)
{
switch (clk_ll_rtc_slow_get_src()) {
// case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
// return SOC_CLK_RC_SLOW_FREQ_APPROX;
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
return SOC_CLK_RC_SLOW_FREQ_APPROX;
#endif
case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
return SOC_CLK_XTAL32K_FREQ_APPROX;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:

4
components/hal/esp32c5/efuse_hal.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -108,5 +108,5 @@ bool efuse_hal_is_coding_error_in_block(unsigned block)
// uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
// return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
// }
// return false;
return false;
}

100
components/hal/esp32c5/include/hal/cache_ll.h
View File

@ -9,9 +9,12 @@
#pragma once
#include <stdbool.h>
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#include "sdkconfig.h" // TODO: remove
#include "soc/cache_reg.h"
// #include "soc/ext_mem_defs.h"
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "soc/ext_mem_defs.h"
#include "rom/cache.h"
#endif
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32c5/rom/cache.h"
@ -66,8 +69,13 @@ __attribute__((always_inline))
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
(void) type;
Cache_Disable_ICache();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
(void) type;
Cache_Disable_Cache();
#endif
}
/**
@ -83,7 +91,11 @@ __attribute__((always_inline))
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Enable_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#endif
}
/**
@ -97,7 +109,11 @@ __attribute__((always_inline))
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Suspend_ICache();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Suspend_Cache();
#endif
}
/**
@ -113,7 +129,11 @@ __attribute__((always_inline))
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Resume_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#endif
}
/**
@ -145,7 +165,11 @@ __attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Freeze_Enable(CACHE_FREEZE_ACK_BUSY);
#endif
}
/**
@ -159,7 +183,11 @@ __attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Freeze_ICache_Disable();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Freeze_Disable();
#endif
}
/**
@ -175,9 +203,15 @@ __attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t size = 0;
size = Cache_Get_ICache_Line_Size();
return size;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t size = 0;
size = Cache_Get_Line_Size(CACHE_MAP_FLASH_CACHE);
return size;
#endif
}
/**
@ -196,6 +230,7 @@ __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// cache_bus_mask_t mask = (cache_bus_mask_t)0;
// // uint32_t vaddr_end = vaddr_start + len - 1;
@ -207,6 +242,20 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
// }
// // return mask;
return (cache_bus_mask_t)0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
//c6 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
} else {
HAL_ASSERT(0); //Out of region
}
return mask;
#endif
}
/**
@ -221,6 +270,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
// HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@ -230,6 +280,19 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
// // uint32_t dbus_mask = 0;
// dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
// REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
#endif
}
/**
@ -241,8 +304,9 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
abort();
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
// HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@ -252,6 +316,19 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
// // uint32_t dbus_mask = 0;
// dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
// REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
#endif
}
/**
@ -267,8 +344,9 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
__attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
abort();
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// bool valid = false;
// uint32_t vaddr_end = vaddr_start + len - 1;
// // valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
@ -279,6 +357,20 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
// }
// // return valid;
return (bool)0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
bool valid = false;
uint32_t vaddr_end = vaddr_start + len - 1;
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
if (valid) {
*out_level = 1;
*out_id = 0;
}
return valid;
#endif
}
/*------------------------------------------------------------------------------

252
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@ -7,6 +7,7 @@
#pragma once
#include <stdint.h>
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
@ -303,7 +304,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
uint8_t dr3;
uint8_t dchgp;
uint8_t dbias;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint8_t href = 3;
uint8_t lref = 1;
/* Configure 480M PLL */
@ -333,17 +334,42 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dbias = 2;
break;
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint8_t dcur;
/* Configure 480M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_40M:
default:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
}
#endif
uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
uint8_t i2c_bbpll_div_7_0 = div7_0;
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint8_t i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
#endif
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, lref);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, href);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
#endif
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num
*/
@ -352,6 +378,7 @@ static inline __attribute__((always_inline)) void clk_ll_bus_update(void)
PCR.bus_clk_update.bus_clock_update = 1;
while (PCR.bus_clk_update.bus_clock_update);
}
#endif
/**
* @brief Select the clock source for CPU_CLK (SOC Clock Root)
@ -364,6 +391,7 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk
case SOC_CPU_CLK_SRC_XTAL:
PCR.sysclk_conf.soc_clk_sel = 0;
break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_CPU_CLK_SRC_RC_FAST:
PCR.sysclk_conf.soc_clk_sel = 1;
break;
@ -373,6 +401,14 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk
case SOC_CPU_CLK_SRC_PLL_F240M:
PCR.sysclk_conf.soc_clk_sel = 3;
break;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_CPU_CLK_SRC_PLL:
PCR.sysclk_conf.soc_clk_sel = 1;
break;
case SOC_CPU_CLK_SRC_RC_FAST:
PCR.sysclk_conf.soc_clk_sel = 2;
break;
#endif
default:
// Unsupported SOC_CLK mux input sel
abort();
@ -391,17 +427,24 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr
case 0:
return SOC_CPU_CLK_SRC_XTAL;
case 1:
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return SOC_CPU_CLK_SRC_RC_FAST;
case 2:
return SOC_CPU_CLK_SRC_PLL_F160M;
case 3:
return SOC_CPU_CLK_SRC_PLL_F240M;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
return SOC_CPU_CLK_SRC_PLL;
case 2:
return SOC_CPU_CLK_SRC_RC_FAST;
#endif
default:
// Invalid SOC_CLK_SEL value
return SOC_CPU_CLK_SRC_INVALID;
}
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Set CPU_CLK's divider
*
@ -450,6 +493,134 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(voi
return (hp_root_ls_div + 1) * (ahb_div + 1);
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
/**
* @brief Set CPU_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
*
* @param divider Divider. (PCR_HS_DIV_NUM + 1) * (PCR_CPU_HS_DIV_NUM + 1) = divider.
*/
static inline __attribute__((always_inline)) void clk_ll_cpu_set_hs_divider(uint32_t divider)
{
// SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> CPU_CLK
// (1) not configurable for the target (HRO register field: PCR_HS_DIV_NUM)
// Fixed at 3 for HS clock source
// Corresponding register field value is PCR_HS_DIV_NUM=2
// (2) configurable
// HS divider option: 1, 2, 4 (PCR_CPU_HS_DIV_NUM=0, 1, 3)
HAL_ASSERT(divider == 3 || divider == 4 || divider == 6 || divider == 12);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, (divider / 3) - 1);
// 120MHz CPU freq cannot be achieved through divider, need to set force_120m
// This field is only valid if PCR_CPU_HS_DIV_NUM=0 and PCR_SOC_CLK_SEL=SOC_CPU_CLK_SRC_PLL
// bool force_120m = (divider == 4) ? 1 : 0;
// PCR.cpu_freq_conf.cpu_hs_120m_force = force_120m;
}
/**
* @brief Set CPU_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST)
*
* @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_CPU_LS_DIV_NUM + 1) = divider.
*/
static inline __attribute__((always_inline)) void clk_ll_cpu_set_ls_divider(uint32_t divider)
{
// SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> CPU_CLK
// (1) not configurable for the target (HRO register field: PCR_LS_DIV_NUM)
// Fixed at 1 for LS clock source
// Corresponding register field value is PCR_LS_DIV_NUM=0
// (2) configurable
// LS divider option: 1, 2, 4, 8, 16, 32 (PCR_CPU_LS_DIV_NUM=0, 1, 3, 7, 15, 31)
HAL_ASSERT((divider > 0) && ((divider & (divider - 1)) == 0));
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, divider - 1);
}
/**
* @brief Get CPU_CLK's high-speed divider
*
* @return Divider. Divider = (PCR_HS_DIV_NUM + 1) * (PCR_CPU_HS_DIV_NUM + 1).
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_hs_divider(void)
{
// uint32_t force_120m = PCR.cpu_freq_conf.cpu_hs_120m_force;
uint32_t cpu_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num);
if (cpu_hs_div == 0) {
return 4;
}
uint32_t hp_root_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, hs_div_num);
return (hp_root_hs_div + 1) * (cpu_hs_div + 1);
}
/**
* @brief Get CPU_CLK's low-speed divider
*
* @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_CPU_LS_DIV_NUM + 1).
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_ls_divider(void)
{
uint32_t cpu_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num);
uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num);
return (hp_root_ls_div + 1) * (cpu_ls_div + 1);
}
/**
* @brief Set AHB_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
*
* @param divider Divider. (PCR_HS_DIV_NUM + 1) * (PCR_AHB_HS_DIV_NUM + 1) = divider.
*/
static inline __attribute__((always_inline)) void clk_ll_ahb_set_hs_divider(uint32_t divider)
{
// SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> AHB_CLK
// (1) not configurable for the target (HRO register field: PCR_HS_DIV_NUM)
// Fixed at 3 for HS clock source
// Corresponding register field value is PCR_HS_DIV_NUM=2
// (2) configurable
// HS divider option: 4, 8, 16 (PCR_AHB_HS_DIV_NUM=3, 7, 15)
HAL_ASSERT(divider == 12 || divider == 24 || divider == 48);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, (divider / 3) - 1);
}
/**
* @brief Set AHB_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST)
*
* @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1) = divider.
*/
static inline __attribute__((always_inline)) void clk_ll_ahb_set_ls_divider(uint32_t divider)
{
// SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> AHB_CLK
// (1) not configurable for the target (HRO register field: PCR_LS_DIV_NUM)
// Fixed at 1 for LS clock source
// Corresponding register field value is PCR_LS_DIV_NUM=0
// (2) configurable
// LS divider option: 1, 2, 4, 8, 16, 32 (PCR_CPU_LS_DIV_NUM=0, 1, 3, 7, 15, 31)
HAL_ASSERT((divider > 0) && ((divider & (divider - 1)) == 0));
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1);
}
/**
* @brief Get AHB_CLK's high-speed divider
*
* @return Divider. Divider = (PCR_HS_DIV_NUM + 1) * (PCR_AHB_HS_DIV_NUM + 1).
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_hs_divider(void)
{
uint32_t ahb_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num);
uint32_t hp_root_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, hs_div_num);
return (hp_root_hs_div + 1) * (ahb_hs_div + 1);
}
/**
* @brief Get AHB_CLK's low-speed divider
*
* @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1).
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_ls_divider(void)
{
uint32_t ahb_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num);
uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num);
return (hp_root_ls_div + 1) * (ahb_ls_div + 1);
}
#endif
/**
* @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider
*
@ -473,6 +644,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Select the clock source for MSPI_FAST_CLK
*
@ -506,6 +678,62 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_divider(u
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, divider - 1);
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
/**
* @brief Set MSPI_FAST_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
*
* @param divider Divider.
*/
static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_hs_divider(uint32_t divider)
{
// SOC_ROOT_CLK ------> MSPI_FAST_CLK
// HS divider option: 4, 5, 6 (PCR_MSPI_FAST_HS_DIV_NUM=3, 4, 5)
uint32_t div_num = 0;
switch (divider) {
case 4:
div_num = 3;
break;
case 5:
div_num = 4;
break;
case 6:
div_num = 5;
break;
default:
// Unsupported HS MSPI_FAST divider
abort();
}
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, div_num);
}
/**
* @brief Set MSPI_FAST_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST)
*
* @param divider Divider.
*/
static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divider(uint32_t divider)
{
// SOC_ROOT_CLK ------> MSPI_FAST_CLK
// LS divider option: 1, 2, 4 (PCR_MSPI_FAST_LS_DIV_NUM=0, 1, 2)
uint32_t div_num = 0;
switch (divider) {
case 1:
div_num = 0;
break;
case 2:
div_num = 1;
break;
case 4:
div_num = 2;
break;
default:
// Unsupported LS MSPI_FAST divider
abort();
}
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, div_num);
}
#endif
/**
* @brief Select the calibration 32kHz clock source for timergroup0
*
@ -557,9 +785,11 @@ static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_c
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
{
switch (in_sel) {
// case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
// LP_CLKRST.lp_clk_conf.slow_clk_sel = 0;
// break;
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
LP_CLKRST.lp_clk_conf.slow_clk_sel = 0;
break;
#endif
case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
LP_CLKRST.lp_clk_conf.slow_clk_sel = 1;
break;
@ -584,8 +814,10 @@ static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_s
{
uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel;
switch (clk_sel) {
// case 0:
// return SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case 0:
return SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
#endif
case 1:
return SOC_RTC_SLOW_CLK_SRC_XTAL32K;
case 2:
@ -611,9 +843,11 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rt
case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
LP_CLKRST.lp_clk_conf.fast_clk_sel = 1;
break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_RTC_FAST_CLK_SRC_XTAL:
LP_CLKRST.lp_clk_conf.fast_clk_sel = 2;
break;
#endif
default:
// Unsupported RTC_FAST_CLK mux input sel
abort();
@ -633,8 +867,10 @@ static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_f
return SOC_RTC_FAST_CLK_SRC_RC_FAST;
case 1:
return SOC_RTC_FAST_CLK_SRC_XTAL_D2;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case 2:
return SOC_RTC_FAST_CLK_SRC_XTAL;
#endif
default:
return SOC_RTC_FAST_CLK_SRC_INVALID;
}
@ -746,7 +982,11 @@ Set the frequency division factor of ref_tick
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
PCR.ctrl_tick_conf.fosc_tick_num = REG_FOSC_TICK_NUM;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
PCR.ctrl_32k_conf.fosc_tick_num = REG_FOSC_TICK_NUM;
#endif
}

16
components/hal/esp32c5/include/hal/ecc_ll.h
View File

@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "hal/assert.h"
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"
@ -20,9 +21,11 @@ typedef enum {
ECC_PARAM_PX = 0x0,
ECC_PARAM_PY,
ECC_PARAM_K,
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
ECC_PARAM_QX,
ECC_PARAM_QY,
ECC_PARAM_QZ,
#endif
} ecc_ll_param_t;
/**
@ -42,9 +45,10 @@ static inline void ecc_ll_reset_register(void)
{
PCR.ecc_conf.ecc_rst_en = 1;
PCR.ecc_conf.ecc_rst_en = 0;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Clear reset on ECDSA, otherwise ECC is held in reset
PCR.ecdsa_conf.ecdsa_rst_en = 0;
#endif
}
static inline void ecc_ll_enable_interrupt(void)
@ -74,6 +78,7 @@ static inline void ecc_ll_set_mode(ecc_mode_t mode)
case ECC_MODE_VERIFY_THEN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case ECC_MODE_JACOBIAN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
break;
@ -98,6 +103,7 @@ static inline void ecc_ll_set_mode(ecc_mode_t mode)
case ECC_MODE_INVERSE_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
break;
#endif
default:
HAL_ASSERT(false && "Unsupported mode");
break;
@ -119,6 +125,7 @@ static inline void ecc_ll_set_curve(ecc_curve_t curve)
}
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
{
switch(base) {
@ -133,6 +140,7 @@ static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
return;
}
}
#endif
static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len)
{
@ -148,6 +156,7 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
case ECC_PARAM_K:
reg = ECC_MULT_K_MEM;
break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case ECC_PARAM_QX:
reg = ECC_MULT_QX_MEM;
break;
@ -157,6 +166,7 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
case ECC_PARAM_QZ:
reg = ECC_MULT_QZ_MEM;
break;
#endif
default:
HAL_ASSERT(false && "Invalid parameter");
return;
@ -193,10 +203,12 @@ static inline ecc_curve_t ecc_ll_get_curve(void)
return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
{
return (ecc_mod_base_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE));
}
#endif
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)
{
@ -211,6 +223,7 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
case ECC_PARAM_K:
reg = ECC_MULT_K_MEM;
break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case ECC_PARAM_QX:
reg = ECC_MULT_QX_MEM;
break;
@ -220,6 +233,7 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
case ECC_PARAM_QZ:
reg = ECC_MULT_QZ_MEM;
break;
#endif
default:
HAL_ASSERT(false && "Invalid parameter");
return;

2
components/hal/esp32c5/include/hal/efuse_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

149
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@ -16,17 +16,28 @@
#include <stdlib.h>
#include <stdbool.h>
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/lp_io_struct.h"
#include "soc/pmu_struct.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "soc/lp_io_struct.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/usb_serial_jtag_struct.h"
#include "soc/io_mux_struct.h"
#include "hal/gpio_types.h"
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "soc/lp_gpio_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/io_mux_struct.h"
#include "hal/gpio_types.h"
#include "hal/misc.h"
#endif
#include "hal/assert.h"
#ifdef __cplusplus
@ -77,7 +88,12 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpu = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
abort();
#endif
}
/**
@ -89,7 +105,12 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpu = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
abort();
#endif
}
/**
@ -100,7 +121,12 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpd = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
abort();
#endif
}
/**
@ -117,11 +143,20 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
// Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IOMUX.gpio[gpio_num].fun_wpd = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
// SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
// }
// REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
abort();
#endif
}
/**
@ -147,7 +182,11 @@ __attribute__((always_inline))
static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
(void)core_id;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
*status = hw->pcpu_int.procpu_int;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -222,7 +261,12 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_ie = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -233,7 +277,12 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_ie = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -244,7 +293,12 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].filter_en = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -255,9 +309,15 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].filter_en = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Enable GPIO hysteresis
*
@ -285,6 +345,7 @@ static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t
IOMUX.gpio[gpio_num].hys_sel = 1;
IOMUX.gpio[gpio_num].hys_en = 0;
}
#endif
/**
* @brief Disable output mode on GPIO.
@ -400,7 +461,12 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_drv = strength;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
abort();
#endif
}
/**
@ -412,7 +478,12 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
*strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
abort();
#endif
}
/**
@ -477,10 +548,18 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Disable USB Serial JTAG if pins 25 or pins 26 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO25_REG || pin_name == IO_MUX_GPIO26_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
// if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// }
abort();
#endif
PIN_FUNC_SELECT(pin_name, func);
}
@ -506,11 +585,20 @@ static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t
__attribute__((always_inline))
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Disable USB Serial JTAG if pins 25 or pins 26 needs to select an IOMUX function
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
IOMUX.gpio[gpio_num].mcu_sel = func;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
// if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// }
// PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
abort();
#endif
}
/**
@ -537,6 +625,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
{
switch (src) {
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
break;
@ -546,6 +635,14 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
case SOC_MOD_CLK_PLL_F80M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
break;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
break;
case SOC_MOD_CLK_PLL_F80M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
break;
#endif
default:
// Unsupported IO_MUX clock source
HAL_ASSERT(false);
@ -597,7 +694,12 @@ static inline void gpio_ll_force_unhold_all(void)
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].slp_sel = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -609,7 +711,12 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].slp_sel = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -620,7 +727,12 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpu = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -631,7 +743,12 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpu = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -642,7 +759,12 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpd = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -653,7 +775,12 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpd = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -664,7 +791,12 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_ie = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -675,7 +807,12 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
*/
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_ie = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -686,7 +823,12 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_oe = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@ -697,7 +839,12 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_oe = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
#ifdef __cplusplus

2
components/hal/esp32c5/include/hal/mmu_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

17
components/hal/esp32c5/include/hal/spi_ll.h
View File

@ -16,6 +16,7 @@
#include <stdlib.h> //for abs()
#include <string.h>
#include "sdkconfig.h" // TODO: [ESP32C5] IDF-8698 remove
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
@ -149,12 +150,15 @@ static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_s
{
uint32_t clk_id = 0;
switch (clk_source) {
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_MOD_CLK_PLL_F160M:
clk_id = 1;
break;
case SOC_MOD_CLK_RC_FAST:
clk_id = 2;
break;
#endif
case SOC_MOD_CLK_XTAL:
clk_id = 0;
break;
@ -426,12 +430,15 @@ static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable)
*/
static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen)
{
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
for (int x = 0; x < bitlen; x += 32) {
//Use memcpy to get around alignment issues for txdata
uint32_t word;
memcpy(&word, &buffer_to_send[x / 8], 4);
hw->data_buf[(x / 32)].buf = word;
}
#endif
}
/**
@ -447,7 +454,8 @@ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t
HAL_ASSERT(byte_id + len <= 64);
HAL_ASSERT(len > 0);
HAL_ASSERT(byte_id >= 0);
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
while (len > 0) {
uint32_t word;
int offset = byte_id % 4;
@ -467,6 +475,7 @@ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t
byte_id += copy_len;
len -= copy_len;
}
#endif
}
/**
@ -478,6 +487,8 @@ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t
*/
static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen)
{
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
for (int x = 0; x < bitlen; x += 32) {
//Do a memcpy to get around possible alignment issues in rx_buffer
uint32_t word = hw->data_buf[x / 32].buf;
@ -487,6 +498,7 @@ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, siz
}
memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8);
}
#endif
}
/**
@ -499,6 +511,8 @@ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, siz
*/
static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len)
{
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
while (len > 0) {
uint32_t word = hw->data_buf[byte_id / 4].buf;
int offset = byte_id % 4;
@ -512,6 +526,7 @@ static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *
out_data += copy_len;
len -= copy_len;
}
#endif
}
/*------------------------------------------------------------------------------

7
components/hal/esp32c5/include/hal/spimem_flash_ll.h
View File

@ -18,6 +18,7 @@
#include <sys/param.h> // For MIN/MAX
#include <stdbool.h>
#include <string.h>
#include "sdkconfig.h" // TODO: remove
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
@ -27,6 +28,7 @@
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include "soc/pcr_struct.h"
#include "esp_rom_sys.h"
#ifdef __cplusplus
extern "C" {
@ -624,12 +626,17 @@ static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_
*/
static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// TODO: [ESP32C5] IDF-8649
// MAY CAN IMPROVE (ONLY rc_fast case is incorrect)!
// TODO: Default is PLL480M, this is hard-coded.
// In the future, we can get the CPU clock source by calling interface.
// HAL_ASSERT(HAL_FORCE_READ_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_func_clk_sel) == 2);
return 40; // Use Xtal clock source
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// TODO: [ESP32C5] IDF-8649
return 80;
#endif
}
/**

49
components/hal/esp32c5/include/hal/timer_ll.h
View File

@ -10,6 +10,7 @@
#pragma once
#include <stdbool.h>
#include "sdkconfig.h" // TODO: remove
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/timer_types.h"
@ -26,6 +27,7 @@ extern "C" {
#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
/**
* @brief Enable the bus clock for timer group module
*
@ -131,7 +133,12 @@ static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, boo
__attribute__((always_inline))
static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en)
{
(void)timer_num;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
hw->hw_timer[timer_num].config.tx_alarm_en = en;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -147,8 +154,12 @@ static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_nu
if (divider >= 65536) {
divider = 0;
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -162,7 +173,11 @@ static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_nu
__attribute__((always_inline))
static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
hw->hw_timer[timer_num].config.tx_autoreload = en;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -174,7 +189,11 @@ static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_nu
*/
static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -188,7 +207,11 @@ static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_n
__attribute__((always_inline))
static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
hw->hw_timer[timer_num].config.tx_en = en;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -200,11 +223,15 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b
__attribute__((always_inline))
static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
hw->hw_timer[timer_num].update.tx_update = 1;
// Timer register is in a different clock domain from Timer hardware logic
// We need to wait for the update to take effect before fetching the count value
while (hw->hw_timer[timer_num].update.tx_update) {
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -218,7 +245,12 @@ static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_
__attribute__((always_inline))
static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
return 0;
#endif
}
/**
@ -231,8 +263,12 @@ static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer
__attribute__((always_inline))
static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32);
hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -245,8 +281,12 @@ static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num,
__attribute__((always_inline))
static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32);
hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -259,7 +299,12 @@ static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num,
__attribute__((always_inline))
static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
return 0;
#endif
}
/**
@ -271,7 +316,11 @@ static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_
__attribute__((always_inline))
static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
hw->hw_timer[timer_num].load.tx_load = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**

11
components/hal/esp32c5/include/hal/uart_ll.h
View File

@ -9,6 +9,7 @@
#pragma once
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "esp_attr.h"
#include "hal/misc.h"
#include "hal/uart_types.h"
@ -166,7 +167,12 @@ FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, ui
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// TODO: [ESP32c5] IDF-8633 Not found sclk_div_num for LP_UART
abort();
#endif
uart_ll_update(hw);
}
@ -431,7 +437,12 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
div_reg.val = hw->clkdiv_sync.val;
int sclk_div;
if ((hw) == &LP_UART) {
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// TODO: [ESP32c5] IDF-8633 Not found sclk_div_num for LP_UART
abort();
#endif
} else {
sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1;
}

33
components/soc/esp32c5/mp/include/soc/mmu.h
View File

@ -1,33 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defined for flash mmap */
#define SOC_MMU_REGIONS_COUNT 1
#define SOC_MMU_PAGES_PER_REGION 256
#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
#define SOC_MMU_ADDR_MASK (SOC_MMU_VALID - 1)
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM0_CACHE_ADDRESS_LOW
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
#define SOC_MMU_VADDR0_START_ADDR (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
#ifdef __cplusplus
}
#endif

4
components/soc/include/soc/rtc_cntl_periph.h
View File

@ -9,7 +9,7 @@
#include "sdkconfig.h"
// TODO: IDF-5645
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "soc/lp_io_reg.h"
#include "soc/lp_io_struct.h"
#include "soc/lp_aon_reg.h"
@ -17,7 +17,7 @@
// ESP32H2-TODO: IDF-6327
#elif CONFIG_IDF_TARGET_ESP32H2
#include "soc/lp_aon_reg.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#elif CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "soc/lp_gpio_reg.h"
#include "soc/lp_gpio_struct.h"
#include "soc/lp_iomux_reg.h"