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https://github.com/espressif/esp-idf.git
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feat(i2c): Support i2c sleep retention on esp32c6/h2
This commit is contained in:
Cao Sen Miao
parent
000d1407ea
commit
cf521b60ea
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -28,6 +28,10 @@
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#include "esp_rom_sys.h"
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#include <sys/param.h>
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#include "soc/clk_tree_defs.h"
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
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#include "esp_private/sleep_retention.h"
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#endif
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#if SOC_I2C_SUPPORT_APB || SOC_I2C_SUPPORT_XTAL
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#include "esp_private/esp_clk.h"
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@ -316,6 +320,7 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
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#if CONFIG_SPIRAM_USE_MALLOC
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p_i2c->intr_alloc_flags = intr_alloc_flags;
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#endif
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#if SOC_I2C_SUPPORT_SLAVE
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if (mode == I2C_MODE_SLAVE) {
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@ -409,6 +414,11 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
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i2c_ll_slave_enable_rx_it(i2c_context[i2c_num].hal.dev);
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}
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#endif // SOC_I2C_SUPPORT_SLAVE
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
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ret = sleep_retention_entries_create(i2c_regs_retention[i2c_num].link_list, i2c_regs_retention[i2c_num].link_num, REGDMA_LINK_PRI_7, I2C_SLEEP_RETENTION_MODULE(i2c_num));
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ESP_GOTO_ON_ERROR(ret, err, I2C_TAG, "failed to allocate mem for sleep retention");
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#endif
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return ESP_OK;
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err:
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@ -461,6 +471,10 @@ esp_err_t i2c_driver_delete(i2c_port_t i2c_num)
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esp_intr_free(p_i2c->intr_handle);
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p_i2c->intr_handle = NULL;
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
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sleep_retention_entries_destroy(I2C_SLEEP_RETENTION_MODULE(i2c_num));
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#endif
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if (p_i2c->cmd_mux) {
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// Let any command in progress finish.
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xSemaphoreTake(p_i2c->cmd_mux, portMAX_DELAY);
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -26,6 +26,9 @@
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#include "soc/i2c_periph.h"
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#include "esp_clk_tree.h"
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#include "clk_ctrl_os.h"
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
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#include "esp_private/sleep_retention.h"
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#endif
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static const char *TAG = "i2c.common";
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@ -55,6 +58,11 @@ static esp_err_t s_i2c_bus_handle_aquire(i2c_port_num_t port_num, i2c_bus_handle
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bus->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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bus->bus_mode = mode;
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
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ret = sleep_retention_entries_create(i2c_regs_retention[port_num].link_list, i2c_regs_retention[port_num].link_num, REGDMA_LINK_PRI_7, I2C_SLEEP_RETENTION_MODULE(port_num));
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ESP_RETURN_ON_ERROR(ret, TAG, "failed to allocate mem for sleep retention");
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#endif
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// Enable the I2C module
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I2C_RCC_ATOMIC() {
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i2c_ll_enable_bus_clock(bus->port_num, true);
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@ -128,6 +136,9 @@ esp_err_t i2c_release_bus_handle(i2c_bus_handle_t i2c_bus)
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if (s_i2c_platform.count[port_num] == 0) {
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do_deinitialize = true;
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s_i2c_platform.buses[port_num] = NULL;
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#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
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sleep_retention_entries_destroy(I2C_SLEEP_RETENTION_MODULE(port_num));
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#endif
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if (i2c_bus->intr_handle) {
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ESP_RETURN_ON_ERROR(esp_intr_free(i2c_bus->intr_handle), TAG, "delete interrupt service failed");
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}
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@ -189,7 +189,7 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
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ESP_RETURN_ON_FALSE(slave_config->i2c_port < SOC_I2C_NUM || slave_config->i2c_port == -1, ESP_ERR_INVALID_ARG, TAG, "invalid i2c port number");
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ESP_RETURN_ON_FALSE((slave_config->send_buf_depth > 0), ESP_ERR_INVALID_ARG, TAG, "invalid SCL speed");
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#if SOC_I2C_SLAVE_SUPPORT_BROADCAST
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ESP_GOTO_ON_FALSE(((slave_config->addr_bit_len != I2C_ADDR_BIT_LEN_10) || (!slave_config->flags.broadcast_en)), ESP_ERR_INVALID_STATE, err, TAG, "10bits address cannot used together with broadcast");
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ESP_RETURN_ON_FALSE(((slave_config->addr_bit_len != I2C_ADDR_BIT_LEN_10) || (!slave_config->flags.broadcast_en)), ESP_ERR_INVALID_STATE, TAG, "10bits address cannot used together with broadcast");
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#endif
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int i2c_port_num = slave_config->i2c_port;
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@ -76,6 +76,9 @@ typedef enum {
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#define I2C_LL_SLAVE_TX_EVENT_INTR (I2C_TXFIFO_WM_INT_ENA_M)
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#define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT (9)
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// I2C sleep retention module
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#define I2C_SLEEP_RETENTION_MODULE(i2c_num) (SLEEP_RETENTION_MODULE_I2C0)
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/**
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* @brief Calculate I2C bus frequency
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* Note that the clock accuracy is affected by the external pull-up resistor,
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@ -75,6 +75,9 @@ typedef enum {
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#define I2C_LL_SLAVE_TX_EVENT_INTR (I2C_TXFIFO_WM_INT_ENA_M)
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#define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT (9)
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// I2C sleep retention module
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#define I2C_SLEEP_RETENTION_MODULE(i2c_num) ((i2c_num == 0) ? SLEEP_RETENTION_MODULE_I2C0 : SLEEP_RETENTION_MODULE_I2C1)
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/**
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* @brief Calculate I2C bus frequency
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* Note that the clock accuracy is affected by the external pull-up resistor,
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@ -335,10 +335,6 @@ config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_PM_SUPPORT_TOP_PD
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bool
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default y
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config SOC_PM_SUPPORT_HP_AON_PD
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bool
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default y
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@ -508,7 +508,7 @@
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#define SOC_PM_SUPPORT_RC32K_PD (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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#define SOC_PM_SUPPORT_TOP_PD (1)
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// #define SOC_PM_SUPPORT_TOP_PD (1) // TODO: IDF-8643
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#define SOC_PM_SUPPORT_HP_AON_PD (1)
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// #define SOC_PM_SUPPORT_MAC_BB_PD (1)
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#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
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@ -1,11 +1,13 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/i2c_periph.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/regdma.h"
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#include "soc/i2c_reg.h"
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/*
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Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
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@ -20,3 +22,32 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
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.module = PERIPH_I2C0_MODULE,
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},
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};
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// I2C sleep retention entries
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// I2C registers require set the reg_update bit to make the configuration take effect
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/* I2C Registers Context
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Include: I2C_SCL_LOW_PERIOD_REG /
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I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
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I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
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I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
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*/
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#define I2C0_RETENTION_REGS_CNT 18
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#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
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static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
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static const regdma_entries_config_t i2c0_regs_retention[] = {
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[0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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};
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const i2c_reg_ctx_link_t i2c_regs_retention[SOC_I2C_NUM] = {
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{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention)},
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};
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@ -38,6 +38,7 @@ typedef enum periph_retention_module_bitmap {
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SLEEP_RETENTION_MODULE_GDMA_CH0 = BIT(24),
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SLEEP_RETENTION_MODULE_GDMA_CH1 = BIT(25),
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SLEEP_RETENTION_MODULE_GDMA_CH2 = BIT(26),
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SLEEP_RETENTION_MODULE_I2C0 = BIT(27),
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SLEEP_RETENTION_MODULE_ALL = (uint32_t)-1
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} periph_retention_module_bitmap_t;
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@ -1,11 +1,13 @@
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/i2c_periph.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/regdma.h"
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#include "soc/i2c_reg.h"
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/*
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Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
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@ -28,3 +30,49 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
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.module = PERIPH_I2C1_MODULE,
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},
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};
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// I2C sleep retention entries
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// I2C registers require set the reg_update bit to make the configuration take effect
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/* I2C Registers Context
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Include: I2C_SCL_LOW_PERIOD_REG /
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I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
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I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
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I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
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*/
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#define I2C0_RETENTION_REGS_CNT 18
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#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
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static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
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static const regdma_entries_config_t i2c0_regs_retention[] = {
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[0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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};
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#define I2C1_RETENTION_REGS_CNT 18
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#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1)
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static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
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static const regdma_entries_config_t i2c1_regs_retention[] = {
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[0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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};
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const i2c_reg_ctx_link_t i2c_regs_retention[SOC_I2C_NUM] = {
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{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention)},
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{i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention)},
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};
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@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -15,7 +15,7 @@ extern "C" {
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* Configures the low level width of the SCL
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* Clock
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*/
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#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
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#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
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/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
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* This register is used to configure for how long SCL remains low in master mode, in
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* I2C module clock cycles.
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@ -28,7 +28,7 @@ extern "C" {
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/** I2C_CTR_REG register
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* Transmission setting
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*/
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#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
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#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4)
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/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
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* 1: direct output, 0: open drain output.
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*/
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@ -148,7 +148,7 @@ extern "C" {
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/** I2C_SR_REG register
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* Describe I2C work status.
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*/
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#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
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#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8)
|
||||
/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
|
||||
* The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
|
||||
*/
|
||||
@ -229,7 +229,7 @@ extern "C" {
|
||||
/** I2C_TO_REG register
|
||||
* Setting time out control for receiving data.
|
||||
*/
|
||||
#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
|
||||
#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc)
|
||||
/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
|
||||
* This register is used to configure the timeout for receiving a data bit in APB
|
||||
* clock cycles.
|
||||
@ -249,7 +249,7 @@ extern "C" {
|
||||
/** I2C_SLAVE_ADDR_REG register
|
||||
* Local slave address setting
|
||||
*/
|
||||
#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
|
||||
#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10)
|
||||
/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
|
||||
* When configured as an I2C Slave, this field is used to configure the slave address.
|
||||
*/
|
||||
@ -268,7 +268,7 @@ extern "C" {
|
||||
/** I2C_FIFO_ST_REG register
|
||||
* FIFO status register.
|
||||
*/
|
||||
#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
|
||||
#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
|
||||
/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
|
||||
* This is the offset address of the APB reading from rxfifo
|
||||
*/
|
||||
@ -308,7 +308,7 @@ extern "C" {
|
||||
/** I2C_FIFO_CONF_REG register
|
||||
* FIFO configuration register.
|
||||
*/
|
||||
#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
|
||||
#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18)
|
||||
/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
|
||||
* The water mark threshold of rx FIFO in nonfifo access mode. When
|
||||
* reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
|
||||
@ -368,7 +368,7 @@ extern "C" {
|
||||
/** I2C_DATA_REG register
|
||||
* Rx FIFO read data.
|
||||
*/
|
||||
#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
|
||||
#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c)
|
||||
/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
|
||||
* The value of rx FIFO read data.
|
||||
*/
|
||||
@ -380,7 +380,7 @@ extern "C" {
|
||||
/** I2C_INT_RAW_REG register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
|
||||
#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
|
||||
/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
@ -518,7 +518,7 @@ extern "C" {
|
||||
/** I2C_INT_CLR_REG register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
|
||||
#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24)
|
||||
/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
@ -656,7 +656,7 @@ extern "C" {
|
||||
/** I2C_INT_ENA_REG register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
|
||||
#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28)
|
||||
/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
@ -794,7 +794,7 @@ extern "C" {
|
||||
/** I2C_INT_STATUS_REG register
|
||||
* Status of captured I2C communication events
|
||||
*/
|
||||
#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
|
||||
#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c)
|
||||
/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
@ -932,7 +932,7 @@ extern "C" {
|
||||
/** I2C_SDA_HOLD_REG register
|
||||
* Configures the hold time after a negative SCL edge.
|
||||
*/
|
||||
#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
|
||||
#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
|
||||
/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
|
||||
* This register is used to configure the time to hold the data after the negative
|
||||
* edge of SCL, in I2C module clock cycles.
|
||||
@ -945,7 +945,7 @@ extern "C" {
|
||||
/** I2C_SDA_SAMPLE_REG register
|
||||
* Configures the sample time after a positive SCL edge.
|
||||
*/
|
||||
#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
|
||||
#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34)
|
||||
/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
|
||||
* This register is used to configure for how long SDA is sampled, in I2C module clock
|
||||
* cycles.
|
||||
@ -958,7 +958,7 @@ extern "C" {
|
||||
/** I2C_SCL_HIGH_PERIOD_REG register
|
||||
* Configures the high level width of SCL
|
||||
*/
|
||||
#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
|
||||
#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38)
|
||||
/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
|
||||
* This register is used to configure for how long SCL remains high in master mode, in
|
||||
* I2C module clock cycles.
|
||||
@ -979,7 +979,7 @@ extern "C" {
|
||||
/** I2C_SCL_START_HOLD_REG register
|
||||
* Configures the delay between the SDA and SCL negative edge for a start condition
|
||||
*/
|
||||
#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
|
||||
#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
|
||||
/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
|
||||
* This register is used to configure the time between the negative edge
|
||||
* of SDA and the negative edge of SCL for a START condition, in I2C module clock
|
||||
@ -994,7 +994,7 @@ extern "C" {
|
||||
* Configures the delay between the positive
|
||||
* edge of SCL and the negative edge of SDA
|
||||
*/
|
||||
#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
|
||||
#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44)
|
||||
/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
|
||||
* This register is used to configure the time between the positive
|
||||
* edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
|
||||
@ -1009,7 +1009,7 @@ extern "C" {
|
||||
* Configures the delay after the SCL clock
|
||||
* edge for a stop condition
|
||||
*/
|
||||
#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
|
||||
#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48)
|
||||
/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
|
||||
* This register is used to configure the delay after the STOP condition,
|
||||
* in I2C module clock cycles.
|
||||
@ -1023,7 +1023,7 @@ extern "C" {
|
||||
* Configures the delay between the SDA and
|
||||
* SCL positive edge for a stop condition
|
||||
*/
|
||||
#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
|
||||
#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c)
|
||||
/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
|
||||
* This register is used to configure the time between the positive edge
|
||||
* of SCL and the positive edge of SDA, in I2C module clock cycles.
|
||||
@ -1036,7 +1036,7 @@ extern "C" {
|
||||
/** I2C_FILTER_CFG_REG register
|
||||
* SCL and SDA filter configuration register
|
||||
*/
|
||||
#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
|
||||
#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50)
|
||||
/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
|
||||
* When a pulse on the SCL input has smaller width than this register value
|
||||
* in I2C module clock cycles, the I2C controller will ignore that pulse.
|
||||
@ -1071,7 +1071,7 @@ extern "C" {
|
||||
/** I2C_CLK_CONF_REG register
|
||||
* I2C CLK configuration register
|
||||
*/
|
||||
#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54)
|
||||
#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54)
|
||||
/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
|
||||
* the integral part of the fractional divisor for i2c module
|
||||
*/
|
||||
@ -1111,7 +1111,7 @@ extern "C" {
|
||||
/** I2C_COMD0_REG register
|
||||
* I2C command register 0
|
||||
*/
|
||||
#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
|
||||
#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58)
|
||||
/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 0. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
||||
@ -1136,7 +1136,7 @@ extern "C" {
|
||||
/** I2C_COMD1_REG register
|
||||
* I2C command register 1
|
||||
*/
|
||||
#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
|
||||
#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c)
|
||||
/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 1. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
||||
@ -1161,7 +1161,7 @@ extern "C" {
|
||||
/** I2C_COMD2_REG register
|
||||
* I2C command register 2
|
||||
*/
|
||||
#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
|
||||
#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60)
|
||||
/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 2. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
||||
@ -1186,7 +1186,7 @@ extern "C" {
|
||||
/** I2C_COMD3_REG register
|
||||
* I2C command register 3
|
||||
*/
|
||||
#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
|
||||
#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
|
||||
/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 3. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
||||
@ -1211,7 +1211,7 @@ extern "C" {
|
||||
/** I2C_COMD4_REG register
|
||||
* I2C command register 4
|
||||
*/
|
||||
#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
|
||||
#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68)
|
||||
/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 4. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
||||
@ -1236,7 +1236,7 @@ extern "C" {
|
||||
/** I2C_COMD5_REG register
|
||||
* I2C command register 5
|
||||
*/
|
||||
#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
|
||||
#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c)
|
||||
/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 5. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
||||
@ -1260,7 +1260,7 @@ extern "C" {
|
||||
/** I2C_COMD6_REG register
|
||||
* I2C command register 6
|
||||
*/
|
||||
#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
|
||||
#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70)
|
||||
/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 6. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
||||
@ -1284,7 +1284,7 @@ extern "C" {
|
||||
/** I2C_COMD7_REG register
|
||||
* I2C command register 7
|
||||
*/
|
||||
#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
|
||||
#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
|
||||
/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 7. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
||||
@ -1308,7 +1308,7 @@ extern "C" {
|
||||
/** I2C_SCL_ST_TIME_OUT_REG register
|
||||
* SCL status time out register
|
||||
*/
|
||||
#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
|
||||
#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78)
|
||||
/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
|
||||
* The threshold value of SCL_FSM state unchanged period. It should be o more than 23
|
||||
*/
|
||||
@ -1320,7 +1320,7 @@ extern "C" {
|
||||
/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
|
||||
* SCL main status time out register
|
||||
*/
|
||||
#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
|
||||
#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c)
|
||||
/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
|
||||
* The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
|
||||
* than 23
|
||||
@ -1333,7 +1333,7 @@ extern "C" {
|
||||
/** I2C_SCL_SP_CONF_REG register
|
||||
* Power configuration register
|
||||
*/
|
||||
#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
|
||||
#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
|
||||
/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
|
||||
* When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
|
||||
* equals to reg_scl_rst_slv_num[4:0].
|
||||
@ -1370,7 +1370,7 @@ extern "C" {
|
||||
/** I2C_SCL_STRETCH_CONF_REG register
|
||||
* Set SCL stretch of I2C slave
|
||||
*/
|
||||
#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
|
||||
#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
|
||||
/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
|
||||
* Configure the period of I2C slave stretching SCL line.
|
||||
*/
|
||||
@ -1412,7 +1412,7 @@ extern "C" {
|
||||
/** I2C_DATE_REG register
|
||||
* Version register
|
||||
*/
|
||||
#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
|
||||
#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8)
|
||||
/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050;
|
||||
* This is the the version register.
|
||||
*/
|
||||
@ -1424,7 +1424,7 @@ extern "C" {
|
||||
/** I2C_TXFIFO_START_ADDR_REG register
|
||||
* I2C TXFIFO base address register
|
||||
*/
|
||||
#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
|
||||
#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100)
|
||||
/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
|
||||
* This is the I2C txfifo first address.
|
||||
*/
|
||||
@ -1436,7 +1436,7 @@ extern "C" {
|
||||
/** I2C_RXFIFO_START_ADDR_REG register
|
||||
* I2C RXFIFO base address register
|
||||
*/
|
||||
#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
|
||||
#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180)
|
||||
/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
|
||||
* This is the I2C rxfifo first address.
|
||||
*/
|
||||
|
||||
@ -36,6 +36,8 @@ typedef enum periph_retention_module_bitmap {
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0 = BIT(24),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1 = BIT(25),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2 = BIT(26),
|
||||
SLEEP_RETENTION_MODULE_I2C0 = BIT(27),
|
||||
SLEEP_RETENTION_MODULE_I2C1 = BIT(28),
|
||||
SLEEP_RETENTION_MODULE_ALL = (uint32_t)-1
|
||||
} periph_retention_module_bitmap_t;
|
||||
|
||||
|
||||
@ -1,22 +1,17 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc/i2c_reg.h"
|
||||
#include "soc/i2c_struct.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#if SOC_PM_SUPPORT_TOP_PD
|
||||
#include "soc/regdma.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -33,6 +28,15 @@ typedef struct {
|
||||
|
||||
extern const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM];
|
||||
|
||||
#if SOC_PM_SUPPORT_TOP_PD
|
||||
typedef struct {
|
||||
const regdma_entries_config_t *link_list;
|
||||
uint32_t link_num;
|
||||
} i2c_reg_ctx_link_t;
|
||||
|
||||
extern const i2c_reg_ctx_link_t i2c_regs_retention[SOC_I2C_NUM];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -44,6 +44,7 @@ extern "C" {
|
||||
#define REGDMA_MODEM_BT_BB_LINK(_pri) ((0x16 << 8) | _pri)
|
||||
#define REGDMA_MODEM_IEEE802154_LINK(_pri) ((0x17 << 8) | _pri)
|
||||
#define REGDMA_GDMA_LINK(_pri) ((0x18 << 8) | _pri)
|
||||
#define REGDMA_I2C_LINK(_pri) ((0x19 << 8) | _pri)
|
||||
#define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri)
|
||||
|
||||
#define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_0
|
||||
|
||||
@ -154,7 +154,6 @@ Light-sleep Peripheral Power Down
|
||||
- Trace
|
||||
- Crypto: AES/ECC/HMAC/RSA/SHA/DS/XTA_AES/ECDSA
|
||||
- SPI2
|
||||
- I2C
|
||||
- I2S
|
||||
- PCNT
|
||||
- USB-Serial-JTAG
|
||||
|
||||
@ -154,7 +154,6 @@ Light-sleep 外设下电
|
||||
- Trace
|
||||
- Crypto: AES/ECC/HMAC/RSA/SHA/DS/XTA_AES/ECDSA
|
||||
- SPI2
|
||||
- I2C
|
||||
- I2S
|
||||
- PCNT
|
||||
- USB-Serial-JTAG
|
||||
|
||||
@ -755,7 +755,6 @@ components/soc/esp32s3/uart_periph.c
|
||||
components/soc/include/soc/dedic_gpio_periph.h
|
||||
components/soc/include/soc/emac_periph.h
|
||||
components/soc/include/soc/gpio_periph.h
|
||||
components/soc/include/soc/i2c_periph.h
|
||||
components/soc/include/soc/ledc_periph.h
|
||||
components/soc/lldesc.c
|
||||
components/spi_flash/include/spi_flash_chip_boya.h
|
||||
|
||||
Loading…
Reference in New Issue
Block a user