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feat(gptimer): basic driver support on esp32c5
This commit is contained in:
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commit
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@ -74,4 +74,16 @@ menu "Driver Configurations"
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you can enable this option.
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endmenu # Legacy MCPWM Driver Configurations
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menu "Legacy Timer Group Driver Configurations"
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depends on SOC_GPTIMER_SUPPORTED
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config GPTIMER_SUPPRESS_DEPRECATE_WARN
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bool "Suppress legacy driver deprecated warning"
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default n
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help
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Wether to suppress the deprecation warnings when using legacy timer group driver (driver/timer.h).
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If you want to continue using the legacy driver, and don't want to see related deprecation warnings,
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you can enable this option.
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endmenu # Legacy Timer Group Driver Configurations
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endmenu # Driver configurations
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@ -22,14 +22,6 @@ menu "ESP-Driver:GPTimer Configurations"
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Ensure the GPTimer interrupt is IRAM-Safe by allowing the interrupt handler to be
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executable when the cache is disabled (e.g. SPI Flash write).
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config GPTIMER_SUPPRESS_DEPRECATE_WARN
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bool "Suppress legacy driver deprecated warning"
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default n
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help
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Wether to suppress the deprecation warnings when using legacy timer group driver (driver/timer.h).
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If you want to continue using the legacy driver, and don't want to see related deprecation warnings,
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you can enable this option.
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config GPTIMER_ENABLE_DEBUG_LOG
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bool "Enable debug log"
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default n
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@ -1,10 +1,11 @@
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/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
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// This Low Level driver only serve the General Purpose Timer function.
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#pragma once
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@ -1,10 +1,11 @@
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/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
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// This Low Level driver only serve the General Purpose Timer function.
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#pragma once
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@ -1,10 +1,11 @@
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/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
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// This Low Level driver only serve the General Purpose Timer function.
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#pragma once
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@ -1,10 +1,11 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
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// This Low Level driver only serve the General Purpose Timer function.
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#pragma once
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@ -25,8 +26,6 @@ extern "C" {
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#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
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#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
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// TODO: [ESP32C5] IDF-8693
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/**
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* @brief Enable the bus clock for timer group module
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*
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@ -35,12 +34,11 @@ extern "C" {
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*/
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static inline void timer_ll_enable_bus_clock(int group_id, bool enable)
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{
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// TODO: [ESP32C5] IDF-8705
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// if (group_id == 0) {
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// PCR.timergroup0_conf.tg0_clk_en = enable;
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// } else {
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// PCR.timergroup1_conf.tg1_clk_en = enable;
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// }
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if (group_id == 0) {
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PCR.timergroup0_conf.tg0_clk_en = enable;
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} else {
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PCR.timergroup1_conf.tg1_clk_en = enable;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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@ -58,22 +56,301 @@ static inline void timer_ll_enable_bus_clock(int group_id, bool enable)
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*/
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static inline void timer_ll_reset_register(int group_id)
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{
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// TODO: [ESP32C5] IDF-8705
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// if (group_id == 0) {
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// PCR.timergroup0_conf.tg0_rst_en = 1;
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// PCR.timergroup0_conf.tg0_rst_en = 0;
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// TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0;
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// } else {
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// PCR.timergroup1_conf.tg1_rst_en = 1;
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// PCR.timergroup1_conf.tg1_rst_en = 0;
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// TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0;
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// }
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if (group_id == 0) {
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PCR.timergroup0_conf.tg0_rst_en = 1;
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PCR.timergroup0_conf.tg0_rst_en = 0;
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TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0;
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} else {
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PCR.timergroup1_conf.tg1_rst_en = 1;
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PCR.timergroup1_conf.tg1_rst_en = 0;
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TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
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#define timer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; timer_ll_reset_register(__VA_ARGS__)
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/**
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* @brief Set clock source for timer
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param clk_src Clock source
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*/
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static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src)
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{
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(void)timer_num; // only one timer in each group
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uint8_t clk_id = 0;
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switch (clk_src) {
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case GPTIMER_CLK_SRC_XTAL:
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clk_id = 0;
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break;
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case GPTIMER_CLK_SRC_RC_FAST:
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clk_id = 1;
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break;
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case GPTIMER_CLK_SRC_PLL_F80M:
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clk_id = 2;
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break;
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default:
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HAL_ASSERT(false);
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break;
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}
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if (hw == &TIMERG0) {
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PCR.timergroup0_timer_clk_conf.tg0_timer_clk_sel = clk_id;
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} else {
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PCR.timergroup1_timer_clk_conf.tg1_timer_clk_sel = clk_id;
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}
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}
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/**
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* @brief Enable Timer Group (GPTimer) module clock
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer index in the group
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* @param en true to enable, false to disable
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*/
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static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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(void)timer_num; // only one timer in each group
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if (hw == &TIMERG0) {
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PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = en;
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} else {
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PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = en;
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}
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}
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/**
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* @brief Enable alarm event
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable alarm
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* False: disable alarm
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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hw->hw_timer[timer_num].config.tx_alarm_en = en;
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}
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/**
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* @brief Set clock prescale for timer
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param divider Prescale value (0 and 1 are not valid)
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*/
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static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
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{
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HAL_ASSERT(divider >= 2 && divider <= 65536);
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if (divider >= 65536) {
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divider = 0;
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
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hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
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}
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/**
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* @brief Enable auto-reload mode
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable auto reload mode
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* False: disable auto reload mode
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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hw->hw_timer[timer_num].config.tx_autoreload = en;
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}
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/**
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* @brief Set count direction
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*
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* @param hw Timer peripheral register base address
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* @param timer_num Timer number in the group
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* @param direction Count direction
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*/
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static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
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{
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hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP);
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}
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/**
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* @brief Enable timer, start couting
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable the counter
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* False: disable the counter
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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hw->hw_timer[timer_num].config.tx_en = en;
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}
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/**
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* @brief Trigger software capture event
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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*/
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__attribute__((always_inline))
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static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num)
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{
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hw->hw_timer[timer_num].update.tx_update = 1;
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// Timer register is in a different clock domain from Timer hardware logic
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// We need to wait for the update to take effect before fetching the count value
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while (hw->hw_timer[timer_num].update.tx_update) {
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}
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}
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/**
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* @brief Get counter value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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*
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* @return counter value
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*/
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__attribute__((always_inline))
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static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num)
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{
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return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
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}
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/**
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* @brief Set alarm value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param alarm_value When counter reaches alarm value, alarm event will be triggered
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*/
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__attribute__((always_inline))
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static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
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{
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hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32);
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hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value;
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}
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/**
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* @brief Set reload value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param reload_val Reload counter value
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*/
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__attribute__((always_inline))
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static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val)
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{
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hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32);
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hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val;
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}
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/**
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* @brief Get reload value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @return reload count value
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*/
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__attribute__((always_inline))
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static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
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{
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return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo);
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}
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/**
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* @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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*/
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__attribute__((always_inline))
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static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num)
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{
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hw->hw_timer[timer_num].load.tx_load = 1;
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}
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/**
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* @brief Enable ETM module
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*
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* @param hw Timer Group register base address
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* @param en True: enable ETM module, False: disable ETM module
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*/
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static inline void timer_ll_enable_etm(timg_dev_t *hw, bool en)
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{
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hw->regclk.etm_en = en;
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}
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/**
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* @brief Enable timer interrupt by mask
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*
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* @param hw Timer Group register base address
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* @param mask Mask of interrupt events
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* @param en True: enable interrupt
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* False: disable interrupt
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en)
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{
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if (en) {
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hw->int_ena_timers.val |= mask;
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} else {
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hw->int_ena_timers.val &= ~mask;
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}
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}
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/**
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* @brief Get interrupt status
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*
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* @param hw Timer Group register base address
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*
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* @return Interrupt status
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*/
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__attribute__((always_inline))
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static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw)
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{
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return hw->int_st_timers.val & 0x01;
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}
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/**
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* @brief Clear interrupt status by mask
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*
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* @param hw Timer Group register base address
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* @param mask Interrupt events mask
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*/
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__attribute__((always_inline))
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static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask)
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{
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hw->int_clr_timers.val = mask;
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}
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/**
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* @brief Enable the register clock forever
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*
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* @param hw Timer Group register base address
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* @param en True: Enable the register clock forever
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* False: Register clock is enabled only when register operation happens
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*/
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static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en)
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{
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hw->regclk.clk_en = en;
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}
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/**
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* @brief Get interrupt status register address
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*
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* @param hw Timer Group register base address
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*
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* @return Interrupt status register address
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*/
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static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
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{
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return &hw->int_st_timers;
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}
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#ifdef __cplusplus
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}
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@ -1,10 +1,11 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
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// This Low Level driver only serve the General Purpose Timer function.
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#pragma once
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|
@ -1,10 +1,11 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
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// This Low Level driver only serve the General Purpose Timer function.
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#pragma once
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||||
|
@ -1,10 +1,11 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// Note that most of the register operations in this layer are non-atomic operations.
|
||||
// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
|
||||
// This Low Level driver only serve the General Purpose Timer function.
|
||||
|
||||
#pragma once
|
||||
|
||||
|
@ -1,10 +1,11 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// Note that most of the register operations in this layer are non-atomic operations.
|
||||
// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
|
||||
// This Low Level driver only serve the General Purpose Timer function.
|
||||
|
||||
#pragma once
|
||||
|
||||
|
@ -1,10 +1,11 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// Note that most of the register operations in this layer are non-atomic operations.
|
||||
// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration.
|
||||
// This Low Level driver only serve the General Purpose Timer function.
|
||||
|
||||
#pragma once
|
||||
|
||||
|
@ -7,6 +7,10 @@ config SOC_UART_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPTIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_KEY_PURPOSE_FIELD
|
||||
bool
|
||||
default y
|
||||
@ -215,6 +219,18 @@ config SOC_TIMER_GROUP_TIMERS_PER_GROUP
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
|
||||
int
|
||||
default 54
|
||||
|
||||
config SOC_TIMER_GROUP_SUPPORT_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_GROUP_TOTAL_TIMERS
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
|
||||
int
|
||||
default 3
|
||||
|
@ -167,12 +167,12 @@ typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6)
|
||||
* }
|
||||
* @endcode
|
||||
*/
|
||||
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
|
||||
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M/*, SOC_MOD_CLK_RC_FAST*/, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of GPTimer clock source
|
||||
*/
|
||||
typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6)
|
||||
typedef enum {
|
||||
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
|
||||
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
@ -182,7 +182,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6)
|
||||
/**
|
||||
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
|
||||
*/
|
||||
typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6)
|
||||
typedef enum {
|
||||
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
|
||||
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
|
||||
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
|
||||
|
@ -22,7 +22,7 @@
|
||||
#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722
|
||||
// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710
|
||||
// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710
|
||||
// #define SOC_GPTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8705
|
||||
#define SOC_GPTIMER_SUPPORTED 1
|
||||
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683
|
||||
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709
|
||||
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691
|
||||
@ -426,10 +426,10 @@
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_GROUPS (2)
|
||||
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
|
||||
// #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
|
||||
// #define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
||||
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
||||
// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
|
||||
// #define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
|
||||
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
|
||||
// #define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
|
||||
@ -516,7 +516,6 @@
|
||||
/* macro redefine for pass esp_wifi headers md5sum check */
|
||||
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
|
||||
|
||||
|
||||
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
|
||||
|
||||
// #define SOC_PM_CPU_RETENTION_BY_SW (1)
|
||||
|
24
components/soc/esp32c5/timer_periph.c
Normal file
24
components/soc/esp32c5/timer_periph.c
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/timer_periph.h"
|
||||
|
||||
const timer_group_signal_conn_t timer_group_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module = PERIPH_TIMG0_MODULE,
|
||||
.timer_irq_id = {
|
||||
[0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.module = PERIPH_TIMG1_MODULE,
|
||||
.timer_irq_id = {
|
||||
[0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
Loading…
Reference in New Issue
Block a user