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Code Issues Actions 2 Packages Projects Releases Wiki Activity

feat(esp32c5): support esptool on esp32c5 beta3

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This commit is contained in:
laokaiyao 2024-01-02 22:19:49 +08:00
parent 3d459e423a
commit d0a8f3e5c4
41 changed files with 98 additions and 171 deletions
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1
.gitlab/ci/dependencies/dependencies.yml
View File

@ -5,6 +5,7 @@
- esp32c3
- esp32c2
- esp32c6
- esp32c5
- esp32h2
- esp32p4

1
.gitlab/ci/pre_check.yml
View File

@ -71,6 +71,7 @@ check_public_headers:
- IDF_TARGET=esp32c3 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
- IDF_TARGET=esp32c2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
- IDF_TARGET=esp32c6 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
- IDF_TARGET=esp32c5 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
- IDF_TARGET=esp32h2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
- IDF_TARGET=esp32p4 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-

15
.gitlab/ci/rules.yml
View File

@ -474,6 +474,9 @@
.if-label-component_ut_esp32c3: &if-label-component_ut_esp32c3
if: '$BOT_LABEL_COMPONENT_UT_ESP32C3 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32c3(?:,[^,\n\r]+)*$/i'
.if-label-component_ut_esp32c5: &if-label-component_ut_esp32c5
if: '$BOT_LABEL_COMPONENT_UT_ESP32C5 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32c5(?:,[^,\n\r]+)*$/i'
.if-label-component_ut_esp32c6: &if-label-component_ut_esp32c6
if: '$BOT_LABEL_COMPONENT_UT_ESP32C6 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32c6(?:,[^,\n\r]+)*$/i'
@ -501,6 +504,9 @@
.if-label-custom_test_esp32c3: &if-label-custom_test_esp32c3
if: '$BOT_LABEL_CUSTOM_TEST_ESP32C3 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32c3(?:,[^,\n\r]+)*$/i'
.if-label-custom_test_esp32c5: &if-label-custom_test_esp32c5
if: '$BOT_LABEL_CUSTOM_TEST_ESP32C5 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32c5(?:,[^,\n\r]+)*$/i'
.if-label-custom_test_esp32c6: &if-label-custom_test_esp32c6
if: '$BOT_LABEL_CUSTOM_TEST_ESP32C6 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32c6(?:,[^,\n\r]+)*$/i'
@ -531,6 +537,9 @@
.if-label-example_test_esp32c3: &if-label-example_test_esp32c3
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32C3 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32c3(?:,[^,\n\r]+)*$/i'
.if-label-example_test_esp32c5: &if-label-example_test_esp32c5
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32C5 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32c5(?:,[^,\n\r]+)*$/i'
.if-label-example_test_esp32c6: &if-label-example_test_esp32c6
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32C6 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32c6(?:,[^,\n\r]+)*$/i'
@ -605,6 +614,7 @@
- <<: *if-label-component_ut_esp32
- <<: *if-label-component_ut_esp32c2
- <<: *if-label-component_ut_esp32c3
- <<: *if-label-component_ut_esp32c5
- <<: *if-label-component_ut_esp32c6
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-component_ut_esp32p4
@ -954,6 +964,7 @@
- <<: *if-label-custom_test_esp32
- <<: *if-label-custom_test_esp32c2
- <<: *if-label-custom_test_esp32c3
- <<: *if-label-custom_test_esp32c5
- <<: *if-label-custom_test_esp32c6
- <<: *if-label-custom_test_esp32h2
- <<: *if-label-custom_test_esp32p4
@ -1212,6 +1223,7 @@
- <<: *if-label-example_test_esp32
- <<: *if-label-example_test_esp32c2
- <<: *if-label-example_test_esp32c3
- <<: *if-label-example_test_esp32c5
- <<: *if-label-example_test_esp32c6
- <<: *if-label-example_test_esp32h2
- <<: *if-label-example_test_esp32p4
@ -1597,6 +1609,7 @@
- <<: *if-label-component_ut_esp32
- <<: *if-label-component_ut_esp32c2
- <<: *if-label-component_ut_esp32c3
- <<: *if-label-component_ut_esp32c5
- <<: *if-label-component_ut_esp32c6
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-component_ut_esp32p4
@ -1606,6 +1619,7 @@
- <<: *if-label-custom_test_esp32
- <<: *if-label-custom_test_esp32c2
- <<: *if-label-custom_test_esp32c3
- <<: *if-label-custom_test_esp32c5
- <<: *if-label-custom_test_esp32c6
- <<: *if-label-custom_test_esp32h2
- <<: *if-label-custom_test_esp32p4
@ -1615,6 +1629,7 @@
- <<: *if-label-example_test_esp32
- <<: *if-label-example_test_esp32c2
- <<: *if-label-example_test_esp32c3
- <<: *if-label-example_test_esp32c5
- <<: *if-label-example_test_esp32c6
- <<: *if-label-example_test_esp32h2
- <<: *if-label-example_test_esp32p4

2
Kconfig
View File

@ -124,7 +124,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
depends on IDF_TARGET_ESP32C5
default IDF_TARGET_ESP32C5_BETA3_VERSION
help
ESP32-C5 will support two versions in a period.
ESP32-C5 will support two versions for a period.
This option is for internal use only.
Select the one that matches your chip model.

31
components/bootloader/subproject/main/ld/esp32c5/bootloader.ld
View File

@ -1,26 +1,27 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-5 ROM static data usage is as follows:
* - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
* TODO: [ESP32C5] IDF-8653 Check this file whether need update
* ESP32-C5 ROM static data usage is as follows:
* - 0x4086b2b8 - 0x4087cbc0: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4087cbc0 - 0x4087ebc0: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4087ebc0 - 0x40880000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x4087c610).
* buffers area (0x4087cbc0).
*/
/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
/* We consider 0x4087cbc0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x4087c610;
bootloader_usable_dram_end = 0x4087cbc0;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0x5000;
bootloader_iram_loader_seg_len = 0x7000;
@ -45,7 +46,7 @@ MEMORY
* 2. Update the value in this assert.
* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x4086E610, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
ASSERT(bootloader_iram_loader_seg_start == 0x4086EBC0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(call_start_cpu0);
@ -222,32 +223,32 @@ SECTIONS
/**
* Appendix: Memory Usage of ROM bootloader
*
* 0x4086ad08 ------------------> _dram0_0_start
* 0x4086b2b8 ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x4087c610 ------------------> __stack_sentry
* 0x4087cbc0 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x4087e610 ------------------> __stack (pro cpu)
* 0x4087ebc0 ------------------> __stack (pro cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x4087f564 ------------------> _dram0_rtos_reserved_start
* 0x4087fb14 ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x4087fab0 ------------------> _dram0_rtos_reserved_end
* 0x4087fefc ------------------> _dram0_rtos_reserved_end
* | |
* 0x4087fce8 ------------------> _data_start_interface
* 0x4087ffb8 ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |

2
components/bootloader/subproject/main/ld/esp32c5/bootloader.rom.ld
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/bootloader_support/include/esp_app_format.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

6
components/bootloader_support/src/bootloader_clock_init.c
View File

@ -54,7 +54,8 @@ __attribute__((weak)) void bootloader_clock_configure(void)
clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
#if CONFIG_IDF_TARGET_ESP32C5
// RC150K can't do calibrate on esp32c5MPW so not use it
// TODO: [ESP32C5] IDF-9009 Check whether SOC_RTC_SLOW_CLK_SRC_RC_SLOW can be used on C5 MP
// RC150K can't do calibrate on ESP32C5MPW so not use it
clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
#else
// Use RTC_SLOW clock source sel register field's default value, RC_SLOW, for 2nd stage bootloader
@ -82,7 +83,8 @@ __attribute__((weak)) void bootloader_clock_configure(void)
#if CONFIG_IDF_TARGET_ESP32C5
/* TODO: [ESP32C5] IDF-8649 temporary use xtal clock source,
need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI */
need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI，
and we need to check flash freq before restart as well */
clk_ll_mspi_fast_set_divider(1);
clk_ll_mspi_fast_sel_clk(MSPI_CLK_SRC_XTAL);
#endif

2
components/bootloader_support/src/bootloader_random_esp32c5.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

8
components/bootloader_support/src/bootloader_utility.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -33,13 +33,7 @@
#include "esp32c6/rom/crc.h"
#include "esp32c6/rom/rtc.h"
#include "esp32c6/rom/uart.h"
#include "esp32c6/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C5
#include "esp32c5/rom/efuse.h"
#include "esp32c5/rom/crc.h"
#include "esp32c5/rom/rtc.h"
#include "esp32c5/rom/uart.h"
#include "esp32c5/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/efuse.h"
#include "esp32h2/rom/crc.h"

41
components/bootloader_support/src/esp32c5/bootloader_ecdsa.c
View File

@ -1,41 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "rom/ecdsa.h"
// TODO: [ESP32C5] IDF-8618 remove esp_log.h
#include "esp_log.h"
#define ROM_FUNC_TYPECAST int(*)(const uint8_t*, const uint8_t*, int, const uint8_t*, uint8_t*)
extern uint32_t _rom_eco_version;
int (*_rom_ets_ecdsa_verify)(const uint8_t*, const uint8_t*, int, const uint8_t*, uint8_t*);
/* On ESP32-C5, the ROM interface hasn't exposed ets_ecdsa_verify symbol, so for that we have defined
* the function here and then jump to the absolute address in ROM.
*
* There is a possibility of updating the ROM in the future chip revisions without any major upgrades,
* in that case, the same binary should work as is on the new chip revision. For that, we check the _rom_eco_version
* and if its a newer one, we jump to the new ROM interface. These addresses won't change in the future
*
* ets_ecdsa_verify symbol will be present in the upcoming ROM ECO versions so even though we have defined it here,
* linker will pick the symbol address from rom.ld file
*/
int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *image_digest, uint8_t *verified_digest)
{
// if (_rom_eco_version == 0) {
// _rom_ets_ecdsa_verify = (ROM_FUNC_TYPECAST)0x4001a824;
// return _rom_ets_ecdsa_verify(key, sig, curve_id, image_digest, verified_digest);
// } else {
// _rom_ets_ecdsa_verify = (ROM_FUNC_TYPECAST)0x40001490;
// return _rom_ets_ecdsa_verify(key, sig, curve_id, image_digest, verified_digest);
// }
// TODO: [ESP32C5] IDF-8618
ESP_EARLY_LOGW("bootloader_ecdsa", "ets_ecdsa_verify() has not been implemented on C5 yet");
return 0;
}

6
components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -32,8 +32,6 @@
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "esp_private/regi2c_ctrl.h"
// #include "soc/regi2c_lp_bias.h"
// #include "soc/regi2c_bias.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
@ -95,8 +93,10 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
// TODO: [ESP32C5] IDF-8650
//Enable super WDT reset.
// bootloader_ana_super_wdt_reset_config(true);
// TODO: [ESP32C5] IDF-8647
//Enable BOD reset
// bootloader_ana_bod_reset_config(true);
}

2
components/bootloader_support/src/esp32c5/bootloader_sha.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/bootloader_support/src/esp32c5/bootloader_soc.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/bootloader_support/src/esp32c5/secure_boot_secure_features.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

6
components/bootloader_support/test_apps/.build-test-rules.yml
View File

@ -2,10 +2,6 @@
components/bootloader_support/test_apps/rtc_custom_section:
enable:
# TODO: [ESP32C5] IDF-8653
- if: SOC_RTC_MEM_SUPPORTED == 1 and IDF_TARGET != "esp32c5"
reason: this feature is supported on chips that have RTC memory
disable:
# TODO: [ESP32C5] IDF-8653
- if: IDF_TARGET == "esp32c5"
temporary: true
reason: not supported yet

2
components/efuse/esp32c5/esp_efuse_rtc_calib.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/efuse/esp32c5/esp_efuse_table.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/efuse/esp32c5/esp_efuse_utility.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/efuse/esp32c5/include/esp_efuse_chip.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/efuse/esp32c5/include/esp_efuse_rtc_calib.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/efuse/esp32c5/include/esp_efuse_table.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/efuse/esp32c5/private_include/esp_efuse_utility.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/esp_adc/esp32c5/include/adc_cali_schemes.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

37
components/esp_hw_support/port/esp32c5/ocode_init.c
View File

@ -1,37 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "soc/soc.h"
#include "soc/rtc.h"
#include "hal/efuse_hal.h"
#include "hal/efuse_ll.h"
#include "regi2c_ctrl.h"
#include "esp_hw_log.h"
static const char *TAG = "ocode_init";
static void set_ocode_by_efuse(int ocode_scheme_ver)
{
// TODO: [ESP32C5] IDF-8702
}
static void calibrate_ocode(void)
{
// TODO: [ESP32C5] IDF-8702
}
void esp_ocode_calib_init(void)
{
// TODO: [ESP32C5] IDF-8702
ESP_HW_LOGW(TAG, "esp_ocode_calib_init() has not implemented yet");
if (efuse_hal_blk_version() >= 1) {
set_ocode_by_efuse(1);
} else {
calibrate_ocode();
}
}

2
components/esp_hw_support/port/esp32c5/private_include/ocode_init.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

4
components/esp_rom/esp32c5/Kconfig.soc_caps.in
View File

@ -67,10 +67,6 @@ config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
bool
default y
config ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE
bool
default y
config ESP_ROM_WDT_INIT_PATCH
bool
default y

1
components/esp_rom/esp32c5/esp_rom_caps.h
View File

@ -22,6 +22,5 @@
#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver
#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs
#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
#define ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE (1) // ECO 0 does not have ets_ecdsa_verify symbol, future revision will have it
#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock
#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init

2
components/esp_system/Kconfig
View File

@ -308,6 +308,7 @@ menu "ESP System Settings"
default 1 if IDF_TARGET_ESP32
default 20 if IDF_TARGET_ESP32C2
default 21 if IDF_TARGET_ESP32C3
default 10 if IDF_TARGET_ESP32C5
default 16 if IDF_TARGET_ESP32C6
default 37 if IDF_TARGET_ESP32P4
default 24 if IDF_TARGET_ESP32H2
@ -326,6 +327,7 @@ menu "ESP System Settings"
default 3 if IDF_TARGET_ESP32
default 19 if IDF_TARGET_ESP32C2
default 20 if IDF_TARGET_ESP32C3
default 11 if IDF_TARGET_ESP32C5
default 17 if IDF_TARGET_ESP32C6
default 38 if IDF_TARGET_ESP32P4
default 23 if IDF_TARGET_ESP32H2

14
components/esp_system/ld/esp32c5/memory.ld.in
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,7 +23,7 @@
#define SRAM_DRAM_START 0x40800000
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END 0x4086E610 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_DRAM_END 0x4086EBC0 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_IRAM_ORG (SRAM_IRAM_START)
#define SRAM_DRAM_ORG (SRAM_DRAM_START)
@ -31,10 +31,10 @@
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/*
* IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB
/**
* TODO: IDF-7890
*/
#define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8)
#define IDROM_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8)
#endif
#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
@ -52,7 +52,7 @@ MEMORY
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped instruction data */
irom_seg (RX) : org = 0x41000020, len = IDRAM0_2_SEG_SIZE - 0x20
irom_seg (RX) : org = 0x41000020, len = IDROM_SEG_SIZE - 0x20
/**
* (0x20 offset above is a convenience for the app binary image generation.
@ -71,7 +71,7 @@ MEMORY
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */
drom_seg (R) : org = 0x41000020, len = IDRAM0_2_SEG_SIZE - 0x20
drom_seg (R) : org = 0x41000020, len = IDROM_SEG_SIZE - 0x20
/* (See irom_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

2
components/esp_system/ld/esp32c5/sections.ld.in
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/hal/esp32c5/include/hal/lpwdt_ll.h
View File

@ -22,7 +22,7 @@ extern "C" {
#include "esp_attr.h"
#include "esp_assert.h"
#include "esp32c6/rom/ets_sys.h"
#include "esp32c5/rom/ets_sys.h"
/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
#define LP_WDT_WKEY_VALUE 0x50D83AA1

2
components/heap/port/esp32c5/memory_layout.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

1
components/soc/esp32c5/include/modem/modem_lpcon_struct.h
View File

@ -10,6 +10,7 @@
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {

16
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@ -39,10 +39,6 @@ config SOC_SPI_FLASH_SUPPORTED
bool
default y
config SOC_SPI_FLASH_SUPPORTED
bool
default y
config SOC_INT_HW_NESTED_SUPPORTED
bool
default y
@ -147,18 +143,6 @@ config SOC_MMU_PERIPH_NUM
int
default 1
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_RTCIO_PIN_COUNT
bool
default n
config SOC_MMU_PERIPH_NUM
int
default 1
config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
int
default 1

14
components/soc/esp32c5/include/soc/uart_channel.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,10 +11,10 @@
// TODO: [ESP32C5] IDF-8722
//UART channels
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 11
#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
#define UART_RXD_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL

2
components/spi_flash/spi_flash_os_func_noos.c
View File

@ -56,6 +56,7 @@ static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
static IRAM_ATTR esp_err_t start(void *arg)
{
// TODO: [ESP32C5] IDF-8646
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Disable(0);
Cache_Read_Disable(1);
@ -75,6 +76,7 @@ static IRAM_ATTR esp_err_t start(void *arg)
static IRAM_ATTR esp_err_t end(void *arg)
{
// TODO: [ESP32C5] IDF-8646
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);
Cache_Read_Enable(1);

4
components/wifi_provisioning/CMakeLists.txt
View File

@ -4,10 +4,6 @@ if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
if(${target} STREQUAL "esp32c5")
return() # not support yet
endif()
set(srcs "src/wifi_config.c"
"src/wifi_scan.c"
"src/wifi_ctrl.c"

15
examples/common_components/env_caps/esp32c5/Kconfig.env_caps Normal file
View File

@ -0,0 +1,15 @@
config ENV_GPIO_RANGE_MIN
int
default 0
config ENV_GPIO_RANGE_MAX
int
default 30
config ENV_GPIO_IN_RANGE_MAX
int
default ENV_GPIO_RANGE_MAX
config ENV_GPIO_OUT_RANGE_MAX
int
default ENV_GPIO_RANGE_MAX

4
examples/get-started/.build-test-rules.yml
View File

@ -2,9 +2,9 @@
examples/get-started/blink:
disable:
- if: IDF_TARGET == "esp32p4"
- if: IDF_TARGET in ["esp32p4", "esp32c5"]
temporary: true
reason: target esp32p4 is not supported yet # TODO: IDF-8074
reason: target esp32p4 and esp32c5 are not supported yet # TODO: IDF-8074, [ESP32C5] IDF-9006
examples/get-started/hello_world:
enable: