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feat(gpio): add gpio support on ESP32C5

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This commit is contained in:
gaoxu 2024-02-20 14:57:25 +08:00
parent ce4b49ae37
commit 3ac736bc95
27 changed files with 696 additions and 3323 deletions
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8
components/esp_driver_gpio/src/gpio.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -337,7 +337,6 @@ esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
{
uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask);
uint32_t io_reg = 0;
uint32_t io_num = 0;
uint8_t input_en = 0;
uint8_t output_en = 0;
@ -358,10 +357,7 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
}
do {
io_reg = GPIO_PIN_MUX_REG[io_num];
if (((gpio_pin_mask >> io_num) & BIT(0))) {
assert(io_reg != (intptr_t)NULL);
#if SOC_RTCIO_PIN_COUNT > 0
if (rtc_gpio_is_valid_gpio(io_num)) {
@ -427,7 +423,7 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
#endif //SOC_GPIO_SUPPORT_PIN_HYS_FILTER
/* By default, all the pins have to be configured as GPIO pins. */
gpio_hal_iomux_func_sel(io_reg, PIN_FUNC_GPIO);
gpio_hal_func_sel(gpio_context.gpio_hal, io_num, PIN_FUNC_GPIO);
}
io_num++;

8
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -506,7 +506,7 @@ static void gpio_interconnect_input_output_pin(uint32_t input_pin, uint32_t outp
{
// signal256 -> output pin -> signal_idx -> input_pin
// Set output pin IE to be able to connect to the signal
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[output_pin]);
gpio_ll_input_enable(&GPIO, output_pin);
esp_rom_gpio_connect_in_signal(output_pin, signal_idx, 0);
// Input pin OE to be able to connect to the signal is done by the esp_rom_gpio_connect_out_signal function
esp_rom_gpio_connect_out_signal(input_pin, signal_idx, 0, 0);
@ -860,7 +860,9 @@ TEST_CASE("GPIO_USB_DP_pin_pullup_disable_test", "[gpio]")
}
#endif //SOC_USB_SERIAL_JTAG_SUPPORTED
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO: IDF-7528 Remove when light sleep is supported on ESP32P4
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4, ESP32C5)
// TODO: IDF-7528 Remove when light sleep is supported on ESP32P4
// TODO: IDF-8638 Remove when light sleep is supported on ESP32C5
// Ignored in CI because it needs manually connect TEST_GPIO_INPUT_LEVEL_LOW_PIN to 3.3v to wake up from light sleep
TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
{

2
components/hal/esp32/include/hal/gpio_ll.h
View File

@ -526,7 +526,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**

2
components/hal/esp32/include/hal/rtc_io_ll.h
View File

@ -280,7 +280,7 @@ static inline void rtcio_ll_force_unhold_all(void)
*/
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
RTCIO.pin[rtcio_num].wakeup_enable = 0x1;
RTCIO.pin[rtcio_num].wakeup_enable = 1;
RTCIO.pin[rtcio_num].int_type = type;
}

2
components/hal/esp32c2/include/hal/gpio_ll.h
View File

@ -346,7 +346,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**

2
components/hal/esp32c3/include/hal/gpio_ll.h
View File

@ -358,7 +358,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**

171
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -22,11 +22,11 @@
#include "soc/lp_aon_struct.h"
#include "soc/lp_io_struct.h"
#include "soc/pmu_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/usb_serial_jtag_struct.h"
#include "soc/io_mux_struct.h"
#include "hal/gpio_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#ifdef __cplusplus
@ -58,18 +58,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
{
// TODO: [ESP32C5] IDF-8717
uint32_t bit_mask = 1 << gpio_num;
uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
*pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
*pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
*ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
*oe = (hw->enable.val & bit_mask) >> gpio_num;
*pu = IOMUX.gpio[gpio_num].fun_wpu;
*pd = IOMUX.gpio[gpio_num].fun_wpd;
*ie = IOMUX.gpio[gpio_num].fun_ie;
*oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num;
*od = hw->pin[gpio_num].pad_driver;
*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
*drv = IOMUX.gpio[gpio_num].fun_drv;
*fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
*slp_sel = IOMUX.gpio[gpio_num].slp_sel;
}
/**
@ -80,8 +77,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
IOMUX.gpio[gpio_num].fun_wpu = 1;
}
/**
@ -93,8 +89,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
IOMUX.gpio[gpio_num].fun_wpu = 0;
}
/**
@ -105,8 +100,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
IOMUX.gpio[gpio_num].fun_wpd = 1;
}
/**
@ -118,17 +112,16 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
IOMUX.gpio[gpio_num].fun_wpd = 0;
}
/**
@ -140,7 +133,6 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type)
{
// TODO: [ESP32C5] IDF-8717
hw->pin[gpio_num].int_type = intr_type;
}
@ -154,7 +146,6 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
// TODO: [ESP32C5] IDF-8717
(void)core_id;
*status = hw->pcpu_int.procpu_int;
}
@ -169,7 +160,6 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
// TODO: [ESP32C5] IDF-8717
*status = 0; // Less than 32 GPIOs in ESP32-C5
}
@ -182,7 +172,6 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
__attribute__((always_inline))
static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
{
// TODO: [ESP32C5] IDF-8717
hw->status_w1tc.status_w1tc = mask;
}
@ -195,7 +184,6 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
__attribute__((always_inline))
static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
{
// TODO: [ESP32C5] IDF-8717
// Less than 32 GPIOs on ESP32-C5 Do nothing.
}
@ -209,7 +197,6 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
__attribute__((always_inline))
static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr
}
@ -223,7 +210,6 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
__attribute__((always_inline))
static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
hw->pin[gpio_num].int_ena = 0; //disable GPIO intr
}
@ -236,8 +222,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].fun_ie = 0;
}
/**
@ -248,8 +233,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].fun_ie = 1;
}
/**
@ -260,8 +244,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].filter_en = 1;
}
/**
@ -272,8 +255,35 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].filter_en = 0;
}
/**
* @brief Enable GPIO hysteresis
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
*/
static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// On ESP32C5, there is an efuse bit that controls the hysteresis enable or not for all IOs.
// We are not going to use the hardware control in IDF for C5.
// Therefore, we need to always switch to use software control first.
// i.e. Swt hys_sel to 1, so that hys_en determines whether hysteresis is enabled or not
IOMUX.gpio[gpio_num].hys_sel = 1;
IOMUX.gpio[gpio_num].hys_en = 1;
}
/**
* @brief Disable GPIO hysteresis
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
*/
static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].hys_sel = 1;
IOMUX.gpio[gpio_num].hys_en = 0;
}
/**
@ -285,11 +295,9 @@ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
// Ensure no other output signal is routed via GPIO matrix to this pin
REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
SIG_GPIO_OUT_IDX);
hw->func_out_sel_cfg[gpio_num].out_sel = SIG_GPIO_OUT_IDX;
}
/**
@ -301,7 +309,6 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
}
@ -313,7 +320,6 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
hw->pin[gpio_num].pad_driver = 0;
}
@ -325,7 +331,6 @@ static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
hw->pin[gpio_num].pad_driver = 1;
}
@ -339,7 +344,6 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
{
// TODO: [ESP32C5] IDF-8717
if (level) {
hw->out_w1ts.out_w1ts = (1 << gpio_num);
} else {
@ -362,9 +366,7 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t
__attribute__((always_inline))
static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
return (hw->in.in_data_next >> gpio_num) & 0x1;
return (int)0;
}
/**
@ -375,8 +377,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**
@ -387,7 +388,6 @@ static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
hw->pin[gpio_num].wakeup_enable = 0;
}
@ -400,8 +400,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
// TODO: [ESP32C5] IDF-8717
SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
IOMUX.gpio[gpio_num].fun_drv = strength;
}
/**
@ -413,8 +412,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
{
// TODO: [ESP32C5] IDF-8717
*strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
*strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
}
/**
@ -425,7 +423,6 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
LP_AON.gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num];
}
@ -437,7 +434,6 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num];
}
@ -456,9 +452,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
return !!(LP_AON.gpio_hold0.gpio_hold0 & BIT(gpio_num));
return (bool)0;
}
/**
@ -471,9 +465,8 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
{
// TODO: [ESP32C5] IDF-8717
hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4));
IOMUX.gpio[gpio].fun_ie = 1;
}
/**
@ -484,10 +477,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// TODO: [ESP32C5] IDF-8717
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// Disable USB Serial JTAG if pins 25 or pins 26 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO25_REG || pin_name == IO_MUX_GPIO26_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(pin_name, func);
}
@ -501,7 +493,6 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
*/
static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
// TODO: [ESP32C5] IDF-8717
SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift);
}
@ -515,12 +506,11 @@ static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t
__attribute__((always_inline))
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
// TODO: [ESP32C5] IDF-8717
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
// Disable USB Serial JTAG if pins 25 or pins 26 needs to select an IOMUX function
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
IOMUX.gpio[gpio_num].mcu_sel = func;
}
/**
@ -534,7 +524,6 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
*/
static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
{
// TODO: [ESP32C5] IDF-8717
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_func_sel(hw, gpio_num, func);
@ -547,13 +536,15 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
*/
static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
{
// TODO: [ESP32C5] IDF-8717
switch (src) {
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
break;
case SOC_MOD_CLK_RC_FAST:
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
break;
case SOC_MOD_CLK_PLL_F80M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
break;
default:
// Unsupported IO_MUX clock source
@ -573,11 +564,9 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
*/
static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
{
// TODO: [ESP32C5] IDF-8717
gpio_func_in_sel_cfg_reg_t reg;
reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
return (reg.sig_in_sel ? reg.in_sel : -1);
return (int)0;
}
/**
@ -608,8 +597,7 @@ static inline void gpio_ll_force_unhold_all(void)
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].slp_sel = 1;
}
/**
@ -621,8 +609,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].slp_sel = 0;
}
/**
@ -633,8 +620,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_wpu = 0;
}
/**
@ -645,8 +631,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_wpu = 1;
}
/**
@ -657,8 +642,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_wpd = 1;
}
/**
@ -669,8 +653,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_wpd = 0;
}
/**
@ -681,8 +664,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_ie = 0;
}
/**
@ -693,8 +675,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
*/
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_ie = 1;
}
/**
@ -705,8 +686,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_oe = 0;
}
/**
@ -717,8 +697,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: [ESP32C5] IDF-8717
PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_oe = 1;
}
#ifdef __cplusplus

2
components/hal/esp32c5/include/hal/rtc_io_ll.h
View File

@ -323,7 +323,7 @@ static inline void rtcio_ll_force_unhold_all(void)
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
// TODO: [ESP32C5] IDF-8719
// LP_IO.pin[rtcio_num].wakeup_enable = 0x1;
// LP_IO.pin[rtcio_num].wakeup_enable = 1;
// LP_IO.pin[rtcio_num].int_type = type;
abort();
}

7
components/hal/esp32c6/include/hal/gpio_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -26,7 +26,6 @@
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "hal/gpio_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#ifdef __cplusplus
@ -59,7 +58,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
{
uint32_t bit_mask = 1 << gpio_num;
uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
uint32_t iomux_reg_val = REG_READ(IO_MUX_GPIO0_REG + (gpio_num * 4));
*pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
*pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
*ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
@ -352,7 +351,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**

2
components/hal/esp32c6/include/hal/rtc_io_ll.h
View File

@ -282,7 +282,7 @@ static inline void rtcio_ll_force_unhold_all(void)
*/
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
LP_IO.pin[rtcio_num].wakeup_enable = 0x1;
LP_IO.pin[rtcio_num].wakeup_enable = 1;
LP_IO.pin[rtcio_num].int_type = type;
}

4
components/hal/esp32h2/include/hal/gpio_ll.h
View File

@ -58,7 +58,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
{
uint32_t bit_mask = 1 << gpio_num;
uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
uint32_t iomux_reg_val = REG_READ(IO_MUX_GPIO0_REG + (gpio_num * 4));
*pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
*pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
*ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
@ -395,7 +395,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**

15
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -64,16 +64,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
{
uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32);
uint32_t bit_mask = 1 << bit_shift;
uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
*pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
*pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
*ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
*pu = IOMUX.gpio[gpio_num].fun_wpu;
*pd = IOMUX.gpio[gpio_num].fun_wpd;
*ie = IOMUX.gpio[gpio_num].fun_ie;
*oe = (((gpio_num < 32) ? hw->enable.val : hw->enable1.val) & bit_mask) >> bit_shift;
*od = hw->pin[gpio_num].pad_driver;
*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
*drv = IOMUX.gpio[gpio_num].fun_drv;
*fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
*slp_sel = IOMUX.gpio[gpio_num].slp_sel;
}
/**

2
components/hal/esp32s2/include/hal/gpio_ll.h
View File

@ -369,7 +369,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**

2
components/hal/esp32s2/include/hal/rtc_io_ll.h
View File

@ -282,7 +282,7 @@ static inline void rtcio_ll_force_unhold_all(void)
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
SENS.sar_io_mux_conf.iomux_clk_gate_en = 1;
RTCIO.pin[rtcio_num].wakeup_enable = 0x1;
RTCIO.pin[rtcio_num].wakeup_enable = 1;
RTCIO.pin[rtcio_num].int_type = type;
}

2
components/hal/esp32s3/include/hal/gpio_ll.h
View File

@ -385,7 +385,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**

2
components/hal/esp32s3/include/hal/rtc_io_ll.h
View File

@ -298,7 +298,7 @@ static inline void rtcio_ll_force_unhold_all(void)
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
SENS.sar_peri_clk_gate_conf.iomux_clk_en = 1;
RTCIO.pin[rtcio_num].wakeup_enable = 0x1;
RTCIO.pin[rtcio_num].wakeup_enable = 1;
RTCIO.pin[rtcio_num].int_type = type;
}

39
components/soc/esp32c5/gpio_periph.c
View File

@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_periph.h"
const uint32_t GPIO_HOLD_MASK[] = {
BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
BIT(1), //GPIO1
BIT(2), //GPIO2
BIT(3), //GPIO3
BIT(4), //GPIO4
BIT(5), //GPIO5
BIT(6), //GPIO6
BIT(7), //GPIO7
BIT(8), //GPIO8
BIT(9), //GPIO9
BIT(10), //GPIO10
BIT(11), //GPIO11
BIT(12), //GPIO12
BIT(13), //GPIO13
BIT(14), //GPIO14
BIT(15), //GPIO15
BIT(16), //GPIO16
BIT(17), //GPIO17
BIT(18), //GPIO18
BIT(19), //GPIO19
BIT(20), //GPIO20
BIT(21), //GPIO21
BIT(22), //GPIO22
BIT(23), //GPIO23
BIT(24), //GPIO24
BIT(25), //GPIO25
BIT(26), //GPIO26
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

38
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@ -107,17 +107,49 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
bool
default y
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 31
default 27
config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
config SOC_GPIO_ETM_EVENTS_PER_GROUP
int
default 8
config SOC_GPIO_ETM_TASKS_PER_GROUP
int
default 8
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 30
default 26
config SOC_GPIO_OUT_RANGE_MAX
int
default 30
default 26
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0000000007FFFF00
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool

8
components/soc/esp32c5/include/soc/gpio_num.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,8 +10,6 @@
extern "C" {
#endif
// TODO: [ESP32C5] IDF-8717
/**
* @brief GPIO number
*/
@ -44,10 +42,6 @@ typedef enum {
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
GPIO_NUM_28 = 28, /*!< GPIO28, input and output */
GPIO_NUM_29 = 29, /*!< GPIO29, input and output */
GPIO_NUM_30 = 30, /*!< GPIO30, input and output */
GPIO_NUM_MAX,
} gpio_num_t;

7
components/soc/esp32c5/include/soc/gpio_pins.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,9 +11,8 @@
extern "C" {
#endif
// TODO: [ESP32C5] IDF-8717 (inherit from C6)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x3F)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3E)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}

3267
components/soc/esp32c5/include/soc/io_mux_reg.h
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File diff suppressed because it is too large Load Diff

80
components/soc/esp32c5/include/soc/io_mux_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -34,81 +34,81 @@ typedef union {
uint32_t reserved_15:17;
};
uint32_t val;
} io_mux_pin_ctrl_reg_t;
} iomux_pin_ctrl_reg_t;
/** Type of gpion register
/** Type of gpio register
* IO MUX Configure Register for pad XTAL_32K_P
*/
typedef union {
struct {
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
/** mcu_oe : R/W; bitpos: [0]; default: 0;
* Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled.
*/
uint32_t gpion_mcu_oe:1;
/** gpion_slp_sel : R/W; bitpos: [1]; default: 0;
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
* Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
*/
uint32_t gpion_slp_sel:1;
/** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
uint32_t slp_sel:1;
/** mcu_wpd : R/W; bitpos: [2]; default: 0;
* Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0:
* internal pull-down disabled.
*/
uint32_t gpion_mcu_wpd:1;
/** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
uint32_t mcu_wpd:1;
/** mcu_wpu : R/W; bitpos: [3]; default: 0;
* Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0:
* internal pull-up disabled.
*/
uint32_t gpion_mcu_wpu:1;
/** gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
uint32_t mcu_wpu:1;
/** mcu_ie : R/W; bitpos: [4]; default: 0;
* Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled.
*/
uint32_t gpion_mcu_ie:1;
/** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2:
* ~20mA. 3: ~40mA.
*/
uint32_t gpion_mcu_drv:2;
/** gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
* Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down
* disabled.
*/
uint32_t gpion_fun_wpd:1;
/** gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
uint32_t fun_wpd:1;
/** fun_wpu : R/W; bitpos: [8]; default: 0;
* Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up
* disabled.
*/
uint32_t gpion_fun_wpu:1;
/** gpion_fun_ie : R/W; bitpos: [9]; default: 0;
uint32_t fun_wpu:1;
/** fun_ie : R/W; bitpos: [9]; default: 0;
* Input enable of the pad. 1: input enabled. 0: input disabled.
*/
uint32_t gpion_fun_ie:1;
/** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [11:10]; default: 2;
* Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA.
*/
uint32_t gpion_fun_drv:2;
/** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 0;
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [14:12]; default: 0;
* Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2.
* etc.
*/
uint32_t gpion_mcu_sel:3;
/** gpion_filter_en : R/W; bitpos: [15]; default: 0;
uint32_t mcu_sel:3;
/** filter_en : R/W; bitpos: [15]; default: 0;
* Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled.
*/
uint32_t gpion_filter_en:1;
/** gpion_hys_en : R/W; bitpos: [16]; default: 0;
uint32_t filter_en:1;
/** hys_en : R/W; bitpos: [16]; default: 0;
* Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0:
* Hysteresis disabled.
*/
uint32_t gpion_hys_en:1;
/** gpion_hys_sel : R/W; bitpos: [17]; default: 0;
uint32_t hys_en:1;
/** hys_sel : R/W; bitpos: [17]; default: 0;
* Select enabling signals of the pad from software and efuse hardware. 1: Select
* enabling siganl from slftware. 0: Select enabling signal from efuse hardware.
*/
uint32_t gpion_hys_sel:1;
uint32_t hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} io_mux_gpion_reg_t;
} iomux_gpio_reg_t;
/** Type of date register
* IO MUX Version Control Register
@ -122,20 +122,20 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} io_mux_date_reg_t;
} iomux_date_reg_t;
typedef struct io_mux_dev_t {
volatile io_mux_pin_ctrl_reg_t pin_ctrl;
volatile io_mux_gpion_reg_t gpion[27];
typedef struct iomux_dev_t {
volatile iomux_pin_ctrl_reg_t pin_ctrl;
volatile iomux_gpio_reg_t gpio[27];
uint32_t reserved_070[35];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
volatile iomux_date_reg_t date;
} iomux_dev_t;
extern io_mux_dev_t IO_MUX;
extern iomux_dev_t IOMUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure");
_Static_assert(sizeof(iomux_dev_t) == 0x100, "Invalid size of iomux_dev_t structure");
#endif
#ifdef __cplusplus

26
components/soc/esp32c5/include/soc/soc_caps.h
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@ -173,37 +173,37 @@
// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
/*-------------------------- GPIO CAPS ---------------------------------------*/
// TODO: [ESP32C5] IDF-8717
// ESP32-C5 has 1 GPIO peripheral
// #define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 31
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 27 // TODO: update C5bate3 to C5 MP
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1
// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8
#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
#define SOC_GPIO_ETM_TASKS_PER_GROUP 8
// Target has the full LP IO subsystem
// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // TODO: [ESP32C5] IDF-8719
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 30
#define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_IN_RANGE_MAX 26
#define SOC_GPIO_OUT_RANGE_MAX 26
// #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
// #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_26)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000007FFFF00ULL
// Support to force hold all IOs
// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

2
components/soc/esp32c5/ld/esp32c5.peripherals.ld
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@ -41,7 +41,7 @@ PROVIDE ( DS = 0x6008C000 );
PROVIDE ( HMAC = 0x6008D000 );
PROVIDE ( ECDSA = 0x6008E000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( IOMUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091f00 );
PROVIDE ( SDM = 0x60091f00 );

157
docs/en/api-reference/peripherals/gpio/esp32c5.inc
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@ -9,6 +9,161 @@
.. gpio-summary
To be updated for C5
Current GPIO is for {IDF_TARGET_NAME} beta3 version. {IDF_TARGET_NAME} MP version would have 2 more available IOs, and some pin functions are changed. The {IDF_TARGET_NAME} MP version will be updated later.
The {IDF_TARGET_NAME} chip features 27 physical GPIO pins (GPIO0 ~ GPIO26). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
.. list-table::
:header-rows: 1
:widths: 8 12 12 20
* - GPIO
- Analog Function
- LP GPIO
- Comments
* - GPIO0
- LP_GPIO0
-
-
* - GPIO1
- ADC1_CH0
- LP_GPIO1
-
* - GPIO2
- ADC1_CH1
- LP_GPIO2
- Strapping pin
* - GPIO3
- ADC1_CH2
- LP_GPIO3
- Strapping pin
* - GPIO4
- ADC1_CH3
- LP_GPIO4
-
* - GPIO5
- ADC1_CH4
- LP_GPIO5
-
* - GPIO6
- ADC1_CH5
- LP_GPIO6
- Strapping pin
* - GPIO7
-
- LP_GPIO7
- Strapping pin
* - GPIO8
-
-
-
* - GPIO9
-
-
-
* - GPIO10
-
-
-
* - GPIO11
-
-
-
* - GPIO12
-
-
-
* - GPIO13
-
-
-
* - GPIO14
-
-
-
* - GPIO15
-
-
-
* - GPIO16
-
-
-
* - GPIO17
-
-
-
* - GPIO18
-
-
- SPI0/1
* - GPIO19
-
-
- SPI0/1
* - GPIO20
-
-
- SPI0/1
* - GPIO21
-
-
- SPI0/1
* - GPIO22
-
-
- SPI0/1
* - GPIO23
-
-
- SPI0/1
* - GPIO24
-
-
- SPI0/1
* - GPIO25
-
-
- USB-JTAG
* - GPIO26
-
-
- USB-JTAG
.. note::
- Strapping pin: GPIO2, GPIO3, GPIO6, and GPIO7 are strapping pins. For more infomation, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
- SPI0/1: GPIO18-24 are usually used for SPI flash and not recommended for other uses.
- USB-JTAG: GPIO 25 and 26 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
---

158
docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc
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@ -9,6 +9,162 @@
.. gpio-summary
To be updated for C5
{IDF_TARGET_NAME} 芯片具有 27 个物理 GPIO 管脚（GPIO0 ~ GPIO26）。
当前的GPIO适用于{IDF_TARGET_NAME} beta3版本。{IDF_TARGET_NAME} MP版本将会增加2个可用的IO，并且一些引脚功能将会改变。{IDF_TARGET_NAME} MP版本将会在以后更新。
每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。
.. list-table::
:header-rows: 1
:widths: 8 12 12 20
* - GPIO
- 模拟功能
- LP GPIO
- 注释
* - GPIO0
- LP_GPIO0
-
-
* - GPIO1
- ADC1_CH0
- LP_GPIO1
-
* - GPIO2
- ADC1_CH1
- LP_GPIO2
- Strapping 管脚
* - GPIO3
- ADC1_CH2
- LP_GPIO3
- Strapping 管脚
* - GPIO4
- ADC1_CH3
- LP_GPIO4
-
* - GPIO5
- ADC1_CH4
- LP_GPIO5
-
* - GPIO6
- ADC1_CH5
- LP_GPIO6
- Strapping 管脚
* - GPIO7
-
- LP_GPIO7
- Strapping 管脚
* - GPIO8
-
-
-
* - GPIO9
-
-
-
* - GPIO10
-
-
-
* - GPIO11
-
-
-
* - GPIO12
-
-
-
* - GPIO13
-
-
-
* - GPIO14
-
-
-
* - GPIO15
-
-
-
* - GPIO16
-
-
-
* - GPIO17
-
-
-
* - GPIO18
-
-
- SPI0/1
* - GPIO19
-
-
- SPI0/1
* - GPIO20
-
-
- SPI0/1
* - GPIO21
-
-
- SPI0/1
* - GPIO22
-
-
- SPI0/1
* - GPIO23
-
-
- SPI0/1
* - GPIO24
-
-
- SPI0/1
* - GPIO25
-
-
- USB-JTAG
* - GPIO26
-
-
- USB-JTAG
.. note::
- Strapping 管脚：GPIO2、GPIO3、GPIO6 和 GPIO7 是 Strapping 管脚。更多信息请参考 `ESP32-C5 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
- SPI0/1：GPIO18-24 通常用于 SPI flash，不推荐用于其他用途。
- USB-JTAG：GPIO25 和 GPIO26 默认用于 USB-JTAG。用做 GPIO 时驱动程序将禁用 USB-JTAG。
---

4
examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild
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@ -5,7 +5,7 @@ menu "Example Configuration"
config GPIO_OUTPUT_0
int "GPIO output pin 0"
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2
default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5
default 18
help
GPIO pin number to be used as GPIO_OUTPUT_IO_0.
@ -13,7 +13,7 @@ menu "Example Configuration"
config GPIO_OUTPUT_1
int "GPIO output pin 1"
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2
default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5
default 19
help
GPIO pin number to be used as GPIO_OUTPUT_IO_1.