alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

feat(gdma): add GDMA support for ESP32C5

Browse Source
This commit is contained in:
Song Ruo Jing 2024-02-07 16:56:53 +08:00
parent f3b95059f9
commit 98d9f04b00
18 changed files with 1453 additions and 407 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
components/bootloader_support/src/bootloader_mem.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -16,6 +16,12 @@
#include "hal/apm_hal.h"
#endif
#if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5!
#include "soc/hp_apm_reg.h"
#include "soc/lp_apm_reg.h"
#include "soc/lp_apm0_reg.h"
#endif
void bootloader_init_mem(void)
{
@ -30,6 +36,13 @@ void bootloader_init_mem(void)
apm_hal_apm_ctrl_filter_enable_all(false);
#endif
#if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5!
// disable apm filter
REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);
REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
#endif
#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
// protect memory region
esp_cpu_configure_region_protection();

9
components/esp_hw_support/CMakeLists.txt
View File

@ -70,9 +70,12 @@ if(NOT BOOTLOADER_BUILD)
if(CONFIG_SOC_GDMA_SUPPORTED)
list(APPEND srcs "dma/gdma.c")
if(CONFIG_SOC_PM_SUPPORT_TOP_PD)
if(CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION)
list(APPEND srcs "dma/gdma_sleep_retention.c")
endif()
if(CONFIG_SOC_GDMA_SUPPORT_ETM)
list(APPEND srcs "dma/gdma_etm.c")
endif()
endif()
if(CONFIG_SOC_MULTI_USAGE_LDO_SUPPORTED)
@ -92,10 +95,6 @@ if(NOT BOOTLOADER_BUILD)
endif() # CONFIG_SOC_CP_DMA_SUPPORTED
endif() # CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED
if(CONFIG_SOC_GDMA_SUPPORT_ETM)
list(APPEND srcs "dma/gdma_etm.c")
endif()
if(CONFIG_SOC_DW_GDMA_SUPPORTED)
list(APPEND srcs "dma/dw_gdma.c")
endif()

45
components/hal/esp32c5/include/hal/cache_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -14,6 +14,7 @@
// #include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32c5/rom/cache.h"
#ifdef __cplusplus
extern "C" {
@ -46,13 +47,12 @@ __attribute__((always_inline))
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// bool enabled = false;
// if (REG_GET_BIT(EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG, EXTMEM_L1_CACHE_AUTOLOAD_ENA)) {
// enabled = true;
// }
// return enabled;
return (bool)0;
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
bool enabled = false;
if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) {
enabled = true;
}
return enabled;
}
/**
@ -66,8 +66,8 @@ __attribute__((always_inline))
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// (void) type;
// Cache_Disable_ICache();
(void) type;
Cache_Disable_ICache();
}
/**
@ -83,7 +83,7 @@ __attribute__((always_inline))
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
}
/**
@ -97,7 +97,7 @@ __attribute__((always_inline))
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Suspend_ICache();
Cache_Suspend_ICache();
}
/**
@ -113,7 +113,7 @@ __attribute__((always_inline))
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
}
/**
@ -131,7 +131,7 @@ __attribute__((always_inline))
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Invalidate_Addr(vaddr, size);
Cache_Invalidate_Addr(vaddr, size);
}
/**
@ -145,7 +145,7 @@ __attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
}
/**
@ -159,7 +159,7 @@ __attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Freeze_ICache_Disable();
Cache_Freeze_ICache_Disable();
}
/**
@ -175,10 +175,9 @@ __attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// uint32_t size = 0;
// size = Cache_Get_ICache_Line_Size();
// return size;
return (uint32_t)0;
uint32_t size = 0;
size = Cache_Get_ICache_Line_Size();
return size;
}
/**
@ -243,6 +242,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
abort();
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
// HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@ -268,6 +268,7 @@ __attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
abort();
// bool valid = false;
// uint32_t vaddr_end = vaddr_start + len - 1;
// // valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
@ -292,7 +293,7 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
}
/**
@ -304,7 +305,7 @@ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint3
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
}
/**

627
components/hal/esp32c5/include/hal/gdma_ll.h Normal file
View File

@ -0,0 +1,627 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stddef.h> /* Required for NULL constant */
#include <stdint.h>
#include <stdbool.h>
#include "hal/gdma_types.h"
#include "soc/gdma_struct.h"
#include "soc/gdma_reg.h"
#include "soc/soc_etm_source.h"
#include "soc/pcr_struct.h"
#include "soc/retention_periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 << (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) << pair_id)
#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_RX_EVENT_MASK (0x7F)
#define GDMA_LL_TX_EVENT_MASK (0x3F)
// any "dummy" peripheral ID can be used for M2M mode
#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC32)
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<6)
#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<5)
#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3)
#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
#define GDMA_LL_EVENT_TX_EOF (1<<1)
#define GDMA_LL_EVENT_TX_DONE (1<<0)
#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2)
#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
#define GDMA_LL_EVENT_RX_DONE (1<<0)
#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0
#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups
#define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group
#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \
(uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \
}, \
{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \
}, \
{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH2, \
}}}[group][chan][event]
#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \
(uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \
}, \
{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \
}, \
{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH2, \
}}}[group][chan][event]
#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \
(uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \
}, \
{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \
}, \
{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH2, \
}}}[group][chan][task]
#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \
(uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \
}, \
{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \
}, \
{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH2, \
}}}[group][chan][task]
// TODO: Workaround for C5-beta3 only. C5-mp can still vectorized channels into an array in gdma_struct.h
#define GDMA_LL_CHANNEL_GET_REG_ADDR(dev, ch) ((volatile gdma_chn_reg_t*[]){&dev->channel0, &dev->channel1, &dev->channel2}[(ch)])
///////////////////////////////////// Common /////////////////////////////////////////
/**
* @brief Enable the bus clock for the DMA module
*/
static inline void gdma_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.gdma_conf.gdma_clk_en = enable;
}
/**
* @brief Reset the DMA module
*/
static inline void gdma_ll_reset_register(int group_id)
{
(void)group_id;
PCR.gdma_conf.gdma_rst_en = 1;
PCR.gdma_conf.gdma_rst_en = 0;
}
/**
* @brief Force enable register clock
*/
static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
{
dev->misc_conf.clk_en = enable;
}
///////////////////////////////////// RX /////////////////////////////////////////
/**
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
if (raw) {
return dev->in_intr[channel].raw.val;
} else {
return dev->in_intr[channel].st.val;
}
}
/**
* @brief Enable DMA RX channel interrupt
*/
static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->in_intr[channel].ena.val |= mask;
} else {
dev->in_intr[channel].ena.val &= ~mask;
}
}
/**
* @brief Clear DMA RX channel interrupt
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->in_intr[channel].clr.val = mask;
}
/**
* @brief Get DMA RX channel interrupt status register address
*/
static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->in_intr[channel].st);
}
/**
* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
*/
static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf1.in_check_owner = enable;
}
/**
* @brief Enable DMA RX channel burst reading data, disabled by default
*/
static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.in_data_burst_en = enable;
}
/**
* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
*/
static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.indscr_burst_en = enable;
}
/**
* @brief Reset DMA RX channel FSM and FIFO pointer
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.in_rst = 1;
ch->in.in_conf0.in_rst = 0;
}
/**
* @brief Check if DMA RX FIFO is full
* @param fifo_level only supports level 1
*/
static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.infifo_status.val & 0x01;
}
/**
* @brief Check if DMA RX FIFO is empty
* @param fifo_level only supports level 1
*/
static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.infifo_status.val & 0x02;
}
/**
* @brief Get number of bytes in RX FIFO
* @param fifo_level only supports level 1
*/
static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.infifo_status.infifo_cnt;
}
/**
* @brief Pop data from DMA RX FIFO
*/
static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_pop.infifo_pop = 1;
return ch->in.in_pop.infifo_rdata;
}
/**
* @brief Set the descriptor link base address for RX channel
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_addr = addr;
}
/**
* @brief Start dealing with RX descriptors
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_start = 1;
}
/**
* @brief Stop dealing with RX descriptors
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_stop = 1;
}
/**
* @brief Restart a new inlink right after the last descriptor
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_restart = 1;
}
/**
* @brief Enable DMA RX to return the address of current descriptor when receives error
*/
static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_auto_ret = enable;
}
/**
* @brief Check if DMA RX descriptor FSM is in IDLE state
*/
static inline bool gdma_ll_rx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_link.inlink_park;
}
/**
* @brief Get RX success EOF descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_suc_eof_des_addr.val;
}
/**
* @brief Get RX error EOF descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_err_eof_des_addr.val;
}
/**
* @brief Get the pre-fetched RX descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_dscr.val;
}
/**
* @brief Set priority for DMA RX channel
*/
static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_pri.rx_pri = prio;
}
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_peri_sel.peri_in_sel = periph_id;
ch->in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);
}
/**
* @brief Disconnect DMA RX channel from peripheral
*/
static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_peri_sel.peri_in_sel = GDMA_LL_INVALID_PERIPH_ID;
ch->in.in_conf0.mem_trans_en = false;
}
/**
* @brief Whether to enable the ETM subsystem for RX channel
*
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
*/
static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.in_etm_en = enable;
}
///////////////////////////////////// TX /////////////////////////////////////////
/**
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
if (raw) {
return dev->out_intr[channel].raw.val;
} else {
return dev->out_intr[channel].st.val;
}
}
/**
* @brief Enable DMA TX channel interrupt
*/
static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->out_intr[channel].ena.val |= mask;
} else {
dev->out_intr[channel].ena.val &= ~mask;
}
}
/**
* @brief Clear DMA TX channel interrupt
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->out_intr[channel].clr.val = mask;
}
/**
* @brief Get DMA TX channel interrupt status register address
*/
static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->out_intr[channel].st);
}
/**
* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
*/
static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf1.out_check_owner = enable;
}
/**
* @brief Enable DMA TX channel burst sending data, disabled by default
*/
static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_data_burst_en = enable;
}
/**
* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
*/
static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.outdscr_burst_en = enable;
}
/**
* @brief Set TX channel EOF mode
*/
static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_eof_mode = mode;
}
/**
* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
*/
static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_auto_wrback = enable;
}
/**
* @brief Reset DMA TX channel FSM and FIFO pointer
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_rst = 1;
ch->out.out_conf0.out_rst = 0;
}
/**
* @brief Check if DMA TX FIFO is full
* @param fifo_level only supports level 1
*/
static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.outfifo_status.val & 0x01;
}
/**
* @brief Check if DMA TX FIFO is empty
* @param fifo_level only supports level 1
*/
static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.outfifo_status.val & 0x02;
}
/**
* @brief Get number of bytes in TX FIFO
* @param fifo_level only supports level 1
*/
static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.outfifo_status.outfifo_cnt;
}
/**
* @brief Push data into DMA TX FIFO
*/
static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_push.outfifo_wdata = data;
ch->out.out_push.outfifo_push = 1;
}
/**
* @brief Set the descriptor link base address for TX channel
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_link.outlink_addr = addr;
}
/**
* @brief Start dealing with TX descriptors
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_link.outlink_start = 1;
}
/**
* @brief Stop dealing with TX descriptors
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_link.outlink_stop = 1;
}
/**
* @brief Restart a new outlink right after the last descriptor
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_link.outlink_restart = 1;
}
/**
* @brief Check if DMA TX descriptor FSM is in IDLE state
*/
static inline bool gdma_ll_tx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.out_link.outlink_park;
}
/**
* @brief Get TX EOF descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.out_eof_des_addr.val;
}
/**
* @brief Get the pre-fetched TX descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.out_dscr.val;
}
/**
* @brief Set priority for DMA TX channel
*/
static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_pri.tx_pri = prio;
}
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
{
(void)periph;
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_peri_sel.peri_out_sel = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_peri_sel.peri_out_sel = GDMA_LL_INVALID_PERIPH_ID;
}
/**
* @brief Whether to enable the ETM subsystem for TX channel
*
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
*/
static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_etm_en = enable;
}
#ifdef __cplusplus
}
#endif

121
components/soc/esp32c5/gdma_periph.c Normal file
View File

@ -0,0 +1,121 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gdma_periph.h"
#include "soc/gdma_reg.h"
const gdma_signal_conn_t gdma_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_GDMA_MODULE,
.pairs = {
[0] = {
.rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
},
[1] = {
.rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
},
[2] = {
.rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
}
}
}
}
};
#if SOC_GDMA_SUPPORT_SLEEP_RETENTION
/* GDMA Channel (Group0, Pair0) Registers Context
Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
*/
#define G0P0_RETENTION_REGS_CNT_0 13
#define G0P0_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH0_REG
#define G0P0_RETENTION_REGS_CNT_1 2
#define G0P0_RETENTION_MAP_BASE_1 GDMA_BT_TX_SEL_REG
static const uint32_t g0p0_regs_map0[4] = {0x4C801001, 0x604C0060, 0, 0};
static const uint32_t g0p0_regs_map1[4] = {0x3, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
g0p0_regs_map0[0], g0p0_regs_map0[1], \
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
g0p0_regs_map1[0], g0p0_regs_map1[1], \
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
.owner = ENTRY(0) | ENTRY(2) },
};
/* GDMA Channel (Group0, Pair1) Registers Context
Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
*/
#define G0P1_RETENTION_REGS_CNT_0 13
#define G0P1_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH1_REG
#define G0P1_RETENTION_REGS_CNT_1 2
#define G0P1_RETENTION_MAP_BASE_1 GDMA_BT_TX_SEL_REG
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604};
static const uint32_t g0p1_regs_map1[4] = {0x3, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
g0p1_regs_map0[0], g0p1_regs_map0[1], \
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
g0p1_regs_map1[0], g0p1_regs_map1[1], \
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
.owner = ENTRY(0) | ENTRY(2) },
};
/* GDMA Channel (Group0, Pair2) Registers Context
Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
*/
#define G0P2_RETENTION_REGS_CNT_0 6
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
#define G0P2_RETENTION_REGS_CNT_1 9
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
static const uint32_t g0p2_regs_map1[4] = {0xf026003, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
g0p2_regs_map0[0], g0p2_regs_map0[1], \
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
g0p2_regs_map1[0], g0p2_regs_map1[1], \
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
.owner = ENTRY(0) | ENTRY(2) },
};
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_PAIRS_PER_GROUP_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
[0] = {
[0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)},
[1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)},
[2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)}
}
};
#endif

24
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@ -7,10 +7,22 @@ config SOC_UART_SUPPORTED
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
config SOC_AHB_GDMA_SUPPORTED
bool
default y
config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@ -115,6 +127,18 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
bool
default y
config SOC_AHB_GDMA_VERSION
int
default 1
config SOC_GDMA_NUM_GROUPS_MAX
int
default 1
config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 3
config SOC_GPIO_PORT
int
default 1

4
components/soc/esp32c5/include/soc/gdma_channel.h
View File

@ -1,13 +1,11 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// TODO: [ESP32C5] IDF-8710
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)

633
components/soc/esp32c5/include/soc/gdma_struct.h
View File

File diff suppressed because it is too large Load Diff

17
components/soc/esp32c5/include/soc/soc_caps.h
View File

@ -20,15 +20,15 @@
// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725
#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722
// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710
// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: [ESP32C5] IDF-8716
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727
// #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851
@ -56,7 +56,7 @@
#define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8622
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
@ -164,10 +164,11 @@
// #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
// #define SOC_AHB_GDMA_VERSION 1U
// #define SOC_GDMA_NUM_GROUPS_MAX 1U
// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_AHB_GDMA_VERSION 1U
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9224
// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-9225
/*-------------------------- ETM CAPS --------------------------------------*/
// #define SOC_ETM_GROUPS 1U // Number of ETM groups

300
components/soc/esp32c5/include/soc/soc_etm_source.h Normal file
View File

@ -0,0 +1,300 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define GPIO_EVT_CH0_RISE_EDGE 1
#define GPIO_EVT_CH1_RISE_EDGE 2
#define GPIO_EVT_CH2_RISE_EDGE 3
#define GPIO_EVT_CH3_RISE_EDGE 4
#define GPIO_EVT_CH4_RISE_EDGE 5
#define GPIO_EVT_CH5_RISE_EDGE 6
#define GPIO_EVT_CH6_RISE_EDGE 7
#define GPIO_EVT_CH7_RISE_EDGE 8
#define GPIO_EVT_CH0_FALL_EDGE 9
#define GPIO_EVT_CH1_FALL_EDGE 10
#define GPIO_EVT_CH2_FALL_EDGE 11
#define GPIO_EVT_CH3_FALL_EDGE 12
#define GPIO_EVT_CH4_FALL_EDGE 13
#define GPIO_EVT_CH5_FALL_EDGE 14
#define GPIO_EVT_CH6_FALL_EDGE 15
#define GPIO_EVT_CH7_FALL_EDGE 16
#define GPIO_EVT_CH0_ANY_EDGE 17
#define GPIO_EVT_CH1_ANY_EDGE 18
#define GPIO_EVT_CH2_ANY_EDGE 19
#define GPIO_EVT_CH3_ANY_EDGE 20
#define GPIO_EVT_CH4_ANY_EDGE 21
#define GPIO_EVT_CH5_ANY_EDGE 22
#define GPIO_EVT_CH6_ANY_EDGE 23
#define GPIO_EVT_CH7_ANY_EDGE 24
#define GPIO_EVT_ZERO_DET_POS 25
#define GPIO_EVT_ZERO_DET_NEG 26
#define LEDC_EVT_DUTY_CHNG_END_CH0 27
#define LEDC_EVT_DUTY_CHNG_END_CH1 28
#define LEDC_EVT_DUTY_CHNG_END_CH2 29
#define LEDC_EVT_DUTY_CHNG_END_CH3 30
#define LEDC_EVT_DUTY_CHNG_END_CH4 31
#define LEDC_EVT_DUTY_CHNG_END_CH5 32
#define LEDC_EVT_OVF_CNT_PLS_CH0 33
#define LEDC_EVT_OVF_CNT_PLS_CH1 34
#define LEDC_EVT_OVF_CNT_PLS_CH2 35
#define LEDC_EVT_OVF_CNT_PLS_CH3 36
#define LEDC_EVT_OVF_CNT_PLS_CH4 37
#define LEDC_EVT_OVF_CNT_PLS_CH5 38
#define LEDC_EVT_TIME_OVF_TIMER0 39
#define LEDC_EVT_TIME_OVF_TIMER1 40
#define LEDC_EVT_TIME_OVF_TIMER2 41
#define LEDC_EVT_TIME_OVF_TIMER3 42
#define LEDC_EVT_TIMER0_CMP 43
#define LEDC_EVT_TIMER1_CMP 44
#define LEDC_EVT_TIMER2_CMP 45
#define LEDC_EVT_TIMER3_CMP 46
#define TG0_EVT_CNT_CMP_TIMER0 47
#define TG0_EVT_CNT_CMP_TIMER1 48
#define TG1_EVT_CNT_CMP_TIMER0 49
#define TG1_EVT_CNT_CMP_TIMER1 50
#define SYSTIMER_EVT_CNT_CMP0 51
#define SYSTIMER_EVT_CNT_CMP1 52
#define SYSTIMER_EVT_CNT_CMP2 53
#define MCPWM0_EVT_TIMER0_STOP 54
#define MCPWM0_EVT_TIMER1_STOP 55
#define MCPWM0_EVT_TIMER2_STOP 56
#define MCPWM0_EVT_TIMER0_TEZ 57
#define MCPWM0_EVT_TIMER1_TEZ 58
#define MCPWM0_EVT_TIMER2_TEZ 59
#define MCPWM0_EVT_TIMER0_TEP 60
#define MCPWM0_EVT_TIMER1_TEP 61
#define MCPWM0_EVT_TIMER2_TEP 62
#define MCPWM0_EVT_OP0_TEA 63
#define MCPWM0_EVT_OP1_TEA 64
#define MCPWM0_EVT_OP2_TEA 65
#define MCPWM0_EVT_OP0_TEB 66
#define MCPWM0_EVT_OP1_TEB 67
#define MCPWM0_EVT_OP2_TEB 68
#define MCPWM0_EVT_F0 69
#define MCPWM0_EVT_F1 70
#define MCPWM0_EVT_F2 71
#define MCPWM0_EVT_F0_CLR 72
#define MCPWM0_EVT_F1_CLR 73
#define MCPWM0_EVT_F2_CLR 74
#define MCPWM0_EVT_TZ0_CBC 75
#define MCPWM0_EVT_TZ1_CBC 76
#define MCPWM0_EVT_TZ2_CBC 77
#define MCPWM0_EVT_TZ0_OST 78
#define MCPWM0_EVT_TZ1_OST 79
#define MCPWM0_EVT_TZ2_OST 80
#define MCPWM0_EVT_CAP0 81
#define MCPWM0_EVT_CAP1 82
#define MCPWM0_EVT_CAP2 83
#define MCPWM0_EVT_OP0_TEE1 84
#define MCPWM0_EVT_OP1_TEE1 85
#define MCPWM0_EVT_OP2_TEE1 86
#define MCPWM0_EVT_OP0_TEE2 87
#define MCPWM0_EVT_OP1_TEE2 88
#define MCPWM0_EVT_OP2_TEE2 89
#define ADC_EVT_CONV_CMPLT0 90
#define ADC_EVT_EQ_ABOVE_THRESH0 91
#define ADC_EVT_EQ_ABOVE_THRESH1 92
#define ADC_EVT_EQ_BELOW_THRESH0 93
#define ADC_EVT_EQ_BELOW_THRESH1 94
#define ADC_EVT_RESULT_DONE0 95
#define ADC_EVT_STOPPED0 96
#define ADC_EVT_STARTED0 97
#define REGDMA_EVT_DONE0 98
#define REGDMA_EVT_DONE1 99
#define REGDMA_EVT_DONE2 100
#define REGDMA_EVT_DONE3 101
#define REGDMA_EVT_ERR0 102
#define REGDMA_EVT_ERR1 103
#define REGDMA_EVT_ERR2 104
#define REGDMA_EVT_ERR3 105
#define GDMA_EVT_IN_DONE_CH0 106
#define GDMA_EVT_IN_DONE_CH1 107
#define GDMA_EVT_IN_DONE_CH2 108
#define GDMA_EVT_IN_SUC_EOF_CH0 109
#define GDMA_EVT_IN_SUC_EOF_CH1 110
#define GDMA_EVT_IN_SUC_EOF_CH2 111
#define GDMA_EVT_IN_FIFO_EMPTY_CH0 112
#define GDMA_EVT_IN_FIFO_EMPTY_CH1 113
#define GDMA_EVT_IN_FIFO_EMPTY_CH2 114
#define GDMA_EVT_IN_FIFO_FULL_CH0 115
#define GDMA_EVT_IN_FIFO_FULL_CH1 116
#define GDMA_EVT_IN_FIFO_FULL_CH2 117
#define GDMA_EVT_OUT_DONE_CH0 118
#define GDMA_EVT_OUT_DONE_CH1 119
#define GDMA_EVT_OUT_DONE_CH2 120
#define GDMA_EVT_OUT_EOF_CH0 121
#define GDMA_EVT_OUT_EOF_CH1 122
#define GDMA_EVT_OUT_EOF_CH2 123
#define GDMA_EVT_OUT_TOTAL_EOF_CH0 124
#define GDMA_EVT_OUT_TOTAL_EOF_CH1 125
#define GDMA_EVT_OUT_TOTAL_EOF_CH2 126
#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 127
#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 128
#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 129
#define GDMA_EVT_OUT_FIFO_FULL_CH0 130
#define GDMA_EVT_OUT_FIFO_FULL_CH1 131
#define GDMA_EVT_OUT_FIFO_FULL_CH2 132
#define TMPSNSR_EVT_OVER_LIMIT 133
#define I2S0_EVT_RX_DONE 134
#define I2S0_EVT_TX_DONE 135
#define I2S0_EVT_X_WORDS_RECEIVED 136
#define I2S0_EVT_X_WORDS_SENT 137
#define ULP_EVT_ERR_INTR 138
#define ULP_EVT_HALT 139
#define ULP_EVT_START_INTR 140
#define RTC_EVT_TICK 141
#define RTC_EVT_OVF 142
#define RTC_EVT_CMP 143
#define PMU_EVT_SLEEP_WEEKUP 144
#define GPIO_TASK_CH0_SET 1
#define GPIO_TASK_CH1_SET 2
#define GPIO_TASK_CH2_SET 3
#define GPIO_TASK_CH3_SET 4
#define GPIO_TASK_CH4_SET 5
#define GPIO_TASK_CH5_SET 6
#define GPIO_TASK_CH6_SET 7
#define GPIO_TASK_CH7_SET 8
#define GPIO_TASK_CH0_CLEAR 9
#define GPIO_TASK_CH1_CLEAR 10
#define GPIO_TASK_CH2_CLEAR 11
#define GPIO_TASK_CH3_CLEAR 12
#define GPIO_TASK_CH4_CLEAR 13
#define GPIO_TASK_CH5_CLEAR 14
#define GPIO_TASK_CH6_CLEAR 15
#define GPIO_TASK_CH7_CLEAR 16
#define GPIO_TASK_CH0_TOGGLE 17
#define GPIO_TASK_CH1_TOGGLE 18
#define GPIO_TASK_CH2_TOGGLE 19
#define GPIO_TASK_CH3_TOGGLE 20
#define GPIO_TASK_CH4_TOGGLE 21
#define GPIO_TASK_CH5_TOGGLE 22
#define GPIO_TASK_CH6_TOGGLE 23
#define GPIO_TASK_CH7_TOGGLE 24
#define LEDC_TASK_TIMER0_RES_UPDATE 25
#define LEDC_TASK_TIMER1_RES_UPDATE 26
#define LEDC_TASK_TIMER2_RES_UPDATE 27
#define LEDC_TASK_TIMER3_RES_UPDATE 28
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34
#define LEDC_TASK_TIMER0_CAP 35
#define LEDC_TASK_TIMER1_CAP 36
#define LEDC_TASK_TIMER2_CAP 37
#define LEDC_TASK_TIMER3_CAP 38
#define LEDC_TASK_SIG_OUT_DIS_CH0 39
#define LEDC_TASK_SIG_OUT_DIS_CH1 40
#define LEDC_TASK_SIG_OUT_DIS_CH2 41
#define LEDC_TASK_SIG_OUT_DIS_CH3 42
#define LEDC_TASK_SIG_OUT_DIS_CH4 43
#define LEDC_TASK_SIG_OUT_DIS_CH5 44
#define LEDC_TASK_OVF_CNT_RST_CH0 45
#define LEDC_TASK_OVF_CNT_RST_CH1 46
#define LEDC_TASK_OVF_CNT_RST_CH2 47
#define LEDC_TASK_OVF_CNT_RST_CH3 48
#define LEDC_TASK_OVF_CNT_RST_CH4 49
#define LEDC_TASK_OVF_CNT_RST_CH5 50
#define LEDC_TASK_TIMER0_RST 51
#define LEDC_TASK_TIMER1_RST 52
#define LEDC_TASK_TIMER2_RST 53
#define LEDC_TASK_TIMER3_RST 54
#define LEDC_TASK_TIMER0_RESUME 55
#define LEDC_TASK_TIMER1_RESUME 56
#define LEDC_TASK_TIMER2_RESUME 57
#define LEDC_TASK_TIMER3_RESUME 58
#define LEDC_TASK_TIMER0_PAUSE 59
#define LEDC_TASK_TIMER1_PAUSE 60
#define LEDC_TASK_TIMER2_PAUSE 61
#define LEDC_TASK_TIMER3_PAUSE 62
#define LEDC_TASK_GAMMA_RESTART_CH0 63
#define LEDC_TASK_GAMMA_RESTART_CH1 64
#define LEDC_TASK_GAMMA_RESTART_CH2 65
#define LEDC_TASK_GAMMA_RESTART_CH3 66
#define LEDC_TASK_GAMMA_RESTART_CH4 67
#define LEDC_TASK_GAMMA_RESTART_CH5 68
#define LEDC_TASK_GAMMA_PAUSE_CH0 69
#define LEDC_TASK_GAMMA_PAUSE_CH1 70
#define LEDC_TASK_GAMMA_PAUSE_CH2 71
#define LEDC_TASK_GAMMA_PAUSE_CH3 72
#define LEDC_TASK_GAMMA_PAUSE_CH4 73
#define LEDC_TASK_GAMMA_PAUSE_CH5 74
#define LEDC_TASK_GAMMA_RESUME_CH0 75
#define LEDC_TASK_GAMMA_RESUME_CH1 76
#define LEDC_TASK_GAMMA_RESUME_CH2 77
#define LEDC_TASK_GAMMA_RESUME_CH3 78
#define LEDC_TASK_GAMMA_RESUME_CH4 79
#define LEDC_TASK_GAMMA_RESUME_CH5 80
#define TG0_TASK_CNT_START_TIMER0 81
#define TG0_TASK_ALARM_START_TIMER0 82
#define TG0_TASK_CNT_STOP_TIMER0 83
#define TG0_TASK_CNT_RELOAD_TIMER0 84
#define TG0_TASK_CNT_CAP_TIMER0 85
#define TG0_TASK_CNT_START_TIMER1 86
#define TG0_TASK_ALARM_START_TIMER1 87
#define TG0_TASK_CNT_STOP_TIMER1 88
#define TG0_TASK_CNT_RELOAD_TIMER1 89
#define TG0_TASK_CNT_CAP_TIMER1 90
#define TG1_TASK_CNT_START_TIMER0 91
#define TG1_TASK_ALARM_START_TIMER0 92
#define TG1_TASK_CNT_STOP_TIMER0 93
#define TG1_TASK_CNT_RELOAD_TIMER0 94
#define TG1_TASK_CNT_CAP_TIMER0 95
#define TG1_TASK_CNT_START_TIMER1 96
#define TG1_TASK_ALARM_START_TIMER1 97
#define TG1_TASK_CNT_STOP_TIMER1 98
#define TG1_TASK_CNT_RELOAD_TIMER1 99
#define TG1_TASK_CNT_CAP_TIMER1 100
#define MCPWM0_TASK_CMPR0_A_UP 101
#define MCPWM0_TASK_CMPR1_A_UP 102
#define MCPWM0_TASK_CMPR2_A_UP 103
#define MCPWM0_TASK_CMPR0_B_UP 104
#define MCPWM0_TASK_CMPR1_B_UP 105
#define MCPWM0_TASK_CMPR2_B_UP 106
#define MCPWM0_TASK_GEN_STOP 107
#define MCPWM0_TASK_TIMER0_SYN 108
#define MCPWM0_TASK_TIMER1_SYN 109
#define MCPWM0_TASK_TIMER2_SYN 110
#define MCPWM0_TASK_TIMER0_PERIOD_UP 111
#define MCPWM0_TASK_TIMER1_PERIOD_UP 112
#define MCPWM0_TASK_TIMER2_PERIOD_UP 113
#define MCPWM0_TASK_TZ0_OST 114
#define MCPWM0_TASK_TZ1_OST 115
#define MCPWM0_TASK_TZ2_OST 116
#define MCPWM0_TASK_CLR0_OST 117
#define MCPWM0_TASK_CLR1_OST 118
#define MCPWM0_TASK_CLR2_OST 119
#define MCPWM0_TASK_CAP0 120
#define MCPWM0_TASK_CAP1 121
#define MCPWM0_TASK_CAP2 122
#define ADC_TASK_SAMPLE0 123
#define ADC_TASK_SAMPLE1 124
#define ADC_TASK_START0 125
#define ADC_TASK_STOP0 126
#define REGDMA_TASK_START0 127
#define REGDMA_TASK_START1 128
#define REGDMA_TASK_START2 129
#define REGDMA_TASK_START3 130
#define GDMA_TASK_IN_START_CH0 131
#define GDMA_TASK_IN_START_CH1 132
#define GDMA_TASK_IN_START_CH2 133
#define GDMA_TASK_OUT_START_CH0 134
#define GDMA_TASK_OUT_START_CH1 135
#define GDMA_TASK_OUT_START_CH2 136
#define TMPSNSR_TASK_START_SAMPLE 137
#define TMPSNSR_TASK_STOP_SAMPLE 138
#define I2S0_TASK_START_RX 139
#define I2S0_TASK_START_TX 140
#define I2S0_TASK_STOP_RX 141
#define I2S0_TASK_STOP_TX 142
#define ULP_TASK_WAKEUP_CPU 143
#define ULP_TASK_INT_CPU 144
#define RTC_TASK_START 145
#define RTC_TASK_STOP 146
#define RTC_TASK_CLR 147
#define RTC_TASK_TRIGGERFLW 148
#define PMU_TASK_SLEEP_REQ 149

10
components/soc/esp32c6/gdma_periph.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -71,22 +71,22 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
*/
#define G0P1_RETENTION_REGS_CNT_0 6
#define G0P2_RETENTION_REGS_CNT_0 6
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
#define G0P1_RETENTION_REGS_CNT_1 7
#define G0P2_RETENTION_REGS_CNT_1 7
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
g0p2_regs_map0[0], g0p2_regs_map0[1], \
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
g0p2_regs_map1[0], g0p2_regs_map1[1], \
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
.owner = ENTRY(0) | ENTRY(2) },

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -419,6 +419,10 @@ config SOC_GDMA_SUPPORT_ETM
bool
default y
config SOC_GDMA_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_ETM_GROUPS
int
default 1

11
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -162,10 +162,11 @@
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_AHB_GDMA_VERSION 1U
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_AHB_GDMA_VERSION 1U
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS --------------------------------------*/
#define SOC_ETM_GROUPS 1U // Number of ETM groups

10
components/soc/esp32h2/gdma_periph.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -71,22 +71,22 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
*/
#define G0P1_RETENTION_REGS_CNT_0 6
#define G0P2_RETENTION_REGS_CNT_0 6
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
#define G0P1_RETENTION_REGS_CNT_1 7
#define G0P2_RETENTION_REGS_CNT_1 7
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
g0p2_regs_map0[0], g0p2_regs_map0[1], \
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
g0p2_regs_map1[0], g0p2_regs_map1[1], \
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
.owner = ENTRY(0) | ENTRY(2) },

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -423,6 +423,10 @@ config SOC_GDMA_SUPPORT_ETM
bool
default y
config SOC_GDMA_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_ETM_GROUPS
int
default 1

11
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -164,10 +164,11 @@
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_AHB_GDMA_VERSION 1U
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_AHB_GDMA_VERSION 1U
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS --------------------------------------*/
#define SOC_ETM_GROUPS 1U // Number of ETM groups

13
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -176,12 +176,13 @@
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_SUPPORT_CRC 1
#define SOC_GDMA_NUM_GROUPS_MAX 2
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_AXI_GDMA_SUPPORT_PSRAM 1
#define SOC_GDMA_SUPPORT_ETM 1
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_SUPPORT_CRC 1
#define SOC_GDMA_NUM_GROUPS_MAX 2
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_AXI_GDMA_SUPPORT_PSRAM 1
#define SOC_GDMA_SUPPORT_ETM 1
// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- 2D-DMA CAPS -------------------------------------*/
#define SOC_DMA2D_GROUPS (1U) // Number of 2D-DMA groups

2
components/soc/include/soc/gdma_periph.h
View File

@ -30,7 +30,7 @@ typedef struct {
extern const gdma_signal_conn_t gdma_periph_signals;
#if SOC_PM_SUPPORT_TOP_PD
#if SOC_GDMA_SUPPORT_SLEEP_RETENTION
typedef struct {
const regdma_entries_config_t *link_list;
uint32_t link_num;