alex/esp-idf
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1932 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
005e6656be Merge branch 'feature/add_new_pkg_and_flash_psram_efuses_v5.1' into 'release/v5.1' 
feat(efuse): Add flash&psram efuses for S3 (v5.1)

See merge request espressif/esp-idf!29143
 2024-03-05 10:34:18 +08:00
Marius Vikhammer
929a8449bd Merge branch 'feature/usb_host_collective_backport_v5.1' into 'release/v5.1' 
USB Host: Collective backport to v5.1

See merge request espressif/esp-idf!28096
 2024-03-01 09:28:23 +08:00
Darian Leung
d837836f84
refactor(hal/usb): Rename usb_fsls_phy API to match header/source names 
Note: Also fixed some formatting issues in usb_wrap_struct.h
 2024-02-28 16:09:52 +08:00
Darian Leung
b32a735bb0
refactor(soc/host): Update USB OTG struct fields 
This commit updates the "*_struct.h" files for the USB OTG peripheral:

- Added/removed some missing/non-existing register fields
- Added "reserved" place holders for registers that are missing due to IP
configuration.
- Added "usb_dwc_cfg.h" listing the USB OTG IP configuration for each target.
- Updated LL/HAL according to register field updates. Also tidied up the include
directives in those headers.
 2024-02-28 16:09:51 +08:00
Cao Sen Miao
9025e440ae fix(temperature_sensor): Cannot switch the range smmothly on esp32h2 2024-02-28 12:39:07 +08:00
morris
92b25c06b3 Merge branch 'bugfix/fix_incorrect_regbase_name_of_i2s_v5.1' into 'release/v5.1' 
fix(i2s): fixed incorrect reg base name on C3 (v5.1)

See merge request espressif/esp-idf!28630
 2024-02-28 11:41:58 +08:00
Aditya Patwardhan
55c5c8367b Merge branch 'bugfix/soc_cpu_subsys_region_v5.1' into 'release/v5.1' 
fix(soc): change debug addr range to CPU subsystem range (v5.1)

See merge request espressif/esp-idf!28672
 2024-02-28 11:16:48 +08:00
Jiang Jiang Jian
c404e951e3 Merge branch 'docs/rf_coexistence_api_guides_support_esp32c2_v5.1' into 'release/v5.1' 
Docs: RF coexistence api guides support esp32c2 (v5.1)

See merge request espressif/esp-idf!29214
 2024-02-28 11:09:29 +08:00
Jiang Jiang Jian
76152c80a2 Merge branch 'c6_auto_dbias_master_hsq_v5.1' into 'release/v5.1' 
ESP32C6: Active & sleep dbg and dbias get from efuse to fix the voltage (v5.1)

See merge request espressif/esp-idf!28722
 2024-02-28 10:49:13 +08:00
linruihao
89881c7c59 fix(esp_coex): add support_coexistence soc_caps for esp32c2 and esp32h2 2024-02-23 16:26:10 +08:00
hongshuqing
80378b809e feat(pmu): set fix voltage to different mode for esp32c6 2024-02-22 15:01:14 +08:00
Marius Vikhammer
d9a6158700 fix(system): update reset reasons for C6 and H2 2024-02-22 12:36:09 +08:00
KonstantinKondrashov
24f6995fb5 feat(efuse): Add flash&psram efuses for S3 2024-02-21 09:36:49 +02:00
KonstantinKondrashov
cce3c4a1d5 feat(efuse): Adds new efuses for esp32c6 2024-01-26 11:39:16 +08:00
KonstantinKondrashov
f7a920685a feat(efuse): Adds new efuse for esp32h2 2024-01-26 11:39:16 +08:00
Mahavir Jain
614ad494f6
fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
 2024-01-24 12:52:27 +05:30
laokaiyao
d7b6ebe7df fix(i2s): fixed incorrect reg base name on C3 
Closes https://github.com/espressif/esp-idf/issues/12643
 2024-01-23 12:05:45 +08:00
Roshan Bangar
dc9d9b41f2 fix(nimble): Added periodic_adv_enh soc_caps for c2, h2 2023-12-27 15:03:17 +05:30
Xu Si Yu
866bc77246 feat(ieee802154): add tx/rx report for IEEE802.15.4 debug 2023-12-21 15:17:54 +08:00
Jiang Jiang Jian
487adc09f4 Merge branch 'change/change_regdma_power_issue_macro_v5.1' into 'release/v5.1' 
change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG (backport v5.1)

See merge request espressif/esp-idf!27991
 2023-12-21 11:27:10 +08:00
Marius Vikhammer
40bea117e4 Merge branch 'bugfix/s3_irom_addr_v5.1' into 'release/v5.1' 
soc: fix SOC_IROM_MASK_HIGH for esp32s3 (v5.1)

See merge request espressif/esp-idf!27136
 2023-12-20 10:00:39 +08:00
Lou Tianhao
1419db4b91 change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG 2023-12-19 11:44:23 +08:00
Mahavir Jain
fa7383162f Merge branch 'fix/esp32s3_soc_drom_high_addr_v5.1' into 'release/v5.1' 
fix(soc): esp32s3/Fix the DROM_HIGH_ADDR (v5.1)

See merge request espressif/esp-idf!27822
 2023-12-17 16:31:41 +08:00
morris
eb7022dd06 Merge branch 'contrib/github_pr_12559_v5.1' into 'release/v5.1' 
fix(spi): Correct REG_SPI_BASE(i) macro for all targets (GitHub PR) (v5.1)

See merge request espressif/esp-idf!27714
 2023-12-14 11:08:03 +08:00
Aditya Patwardhan
f62e7fd4e8
fix(soc): esp32s3/Fix the DROM_DROM_HIGH limit 
Previously the DROM_HIGH_ADDR for esp32s3 was 0x3D000000, which
    convers only 16 MB of address range. But esp32s3 supports 32 MB
    external memory. So this address should be 0x3E000000
 2023-12-11 12:17:31 +05:30
Mahavir Jain
ca02c6d274 Merge branch 'fix/rng_register_prefix_discrepency_newer_targets_v5.1' into 'release/v5.1' 
Fix: RNG register prefix discrepancy for ESP32C6 and ESP32H2 (v5.1)

See merge request espressif/esp-idf!27684
 2023-12-08 12:01:36 +08:00
harshal.patil
6a990a37ce
fix(soc/esp32h2): Fix llperi_rng_data field discrepancy 2023-12-07 11:42:00 +05:30
gaoxu
6190b3f7c9 fix(adc): restore cali registers after light sleep wake up on H2 and enable test 2023-12-06 10:19:52 +00:00
wanlei
3486cf1b60 fix(spi): correct some signals and dummy bits docs 2023-12-06 16:15:23 +08:00
TD-er
8e0d64e94c fix(spi): Correct REG_SPI_BASE(i) macro for all targets 
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
 2023-12-06 16:13:01 +08:00
harshal.patil
c040a614a9
fix(soc/esp32c6): Fix llperi_rng_data field discrepancy 2023-12-05 21:08:48 +05:30
Darian Leung
411405355d refactor(soc): SOC_USB_PERIPH_NUM option 
This commit refactors SOC_USB_PERIPH_NUM as follows:

- Renamed to SOC_USB_OTG_PERIPH_NUM to avoid confusion with USB Serial JTAG
- Updated to unsigned integer "1U"
- Updated some build rules to depend on SOC_USB_OTG_SUPPORTED instead
 2023-11-28 22:00:30 +01:00
Shu Chen
ecbbd3c3d9 Merge branch 'backport/add_ot_radio_stats_enable_config_5_1' into 'release/v5.1' 
feat(openthread): backport some openthread features(BackportV5.1)

See merge request espressif/esp-idf!26885
 2023-11-22 12:23:53 +08:00
Aditya Patwardhan
514cd783a3 Merge branch 'bugfix/esp32h2_ecdsa_hardware_k_v5.1' into 'release/v5.1' 
fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose (v5.1)

See merge request espressif/esp-idf!27271
 2023-11-21 13:57:38 +08:00
Jiang Jiang Jian
0e1ec38785 Merge branch 'bugfix/fix_lightsleep_current_leakage_on_usj_pad_v5.1' into 'release/v5.1' 
fix(esp_hw_support): fix lightsleep current leakage on usb pad (backport v5.1)

See merge request espressif/esp-idf!27205
 2023-11-21 10:51:11 +08:00
Mahavir Jain
0ccfa4b0c2
fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose 
In ESP32-H2, the ECDSA peripheral by default uses the TRNG (hardware)
generated k value but it can be overridden to software supplied k.
This can happen through by overriding the `ECDSA_SOFTWARE_SET_K` bit
in the configuration register. Even though the HAL API is not exposed
for this but still it could be achieved by direct register
programming. And for this scenario, if sufficiently random k is not
supplied by the software then it could posses a security risk.

In this change, we are unconditionally programming the efuse
`ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K` bit during startup security
checks itself. Additionally, same is ensured in the `esp_efuse_write_key`
API as well. This always enforces the hardware k mode in the ECDSA
peripheral and ensures strongest possible security.
 2023-11-20 16:03:29 +05:30
Jiang Jiang Jian
5719d882d1 Merge branch 'bugfix/fix_onebyte_watchpoint_setting_v5.1' into 'release/v5.1' 
fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting (v5.1)

See merge request espressif/esp-idf!27215
 2023-11-20 17:37:03 +08:00
morris
1b3713f7cd Merge branch 'feature/support_adc_calibration_on_h2_v5.1' into 'release/v5.1' 
adc_cali: supported adc calibration v1 on ESP32H2 (v5.1)

See merge request espressif/esp-idf!26963
 2023-11-17 16:41:00 +08:00
morris
ddb6d22468 Merge branch 'feature/gpio_dump_io_info_v5.1' into 'release/v5.1' 
feat(gpio): add a dump API to dump IO configurations (v5.1)

See merge request espressif/esp-idf!26870
 2023-11-17 16:30:22 +08:00
wuzhenghui
eb45eec5db
change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 2023-11-16 20:40:03 +08:00
wuzhenghui
6ae596c764
fix(esp_hw_support): fix lightsleep current leakage on usb-phy controlled pad 2023-11-16 20:03:30 +08:00
Ivan Grokhotkov
c43b66cd35
fix(soc): update SOC_IROM_MASK_HIGH for esp32, c6, h2 for consistency 2023-11-14 14:27:24 +01:00
Ivan Grokhotkov
6fa2080706
fix(soc): correct SOC_IROM_MASK_HIGH for esp32s3 
Fixes corrupted backtraces on S3 when a function is in ROM.

Closes https://github.com/espressif/esp-idf/issues/11512
 2023-11-14 14:27:23 +01:00
Jiang Jiang Jian
0172c33818 Merge branch 'bugfix/fix_deinit_init_wifi_scan_fail_issue_v5.1' into 'release/v5.1' 
Bugfix/fix deinit init wifi scan fail issue v5.1(Backport v5.1)

See merge request espressif/esp-idf!27064
 2023-11-14 15:25:54 +08:00
gaoxu
c5e107c53d feat(adc_cali): Add ADC calibration support for ESP32H2 2023-11-13 03:04:03 +00:00
muhaidong
666ba33829 fix(wifi): fix deinit init wifi scan fail issue 2023-11-10 11:15:38 +08:00
KonstantinKondrashov
d9b776c59a feat(efuse): Adds efuse ADC calibration data for ESP32H2 2023-11-07 15:41:59 +08:00
Song Ruo Jing
4892c481b5 feat(gpio): add a dump API to dump IO configurations 
Merges https://github.com/espressif/esp-idf/pull/12511
 2023-11-03 16:21:31 +08:00
Lou Tianhao
9b3e40c9d1 feat(pm/deepsleep): Support EXT1_WAKEUP_MODE_PER_PIN 2023-11-03 11:02:56 +08:00
Jiang Jiang Jian
1aabb5f0d5 Merge branch 'bugfix/revert_pvt_v5.1' into 'release/v5.1' 
Revert "feat(volt): chip auto adjust volt for esp32c6 & esp32h2" (v5.1)

See merge request espressif/esp-idf!26485
 2023-10-18 10:44:14 +08:00