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fix(system): update reset reasons for C6 and H2
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@ -82,7 +82,6 @@ typedef enum {
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TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
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TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
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RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
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INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
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TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
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RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
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RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
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@ -90,11 +89,11 @@ typedef enum {
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RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
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TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
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SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
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GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
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EFUSE_RESET = 20, /**<20, efuse reset digital core*/
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USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
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USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
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POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
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JTAG_CPU_RESET = 24, /**<24, jtag reset CPU*/
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} RESET_REASON;
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// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
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@ -111,11 +110,11 @@ ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
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ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
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ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
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ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
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ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
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ESP_STATIC_ASSERT((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
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ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_CPU_RESET == RESET_REASON_CPU0_JTAG, "JTAG_CPU_RESET != RESET_REASON_CPU0_JTAG");
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typedef enum {
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NO_SLEEP = 0,
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@ -33,6 +33,11 @@ typedef enum {
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ESP_RST_DEEPSLEEP, //!< Reset after exiting deep sleep mode
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ESP_RST_BROWNOUT, //!< Brownout reset (software or hardware)
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ESP_RST_SDIO, //!< Reset over SDIO
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ESP_RST_USB, //!< Reset by USB peripheral
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ESP_RST_JTAG, //!< Reset by JTAG
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ESP_RST_EFUSE, //!< Reset due to efuse error
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ESP_RST_PWR_GLITCH, //!< Reset due to power glitch detected
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ESP_RST_CPU_LOCKUP, //!< Reset due to CPU lock up
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} esp_reset_reason_t;
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/**
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@ -50,6 +50,19 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
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case RESET_REASON_SYS_BROWN_OUT:
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return ESP_RST_BROWNOUT;
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case RESET_REASON_CORE_USB_UART:
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case RESET_REASON_CORE_USB_JTAG:
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return ESP_RST_USB;
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case RESET_REASON_CORE_EFUSE_CRC:
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return ESP_RST_EFUSE;
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case RESET_REASON_CPU0_JTAG:
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return ESP_RST_JTAG;
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case RESET_REASON_CORE_SDIO:
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return ESP_RST_SDIO;
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default:
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return ESP_RST_UNKNOWN;
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}
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@ -50,6 +50,19 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
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case RESET_REASON_SYS_BROWN_OUT:
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return ESP_RST_BROWNOUT;
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case RESET_REASON_CORE_USB_UART:
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case RESET_REASON_CORE_USB_JTAG:
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return ESP_RST_USB;
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case RESET_REASON_CORE_EFUSE_CRC:
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return ESP_RST_EFUSE;
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case RESET_REASON_CORE_PWR_GLITCH:
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return ESP_RST_PWR_GLITCH;
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case RESET_REASON_CPU0_JTAG:
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return ESP_RST_JTAG;
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default:
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return ESP_RST_UNKNOWN;
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}
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@ -23,7 +23,6 @@ extern "C" {
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#endif
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// TODO: IDF-5719
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/**
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* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
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* @note refer to TRM: <Reset and Clock> chapter
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@ -23,7 +23,6 @@ extern "C" {
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#endif
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// ESP32H2-TODO: IDF-5719 Need update
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/**
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* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
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* @note refer to TRM: <Reset and Clock> chapter
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@ -31,7 +30,6 @@ extern "C" {
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typedef enum {
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RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
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RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
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RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
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RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
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RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
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RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
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@ -44,11 +42,11 @@ typedef enum {
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RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
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RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
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RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
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RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
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RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
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RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core
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RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core
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RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
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RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
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} soc_reset_reason_t;
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