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For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same address range is part of CPU Subsystem range which contains debug mode specific code and interrupt config registers (CLINT, PLIC etc.). For now the PMP entry is provided with RWX permission for both machine and user mode but we can save this entry and allow the access to only machine mode for this range. For P4/C5 case, this PMP entry can have RW permission as the debug mode specific code is not present in this memory range.
soc
The soc component provides hardware description for targets supported by ESP-IDF.
- `xxx_reg.h` - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h` - features/capabilities of the hardware
- `xxx_pins.h` - pin definitions
- `xxx_periph.h/*.c` - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware