alex/esp-idf
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32,789 Commits 20 Branches 148 Tags 384 MiB
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Commit Graph

411 Commits

Author SHA1 Message Date
Song Ruo Jing
c57bfa3737 fix(gpio_etm): allow one GPIO binds to multiple ETM tasks 2024-04-24 17:10:03 +08:00
Cao Sen Miao
9025e440ae fix(temperature_sensor): Cannot switch the range smmothly on esp32h2 2024-02-28 12:39:07 +08:00
morris
92b25c06b3 Merge branch 'bugfix/fix_incorrect_regbase_name_of_i2s_v5.1' into 'release/v5.1' 
fix(i2s): fixed incorrect reg base name on C3 (v5.1)

See merge request espressif/esp-idf!28630
 2024-02-28 11:41:58 +08:00
Aditya Patwardhan
55c5c8367b Merge branch 'bugfix/soc_cpu_subsys_region_v5.1' into 'release/v5.1' 
fix(soc): change debug addr range to CPU subsystem range (v5.1)

See merge request espressif/esp-idf!28672
 2024-02-28 11:16:48 +08:00
Jiang Jiang Jian
c404e951e3 Merge branch 'docs/rf_coexistence_api_guides_support_esp32c2_v5.1' into 'release/v5.1' 
Docs: RF coexistence api guides support esp32c2 (v5.1)

See merge request espressif/esp-idf!29214
 2024-02-28 11:09:29 +08:00
linruihao
89881c7c59 fix(esp_coex): add support_coexistence soc_caps for esp32c2 and esp32h2 2024-02-23 16:26:10 +08:00
Marius Vikhammer
d9a6158700 fix(system): update reset reasons for C6 and H2 2024-02-22 12:36:09 +08:00
KonstantinKondrashov
f7a920685a feat(efuse): Adds new efuse for esp32h2 2024-01-26 11:39:16 +08:00
Mahavir Jain
614ad494f6
fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
 2024-01-24 12:52:27 +05:30
laokaiyao
d7b6ebe7df fix(i2s): fixed incorrect reg base name on C3 
Closes https://github.com/espressif/esp-idf/issues/12643
 2024-01-23 12:05:45 +08:00
Roshan Bangar
dc9d9b41f2 fix(nimble): Added periodic_adv_enh soc_caps for c2, h2 2023-12-27 15:03:17 +05:30
Xu Si Yu
866bc77246 feat(ieee802154): add tx/rx report for IEEE802.15.4 debug 2023-12-21 15:17:54 +08:00
Jiang Jiang Jian
487adc09f4 Merge branch 'change/change_regdma_power_issue_macro_v5.1' into 'release/v5.1' 
change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG (backport v5.1)

See merge request espressif/esp-idf!27991
 2023-12-21 11:27:10 +08:00
Marius Vikhammer
40bea117e4 Merge branch 'bugfix/s3_irom_addr_v5.1' into 'release/v5.1' 
soc: fix SOC_IROM_MASK_HIGH for esp32s3 (v5.1)

See merge request espressif/esp-idf!27136
 2023-12-20 10:00:39 +08:00
Lou Tianhao
1419db4b91 change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG 2023-12-19 11:44:23 +08:00
morris
eb7022dd06 Merge branch 'contrib/github_pr_12559_v5.1' into 'release/v5.1' 
fix(spi): Correct REG_SPI_BASE(i) macro for all targets (GitHub PR) (v5.1)

See merge request espressif/esp-idf!27714
 2023-12-14 11:08:03 +08:00
Mahavir Jain
ca02c6d274 Merge branch 'fix/rng_register_prefix_discrepency_newer_targets_v5.1' into 'release/v5.1' 
Fix: RNG register prefix discrepancy for ESP32C6 and ESP32H2 (v5.1)

See merge request espressif/esp-idf!27684
 2023-12-08 12:01:36 +08:00
harshal.patil
6a990a37ce
fix(soc/esp32h2): Fix llperi_rng_data field discrepancy 2023-12-07 11:42:00 +05:30
gaoxu
6190b3f7c9 fix(adc): restore cali registers after light sleep wake up on H2 and enable test 2023-12-06 10:19:52 +00:00
wanlei
3486cf1b60 fix(spi): correct some signals and dummy bits docs 2023-12-06 16:15:23 +08:00
TD-er
8e0d64e94c fix(spi): Correct REG_SPI_BASE(i) macro for all targets 
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
 2023-12-06 16:13:01 +08:00
Shu Chen
ecbbd3c3d9 Merge branch 'backport/add_ot_radio_stats_enable_config_5_1' into 'release/v5.1' 
feat(openthread): backport some openthread features(BackportV5.1)

See merge request espressif/esp-idf!26885
 2023-11-22 12:23:53 +08:00
Mahavir Jain
0ccfa4b0c2
fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose 
In ESP32-H2, the ECDSA peripheral by default uses the TRNG (hardware)
generated k value but it can be overridden to software supplied k.
This can happen through by overriding the `ECDSA_SOFTWARE_SET_K` bit
in the configuration register. Even though the HAL API is not exposed
for this but still it could be achieved by direct register
programming. And for this scenario, if sufficiently random k is not
supplied by the software then it could posses a security risk.

In this change, we are unconditionally programming the efuse
`ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K` bit during startup security
checks itself. Additionally, same is ensured in the `esp_efuse_write_key`
API as well. This always enforces the hardware k mode in the ECDSA
peripheral and ensures strongest possible security.
 2023-11-20 16:03:29 +05:30
Jiang Jiang Jian
5719d882d1 Merge branch 'bugfix/fix_onebyte_watchpoint_setting_v5.1' into 'release/v5.1' 
fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting (v5.1)

See merge request espressif/esp-idf!27215
 2023-11-20 17:37:03 +08:00
morris
1b3713f7cd Merge branch 'feature/support_adc_calibration_on_h2_v5.1' into 'release/v5.1' 
adc_cali: supported adc calibration v1 on ESP32H2 (v5.1)

See merge request espressif/esp-idf!26963
 2023-11-17 16:41:00 +08:00
morris
ddb6d22468 Merge branch 'feature/gpio_dump_io_info_v5.1' into 'release/v5.1' 
feat(gpio): add a dump API to dump IO configurations (v5.1)

See merge request espressif/esp-idf!26870
 2023-11-17 16:30:22 +08:00
wuzhenghui
eb45eec5db
change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 2023-11-16 20:40:03 +08:00
Ivan Grokhotkov
c43b66cd35
fix(soc): update SOC_IROM_MASK_HIGH for esp32, c6, h2 for consistency 2023-11-14 14:27:24 +01:00
gaoxu
c5e107c53d feat(adc_cali): Add ADC calibration support for ESP32H2 2023-11-13 03:04:03 +00:00
KonstantinKondrashov
d9b776c59a feat(efuse): Adds efuse ADC calibration data for ESP32H2 2023-11-07 15:41:59 +08:00
Song Ruo Jing
4892c481b5 feat(gpio): add a dump API to dump IO configurations 
Merges https://github.com/espressif/esp-idf/pull/12511
 2023-11-03 16:21:31 +08:00
Lou Tianhao
9b3e40c9d1 feat(pm/deepsleep): Support EXT1_WAKEUP_MODE_PER_PIN 2023-11-03 11:02:56 +08:00
zlq
17c2931309 feat(bootloader): adjust dbias of bootloader, change clock of H2 to 64 
MHz
 2023-10-16 14:35:45 +08:00
Xiao Xufeng
81dcc61008 Revert "feat(volt): chip auto adjust volt for esp32c6 & esp32h2" 
This reverts commit b221f87e00.
 2023-10-16 14:35:41 +08:00
wuzhenghui
49013a0560 feat(modem_clock): separate management of modem_adc_common_fe clock and modem_private_fe 2023-09-28 16:24:39 +00:00
zlq
7bbe19d92f feat(volt): chip auto adjust volt for esp32c6 & esp32h2 2023-09-27 06:39:59 +00:00
cjin
179e3293be change: remove has clock bug macro for esp32h2 2023-09-25 13:40:26 +08:00
Marius Vikhammer
41a291fee0 fix(wdt): changed WDT clock source to XTAL for C6/H2 
Previously it used PLL, but PLL could potentially be powered down by power-management
when CPU frequency changed.
 2023-09-13 10:45:51 +08:00
Marius Vikhammer
c192ea478e fix(wdt): changed ESP32-C3 WDT to use XTAL as clock 
This clock is unchanged even when CPU/APB frequency changes (e.g. due to esp_pm),
which means timeout period is correct even after such a change.
 2023-09-13 10:45:49 +08:00
Jiang Jiang Jian
9eceef649b Merge branch 'bugfix/esp32h2_update_desc_ecdsa_workmode_v5.1' into 'release/v5.1' 
fix(soc/esp32h2): Update the description of the ECDSA_WORK_MODE (backport v5.1)

See merge request espressif/esp-idf!25818
 2023-09-08 16:09:42 +08:00
Jiang Guang Ming
9ed6944c0d fix(soc/esp32h2): Update the description of the ECDSA_WORK_MODE 2023-09-07 10:34:36 +08:00
wuzhenghui
d3bfaf8f5f feat(esp_hw_support): manage modem_etm clock in modem_clock for bt/154 indepently 2023-09-06 15:48:37 +08:00
Chen Jichang
c240a1f46b feat(MCPWM): Add mcpwm carrier clk source 
The MCPWM carrier is part of the operator and can work independently
without the MCPWM timer being enabled. This commit add the MCPWM
carrier clk source.
 2023-08-25 17:34:58 +08:00
Jiang Jiang Jian
b638cb3335 Merge branch 'bringup/esp32h2_deep_sleep_for_rebase_v5.1' into 'release/v5.1' 
esp32h2: support deep_sleep(backport v5.1)

See merge request espressif/esp-idf!24962
 2023-08-23 20:12:01 +08:00
wuzhenghui
aaf04f514f fix(esp_hw_support): manage i2c_ana_mst clock witch modem clock driver 2023-08-04 12:04:40 +08:00
Lou Tianhao
b27e57db7b feat(pm/deepsleep): Support EXT1 wakeup for esp32h2 deep_sleep 2023-08-03 16:46:55 +08:00
Song Ruo Jing
6768f098dc change(driver/rtcio): Describe RTCIO CAPS with more accurate note 2023-08-03 16:46:55 +08:00
Lou Tianhao
4bc5e24f82 feat(pm/deepsleep): Support deep_sleep example and deep_sleep_wake_stub example for esp32h2 2023-08-03 16:46:54 +08:00
Jiang Jiang Jian
d83fe16c93 Merge branch 'bugfix/revert_26mhz_esp32c2_bad_apb_clock_fix' into 'release/v5.1' 
Revert "fix(soc): fix wrong freq definition for 26Mhz version esp32c2 soc" (v5.1)

See merge request espressif/esp-idf!24983
 2023-07-31 10:26:58 +08:00
Jiang Jiang Jian
d026b92c75 Merge branch 'bugfix/fix_c6_wrong_pwdet_register_v5.1' into 'release/v5.1' 
pwdet: fix pwdet wrong base address on c6 h2 (v5.1)

See merge request espressif/esp-idf!25025
 2023-07-31 10:22:57 +08:00