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Merge branch 'bringup/esp32h2_deep_sleep_for_rebase_v5.1' into 'release/v5.1'

Browse Source 
esp32h2: support deep_sleep(backport v5.1)

See merge request espressif/esp-idf!24962
This commit is contained in:
Jiang Jiang Jian 2023-08-23 20:12:01 +08:00
commit b638cb3335
41 changed files with 804 additions and 222 deletions
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2
components/driver/gpio/gpio.c
View File

@ -361,7 +361,7 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
if (((gpio_pin_mask >> io_num) & BIT(0))) {
assert(io_reg != (intptr_t)NULL);
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_PIN_COUNT > 0
if (rtc_gpio_is_valid_gpio(io_num)) {
rtc_gpio_deinit(io_num);
}

45
components/driver/gpio/include/driver/rtc_io.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -28,7 +28,7 @@ bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num);
#define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num)
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_PIN_COUNT > 0
/**
* @brief Get RTC IO index number by gpio number.
*
@ -63,6 +63,7 @@ esp_err_t rtc_gpio_init(gpio_num_t gpio_num);
*/
esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num);
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
/**
* @brief Get the RTC IO input level
*
@ -231,24 +232,6 @@ esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num);
*/
esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num);
/**
* @brief Helper function to disconnect internal circuits from an RTC IO
* This function disables input, output, pullup, pulldown, and enables
* hold feature for an RTC IO.
* Use this function if an RTC IO needs to be disconnected from internal
* circuits in deep sleep, to minimize leakage current.
*
* In particular, for ESP32-WROVER module, call
* rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce
* deep sleep current.
*
* @param gpio_num GPIO number (e.g. GPIO_NUM_12).
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if GPIO is not an RTC IO
*/
esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num);
/**
* @brief Enable force hold signal for all RTC IOs
*
@ -267,6 +250,26 @@ esp_err_t rtc_gpio_force_hold_dis_all(void);
#endif // SOC_RTCIO_HOLD_SUPPORTED
#if SOC_RTCIO_HOLD_SUPPORTED && SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
/**
* @brief Helper function to disconnect internal circuits from an RTC IO
* This function disables input, output, pullup, pulldown, and enables
* hold feature for an RTC IO.
* Use this function if an RTC IO needs to be disconnected from internal
* circuits in deep sleep, to minimize leakage current.
*
* In particular, for ESP32-WROVER module, call
* rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce
* deep sleep current.
*
* @param gpio_num GPIO number (e.g. GPIO_NUM_12).
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if GPIO is not an RTC IO
*/
esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num);
#endif // SOC_RTCIO_HOLD_SUPPORTED && SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_WAKE_SUPPORTED
/**
@ -292,6 +295,8 @@ esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num);
#endif // SOC_RTCIO_WAKE_SUPPORTED
#endif // SOC_RTCIO_PIN_COUNT > 0
#ifdef __cplusplus
}
#endif

58
components/driver/gpio/rtc_io.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -13,6 +13,7 @@
#include "freertos/timers.h"
#include "driver/rtc_io.h"
#include "hal/rtc_io_hal.h"
#include "soc/rtc_io_periph.h"
#include "soc/soc_caps.h"
static const char __attribute__((__unused__)) *RTCIO_TAG = "RTCIO";
@ -21,11 +22,24 @@ extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate posi
#define RTCIO_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
#define RTCIO_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num)
{
#if SOC_RTCIO_PIN_COUNT > 0
return (gpio_num < GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0);
#else
return false;
#endif
}
#if SOC_RTCIO_PIN_COUNT > 0
/*---------------------------------------------------------------
RTC IO
---------------------------------------------------------------*/
int rtc_io_number_get(gpio_num_t gpio_num)
{
return rtc_io_num_map[gpio_num];
}
esp_err_t rtc_gpio_init(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
@ -47,6 +61,7 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num)
return ESP_OK;
}
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
@ -167,16 +182,6 @@ esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num)
return ESP_OK;
}
esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
rtcio_hal_isolate(rtc_io_number_get(gpio_num));
RTCIO_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rtc_gpio_force_hold_en_all(void)
{
RTCIO_ENTER_CRITICAL();
@ -196,6 +201,18 @@ esp_err_t rtc_gpio_force_hold_dis_all(void)
}
#endif // SOC_RTCIO_HOLD_SUPPORTED
#if SOC_RTCIO_HOLD_SUPPORTED && SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
rtcio_hal_isolate(rtc_io_number_get(gpio_num));
RTCIO_EXIT_CRITICAL();
return ESP_OK;
}
#endif // SOC_RTCIO_HOLD_SUPPORTED && SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_WAKE_SUPPORTED
esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
@ -221,19 +238,4 @@ esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num)
#endif // SOC_RTCIO_WAKE_SUPPORTED
bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num)
{
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
return (gpio_num < GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0);
#else
return false;
#endif
}
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
int rtc_io_number_get(gpio_num_t gpio_num)
{
return rtc_io_num_map[gpio_num];
}
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#endif // SOC_RTCIO_PIN_COUNT > 0

2
components/driver/test_apps/gpio/main/CMakeLists.txt
View File

@ -5,7 +5,7 @@ if(CONFIG_SOC_SDM_SUPPORTED)
list(APPEND srcs "test_sigma_delta_legacy.c")
endif()
if(CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED)
if(CONFIG_SOC_RTCIO_PIN_COUNT GREATER 0)
list(APPEND srcs "test_rtcio.c")
endif()

32
components/driver/test_apps/gpio/main/test_rtcio.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -17,12 +17,6 @@
#include "esp_log.h"
#include "soc/rtc_io_periph.h"
#define RTCIO_CHECK(condition) TEST_ASSERT_MESSAGE((condition == ESP_OK), "ret is not ESP_OK")
#define RTCIO_VERIFY(condition, msg) TEST_ASSERT_MESSAGE((condition), msg)
#define TEST_COUNT 10
static const char *TAG = "rtcio_test";
#ifdef CONFIG_IDF_TARGET_ESP32
// The input-only rtcio pins do not have pull-up/down resistors (not support pull-up/down)
#define RTCIO_SUPPORT_PU_PD(num) (rtc_io_desc[num].pullup != 0)
@ -117,8 +111,27 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
};
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_PIN_COUNT 8
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_7, //GPIO7
GPIO_NUM_8, //GPIO8
GPIO_NUM_9, //GPIO9
GPIO_NUM_10, //GPIO10
GPIO_NUM_11, //GPIO11
GPIO_NUM_12, //GPIO12
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
};
#endif
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
static const char *TAG = "rtcio_test";
#define RTCIO_CHECK(condition) TEST_ASSERT_MESSAGE((condition == ESP_OK), "ret is not ESP_OK")
#define TEST_COUNT 10
/*
* Test output/input function.
*/
@ -325,10 +338,12 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
}
ESP_LOGI(TAG, "RTCIO hold test over");
}
#endif //SOC_RTCIO_HOLD_SUPPORTED
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
// It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
// Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5) these pads' default configuration is low level
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12) these pads' default configuration is low level
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5
static void rtcio_deep_sleep_hold_test_first_stage(void)
@ -374,4 +389,3 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]",
rtcio_deep_sleep_hold_test_first_stage,
rtcio_deep_sleep_hold_test_second_stage)
#endif //SOC_RTCIO_HOLD_SUPPORTED

1
components/driver/test_apps/gpio/pytest_gpio.py
View File

@ -33,6 +33,7 @@ def test_legacy_sigma_delta(dut: IdfDut) -> None:
@pytest.mark.esp32s2
@pytest.mark.esp32s3
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.generic
@pytest.mark.parametrize('config', CONFIGS, indirect=True)
def test_rtc_io(dut: IdfDut) -> None:

6
components/esp_hw_support/CMakeLists.txt
View File

@ -114,12 +114,6 @@ if(NOT BOOTLOADER_BUILD)
if(CONFIG_SOC_RTC_FAST_MEM_SUPPORTED)
list(APPEND srcs "sleep_wake_stub.c")
endif()
if(CONFIG_IDF_TARGET_ESP32H2)
list(REMOVE_ITEM srcs
"sleep_wake_stub.c" # TODO: IDF-6268
)
endif()
else()
# Requires "_esp_error_check_failed()" function
list(APPEND priv_requires "esp_system")

36
components/esp_hw_support/include/esp_sleep.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -26,10 +26,21 @@ typedef void (*esp_deep_sleep_cb_t)(void);
/**
* @brief Logic function used for EXT1 wakeup mode.
*/
#if SOC_PM_SUPPORT_EXT1_WAKEUP
#if CONFIG_IDF_TARGET_ESP32
typedef enum {
ESP_EXT1_WAKEUP_ALL_LOW = 0, //!< Wake the chip when all selected GPIOs go low
ESP_EXT1_WAKEUP_ANY_HIGH = 1 //!< Wake the chip when any of the selected GPIOs go high
} esp_sleep_ext1_wakeup_mode_t;
#else
typedef enum {
ESP_EXT1_WAKEUP_ANY_LOW = 0, //!< Wake the chip when any of the selected GPIOs go low
ESP_EXT1_WAKEUP_ANY_HIGH = 1, //!< Wake the chip when any of the selected GPIOs go high
ESP_EXT1_WAKEUP_ALL_LOW __attribute__((deprecated("wakeup mode \"ALL_LOW\" is no longer supported after ESP32, \
please use ESP_EXT1_WAKEUP_ANY_LOW instead"))) = ESP_EXT1_WAKEUP_ANY_LOW
} esp_sleep_ext1_wakeup_mode_t;
#endif
#endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
typedef enum {
@ -250,18 +261,27 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level);
* @note Internal pullups and pulldowns don't work when RTC peripherals are
* shut down. In this case, external resistors need to be added.
* Alternatively, RTC peripherals (and pullups/pulldowns) may be
* kept enabled using esp_sleep_pd_config function.
* kept enabled using esp_sleep_pd_config function. If we turn off the
* ``RTC_PERIPH`` domain or certain chips lack the ``RTC_PERIPH`` domain,
* we will use the HOLD feature to maintain the pull-up and pull-down on
* the pins during sleep. HOLD feature will be acted on the pin internally
* before the system entering sleep, and this can further reduce power consumption.
*
* @param mask bit mask of GPIO numbers which will cause wakeup. Only GPIOs
* which have RTC functionality can be used in this bit map.
* For different SoCs, the related GPIOs are:
* - ESP32: 0, 2, 4, 12-15, 25-27, 32-39;
* - ESP32-S2: 0-21;
* - ESP32-S3: 0-21.
* - ESP32-C6: 0-7.
* - ESP32: 0, 2, 4, 12-15, 25-27, 32-39
* - ESP32-S2: 0-21
* - ESP32-S3: 0-21
* - ESP32-C6: 0-7
* - ESP32-H2: 7-14
* @param mode select logic function used to determine wakeup condition:
* - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low
* - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high
* When target chip is ESP32:
* - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low
* - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high
* When target chip is ESP32-S2, ESP32-S3, ESP32-C6 or ESP32-H2:
* - ESP_EXT1_WAKEUP_ANY_LOW: wake up when any of the selected GPIOs is low
* - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO,

3
components/esp_hw_support/port/esp32h2/pmu_sleep.c
View File

@ -14,6 +14,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/pmu_struct.h"
#include "hal/lp_aon_hal.h"
#include "esp_private/esp_pmu.h"
#define HP(state) (PMU_MODE_HP_ ## state)
@ -218,6 +219,8 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
{
assert(PMU_instance()->hal);
lp_aon_hal_inform_wakeup_type(dslp);
pmu_ll_hp_set_wakeup_enable(PMU_instance()->hal->dev, wakeup_opt);
pmu_ll_hp_set_reject_enable(PMU_instance()->hal->dev, reject_opt);

21
components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
View File

@ -337,34 +337,33 @@ typedef struct {
.pd_cur = 1, \
.bias_sleep = 1, \
.xpd = 0, \
.dbias = 0x15, \
.slp_mem_xpd = 1, \
.slp_mem_dbias = 0xc, \
.slp_logic_xpd = 1, \
.slp_logic_dbias = 0x5, \
.drv_b = 0x18c \
.dbias = 0, \
.slp_mem_xpd = 0, \
.slp_mem_dbias = 0, \
.slp_logic_xpd = 0, \
.slp_logic_dbias = 0, \
.drv_b = 0xFFFFFF \
} \
}, \
.lp_sys[PMU_MODE_LP_ACTIVE] = { \
.analog = { \
.xpd = 1, \
.dbias = 0x1a, \
.dbias = 0xe, \
.slp_xpd = 0, \
.slp_dbias = 0, \
.drv_b = 0x7 \
.drv_b = 0 \
} \
}, \
.lp_sys[PMU_MODE_LP_SLEEP] = { \
.analog = { \
.xpd_bias = 0, \
.dbg_atten = 0xe, \
.pd_cur = 1, \
.bias_sleep = 1, \
.xpd = 0, \
.dbias = 0, \
.slp_xpd = 1, \
.slp_dbias = 0xe, \
.drv_b = 0 \
.slp_dbias = 5, \
.drv_b = 7 \
} \
} \
}

3
components/esp_hw_support/sleep_gpio.c
View File

@ -20,14 +20,13 @@
#include "driver/gpio.h"
#include "hal/gpio_hal.h"
#include "hal/rtc_io_hal.h"
#include "soc/rtc_io_periph.h"
#if SOC_LP_AON_SUPPORTED
#include "hal/lp_aon_hal.h"
#else
#if !CONFIG_IDF_TARGET_ESP32H2
#include "hal/rtc_hal.h"
#endif
#endif
#include "esp_private/gpio.h"
#include "esp_private/sleep_gpio.h"

45
components/esp_hw_support/sleep_modes.c
View File

@ -32,11 +32,9 @@
#if SOC_LP_AON_SUPPORTED
#include "hal/lp_aon_hal.h"
#else
#if !CONFIG_IDF_TARGET_ESP32H2
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_hal.h"
#endif
#endif
#include "driver/uart.h"
@ -90,6 +88,7 @@
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/rtc.h"
#include "soc/extmem_reg.h"
#include "hal/gpio_ll.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
@ -262,7 +261,6 @@ static void touch_wakeup_prepare(void);
static void gpio_deep_sleep_wakeup_prepare(void);
#endif
#if !CONFIG_IDF_TARGET_ESP32H2
#if SOC_RTC_FAST_MEM_SUPPORTED
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
static RTC_FAST_ATTR esp_deep_sleep_wake_stub_fn_t wake_stub_fn_handler = NULL;
@ -368,7 +366,6 @@ void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void)
void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
#endif // SOC_RTC_FAST_MEM_SUPPORTED
#endif // !CONFIG_IDF_TARGET_ESP32H2
void esp_deep_sleep(uint64_t time_in_us)
{
@ -626,7 +623,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
#endif
}
#endif
misc_modules_sleep_prepare(deep_sleep);
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
@ -666,7 +662,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
if (periph_using_8m) {
sleep_flags |= RTC_SLEEP_DIG_USE_8M;
}
// Enter sleep
esp_err_t result;
#if SOC_PMU_SUPPORTED
@ -706,7 +701,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
esp_sleep_isolate_digital_gpio();
#endif
#if !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6268
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
esp_set_deep_sleep_wake_stub_default_entry();
// Enter Deep Sleep
@ -727,9 +721,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
#endif
#endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
#else // !CONFIG_IDF_TARGET_ESP32H2
result = ESP_OK;
#endif // !CONFIG_IDF_TARGET_ESP32H2
} else {
/* Wait cache idle in cache suspend to avoid cache load wrong data after spi io isolation */
cache_hal_suspend(CACHE_TYPE_ALL);
@ -1305,11 +1296,11 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
{
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_PIN_COUNT > 0
return RTC_GPIO_IS_VALID_GPIO(gpio_num);
#else
return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#endif
}
#if SOC_PM_SUPPORT_EXT0_WAKEUP
@ -1381,20 +1372,23 @@ static void ext1_wakeup_prepare(void)
rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_RTC);
// set input enable in sleep mode
rtcio_hal_input_enable(rtc_pin);
#endif
#if SOC_PM_SUPPORT_RTC_PERIPH_PD
// Pad configuration depends on RTC_PERIPH state in sleep mode
if (s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option != ESP_PD_OPTION_ON) {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
// RTC_PERIPH will be powered down, so RTC_IO_ registers will
// loose their state. Lock pad configuration.
// Pullups/pulldowns also need to be disabled.
rtcio_hal_pullup_disable(rtc_pin);
rtcio_hal_pulldown_disable(rtc_pin);
#endif
rtcio_hal_hold_enable(rtc_pin);
}
#endif
#else
/* ESP32H2 use hp iomux to config rtcio, and there is no complete
* rtcio functionality. In the case of EXT1 wakeup, rtcio only provides
* a pathway to EXT1. */
// Route pad to DIGITAL
rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_DIGITAL);
// set input enable
gpio_ll_input_enable(&GPIO, gpio);
// hold rtc_pin to use it during sleep state
rtcio_hal_hold_enable(rtc_pin);
#endif
// Keep track of pins which are processed to bail out early
rtc_gpio_mask &= ~BIT(rtc_pin);
@ -1402,7 +1396,7 @@ static void ext1_wakeup_prepare(void)
// Clear state from previous wakeup
rtc_hal_ext1_clear_wakeup_status();
// Set RTC IO pins and mode (any high, all low) to be used for wakeup
// Set RTC IO pins and mode to be used for wakeup
rtc_hal_ext1_set_wakeup_pins(s_config.ext1_rtc_gpio_mask, s_config.ext1_trigger_mode);
}
@ -1432,20 +1426,14 @@ uint64_t esp_sleep_get_ext1_wakeup_status(void)
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
uint64_t esp_sleep_get_gpio_wakeup_status(void)
{
#if CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6268
return 0;
#else
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_GPIO) {
return 0;
}
return rtc_hal_gpio_get_wakeup_status();
#endif // !CONFIG_IDF_TARGET_ESP32H2
}
static void gpio_deep_sleep_wakeup_prepare(void)
{
#if !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6268
for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++) {
if (((1ULL << gpio_idx) & s_config.gpio_wakeup_mask) == 0) {
continue;
@ -1461,7 +1449,6 @@ static void gpio_deep_sleep_wakeup_prepare(void)
}
// Clear state from previous wakeup
rtc_hal_gpio_clear_wakeup_status();
#endif // !CONFIG_IDF_TARGET_ESP32H2
}
esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepsleep_gpio_wake_up_mode_t mode)

2
components/esp_rom/include/esp32h2/rom/rtc.h
View File

@ -51,6 +51,7 @@ extern "C" {
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
* LP_AON_STORE8_REG Store light sleep wake stub addr
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
*************************************************************************************
*/
@ -63,6 +64,7 @@ extern "C" {
#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG
#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG
#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG
#define SLEEP_MODE_REG LP_AON_STORE9_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.

2
components/esp_system/ld/esp32h2/sections.ld.in
View File

@ -17,6 +17,8 @@ SECTIONS
{
. = ALIGN(4);
_rtc_fast_start = ABSOLUTE(.);
_rtc_text_start = ABSOLUTE(.);
*(.rtc.entry.text)
mapping[rtc_text]

10
components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
View File

@ -41,7 +41,6 @@
__attribute__((unused)) static struct timeval tv_start, tv_stop;
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32H2)
static void check_sleep_reset(void)
{
@ -419,7 +418,11 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is off (13 low)", "[deepsleep][ign
{
// This test needs external pullup
ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
#if CONFIG_IDF_TARGET_ESP32
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ALL_LOW));
#else
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_LOW));
#endif
esp_deep_sleep_start();
}
@ -439,7 +442,11 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 low)", "[deepsleep][igno
ESP_ERROR_CHECK(gpio_pullup_en(GPIO_NUM_13));
ESP_ERROR_CHECK(gpio_pulldown_dis(GPIO_NUM_13));
ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON));
#if CONFIG_IDF_TARGET_ESP32
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ALL_LOW));
#else
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_LOW));
#endif
esp_deep_sleep_start();
}
#endif // SOC_PM_SUPPORT_EXT1_WAKEUP
@ -658,4 +665,3 @@ TEST_CASE("wake up using GPIO (2 or 4 low)", "[deepsleep][ignore]")
esp_deep_sleep_start();
}
#endif // SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32H2) TODO: IDF-6268

17
components/hal/esp32c6/include/hal/lp_aon_hal.h
View File

@ -8,17 +8,10 @@
#include "hal/lp_aon_ll.h"
#define rtc_hal_ext1_get_wakeup_status() lp_aon_hal_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_hal_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(mask, mode) lp_aon_hal_ext1_set_wakeup_pins(mask, mode)
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_hal_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_hal_ext1_get_wakeup_pins()
#define lp_aon_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
#define lp_aon_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
#define lp_aon_hal_ext1_set_wakeup_pins(mask, mode) lp_aon_ll_ext1_set_wakeup_pins(mask, mode)
#define lp_aon_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
#define lp_aon_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(mask, mode) lp_aon_ll_ext1_set_wakeup_pins(mask, mode)
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)

2
components/hal/esp32c6/include/hal/lp_aon_ll.h
View File

@ -40,7 +40,7 @@ static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
/**
* @brief Set the wake-up LP_IO of the ext1 wake-up source
* @param mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
* @param mode 0: Wake the chip when all selected GPIOs go low
* @param mode 0: Wake the chip when any of the selected GPIOs go low
* 1: Wake the chip when any of the selected GPIOs go high
*/
static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t mask, int mode)

17
components/hal/esp32h2/include/hal/lp_aon_hal.h Normal file
View File

@ -0,0 +1,17 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/lp_aon_ll.h"
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(mask, mode) lp_aon_ll_ext1_set_wakeup_pins(mask, mode)
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)

97
components/hal/esp32h2/include/hal/lp_aon_ll.h Normal file
View File

@ -0,0 +1,97 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H2 LP_AON register operations
#pragma once
#include <stdlib.h>
#include "soc/soc.h"
#include "soc/lp_aon_struct.h"
#include "hal/misc.h"
#include "esp32h2/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get ext1 wakeup source status
* @return The lower 8 bits of the returned value are the bitmap of
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
*/
static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
}
/**
* @brief Clear the ext1 wakeup source status
*/
static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
}
/**
* @brief Set the wake-up LP_IO of the ext1 wake-up source
* @param mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
* @param mode 0: Wake the chip when any of the selected GPIOs go low
* 1: Wake the chip when any of the selected GPIOs go high
*/
static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t mask, int mode)
{
uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
wakeup_sel_mask |= mask;
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
if (mode) {
wakeup_level_mask |= mask;
} else {
wakeup_level_mask &= ~mask;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
}
/**
* @brief Clear all ext1 wakup-source setting
*/
static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
}
/**
* @brief Get ext1 wakeup source setting
* @return The lower 8 bits of the returned value are the bitmap of
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
*/
static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
}
/**
* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
* Set the flag to inform
* @param true: deepsleep false: lightsleep
*/
static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
{
if (dslp) {
REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
} else {
REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
}
}
#ifdef __cplusplus
}
#endif

104
components/hal/esp32h2/include/hal/rtc_io_ll.h Normal file
View File

@ -0,0 +1,104 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in hal/readme.md
******************************************************************************/
#pragma once
#include "soc/lp_aon_struct.h"
#include "soc/pmu_struct.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTCIO_LL_GPIO_NUM_OFFSET 7 // rtcio 0-7 correspond to gpio 7-14
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
/**
* @brief Select the rtcio function.
*
* @note The RTC function must be selected before the pad analog function is enabled.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param func Select pin function.
*/
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_FUNC_RTC) {
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
} else if (func == RTCIO_FUNC_DIGITAL) {
// Clear the bit to use digital GPIO module
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask &= ~BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
}
}
/**
* Enable force hold function for an RTC IO pad.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
* This function is useful when going into light or deep sleep mode to prevent
* the pin configuration from changing.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_force_hold_enable(int rtcio_num)
{
LP_AON.gpio_hold0.gpio_hold0 |= BIT(rtcio_num + RTCIO_LL_GPIO_NUM_OFFSET);
}
/**
* Disable hold function on an RTC IO pad
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_force_hold_disable(int rtcio_num)
{
LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num + RTCIO_LL_GPIO_NUM_OFFSET);
}
/**
* Enable force hold function for all RTC IO pads
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
* This function is useful when going into light or deep sleep mode to prevent
* the pin configuration from changing.
*/
static inline void rtcio_ll_force_hold_all(void)
{
PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
}
/**
* Disable hold function fon all RTC IO pads
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
*/
static inline void rtcio_ll_force_unhold_all(void)
{
PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
}
#ifdef __cplusplus
}
#endif

16
components/hal/include/hal/rtc_io_hal.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -18,16 +18,18 @@
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_PIN_COUNT > 0
#include "hal/rtc_io_ll.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#include "hal/rtc_io_types.h"
#endif
#endif //SOC_RTCIO_PIN_COUNT > 0
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_PIN_COUNT > 0
/**
* Select the rtcio function.
*
@ -37,6 +39,7 @@ extern "C" {
*/
#define rtcio_hal_function_select(rtcio_num, func) rtcio_ll_function_select(rtcio_num, func)
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
/**
* Enable rtcio output.
*
@ -235,7 +238,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
#endif
#if SOC_RTCIO_HOLD_SUPPORTED || SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_HOLD_SUPPORTED && SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
/**
* Helper function to disconnect internal circuits from an RTC IO
@ -254,6 +257,8 @@ void rtcio_hal_isolate(int rtc_num);
#endif
#endif //SOC_RTCIO_PIN_COUNT > 0
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
#define gpio_hal_deepsleep_wakeup_enable(hal, gpio_num, intr_type) rtcio_hal_wakeup_enable(gpio_num, intr_type)
@ -283,7 +288,8 @@ void rtcio_hal_isolate(int rtc_num);
*/
#define rtcio_hal_clear_interrupt_status() rtcio_ll_clear_interrupt_status()
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
#ifdef __cplusplus
}
#endif

22
components/hal/rtc_io_hal.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -49,15 +49,6 @@ void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode)
}
}
void rtcio_hal_isolate(int rtcio_num)
{
rtcio_ll_pullup_disable(rtcio_num);
rtcio_ll_pulldown_disable(rtcio_num);
rtcio_ll_output_disable(rtcio_num);
rtcio_ll_input_disable(rtcio_num);
rtcio_ll_force_hold_enable(rtcio_num);
}
void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode)
{
switch (mode) {
@ -86,4 +77,15 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode)
}
}
#if SOC_RTCIO_HOLD_SUPPORTED
void rtcio_hal_isolate(int rtcio_num)
{
rtcio_ll_pullup_disable(rtcio_num);
rtcio_ll_pulldown_disable(rtcio_num);
rtcio_ll_output_disable(rtcio_num);
rtcio_ll_input_disable(rtcio_num);
rtcio_ll_force_hold_enable(rtcio_num);
}
#endif
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED

5
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -198,7 +198,10 @@
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 8
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
* so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
* when the pins are switched to RTC function.
*/
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1

2
components/soc/esp32c6/rtc_io_periph.c
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/rtc_periph.h"
#include "soc/rtc_io_periph.h"
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0

26
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -171,6 +171,10 @@ config SOC_LP_TIMER_SUPPORTED
bool
default y
config SOC_LP_AON_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED
bool
default y
@ -415,14 +419,10 @@ config SOC_GPIO_ETM_TASKS_PER_GROUP
int
default 8
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000000FFF807F
@ -435,6 +435,14 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 8
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
@ -731,10 +739,6 @@ config SOC_PARLIO_TRANS_BIT_ALIGN
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 0
config SOC_RSA_MAX_BIT_LEN
int
default 3072
@ -1079,6 +1083,10 @@ config SOC_PM_SUPPORT_BT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_EXT1_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y

32
components/soc/esp32h2/include/soc/rtc_io_channel.h Normal file
View File

@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO7_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 7
#define RTCIO_GPIO8_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 8
#define RTCIO_GPIO9_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 9
#define RTCIO_GPIO10_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 10
#define RTCIO_GPIO11_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 11
#define RTCIO_GPIO12_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 12
#define RTCIO_GPIO13_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 13
#define RTCIO_GPIO14_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 14

24
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -68,6 +68,7 @@
#define SOC_APM_SUPPORTED 1
#define SOC_PMU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
@ -181,14 +182,15 @@
#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
#define SOC_GPIO_ETM_TASKS_PER_GROUP 8
// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as deep-sleep wakeup pins)
// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins)
// Digital IOs have their own registers to control pullup/down/capability
// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO7~14 on ESP32H2 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// GPIO7~14 on ESP32H2 can support chip deep sleep wakeup through EXT1 wake up
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL
@ -198,6 +200,12 @@
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported
* for hold, wake & 32kHz crystal functions - via LP_AON registers */
#define SOC_RTCIO_PIN_COUNT (8U)
#define SOC_RTCIO_HOLD_SUPPORTED (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
@ -300,11 +308,6 @@
#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated LP_IO subsystem on ESP32-H2. LP functions are still supported
* for hold, wake & 32kHz crystal functions - via LP_AON registers */
#define SOC_RTCIO_PIN_COUNT (0U)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
@ -453,6 +456,7 @@
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_MODEM_PD (1) /*!<modem includes BLE and 15.4 */
#define SOC_PM_SUPPORT_XTAL32K_PD (1)

37
components/soc/esp32h2/rtc_io_periph.c Normal file
View File

@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/rtc_io_periph.h"
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-1,//GPIO0
-1,//GPIO1
-1,//GPIO2
-1,//GPIO3
-1,//GPIO4
-1,//GPIO5
-1,//GPIO6
RTCIO_GPIO7_CHANNEL,//GPIO7
RTCIO_GPIO8_CHANNEL,//GPIO8
RTCIO_GPIO9_CHANNEL,//GPIO9
RTCIO_GPIO10_CHANNEL,//GPIO10
RTCIO_GPIO11_CHANNEL,//GPIO11
RTCIO_GPIO12_CHANNEL,//GPIO12
RTCIO_GPIO13_CHANNEL,//GPIO13
RTCIO_GPIO14_CHANNEL,//GPIO14
-1,//GPIO15
-1,//GPIO16
-1,//GPIO17
-1,//GPIO18
-1,//GPIO19
-1,//GPIO20
-1,//GPIO21
-1,//GPIO22
-1,//GPIO23
-1,//GPIO24
-1,//GPIO25
-1,//GPIO26
-1,//GPIO27
};

7
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -247,7 +247,10 @@
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 22
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
* so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
* when the pins are switched to RTC function.
*/
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1

7
components/soc/esp32s3/include/soc/soc_caps.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -275,7 +275,10 @@
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 22
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
* so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
* when the pins are switched to RTC function.
*/
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1

12
components/soc/include/soc/rtc_io_periph.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,11 +11,13 @@
//include soc related (generated) definitions
#include "soc/soc_caps.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_PIN_COUNT > 0
#include "soc/rtc_io_channel.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#include "soc/rtc_io_reg.h"
#include "soc/rtc_io_struct.h"
#endif
#endif
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_struct.h"
@ -26,8 +28,8 @@ extern "C"
{
#endif
#if SOC_RTCIO_PIN_COUNT > 0
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
/**
* @brief Pin function information for a single RTCIO pad's.
*
@ -60,6 +62,7 @@ typedef struct {
* for external use.
*/
extern const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT];
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
/**
* @brief Provides a constant table to get rtc io number with gpio number
@ -68,8 +71,7 @@ extern const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT];
* for external use.
*/
extern const int rtc_io_num_map[SOC_GPIO_PIN_COUNT];
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#endif //SOC_RTCIO_PIN_COUNT > 0
#ifdef __cplusplus
}

25
docs/en/api-reference/system/sleep_modes.rst
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@ -73,7 +73,7 @@ RTC peripherals or RTC memories don't need to be powered on during sleep in this
:cpp:func:`esp_sleep_enable_touchpad_wakeup` function can be used to enable this wakeup source.
.. only:: SOC_PM_SUPPORT_EXT0_WAKEUP or SOC_PM_SUPPORT_EXT1_WAKEUP
.. only:: SOC_PM_SUPPORT_EXT0_WAKEUP
External Wakeup (ext0)
^^^^^^^^^^^^^^^^^^^^^^
@ -90,20 +90,39 @@ RTC peripherals or RTC memories don't need to be powered on during sleep in this
.. warning:: After waking up from sleep, the IO pad used for wakeup will be configured as RTC IO. Therefore, before using this pad as digital GPIO, users need to reconfigure it using :cpp:func:`rtc_gpio_deinit` function.
.. only:: SOC_PM_SUPPORT_EXT1_WAKEUP
External Wakeup (ext1)
^^^^^^^^^^^^^^^^^^^^^^
The RTC controller contains the logic to trigger wakeup using multiple RTC GPIOs. One of the following two logic functions can be used to trigger wakeup:
.. only:: esp32
- wake up if any of the selected pins is high (``ESP_EXT1_WAKEUP_ANY_HIGH``)
- wake up if all the selected pins are low (``ESP_EXT1_WAKEUP_ALL_LOW``)
This wakeup source is implemented by the RTC controller. As such, RTC peripherals and RTC memories can be powered down in this mode. However, if RTC peripherals are powered down, internal pullup and pulldown resistors will be disabled. To use internal pullup or pulldown resistors, request the RTC peripherals power domain to be kept on during sleep, and configure pullup/pulldown resistors using ``rtc_gpio_`` functions before entering sleep::
.. only:: esp32s2 or esp32s3 or esp32c6 or esp32h2
- wake up if any of the selected pins is high (``ESP_EXT1_WAKEUP_ANY_HIGH``)
- wake up if any of the selected pins is low (``ESP_EXT1_WAKEUP_ANY_LOW``)
This wakeup source is implemented by the RTC controller. As such, RTC peripherals and RTC memories can be powered down in this mode. However, if RTC peripherals are powered down, internal pullup and pulldown resistors will be disabled if we don't use the HOLD feature. To use internal pullup or pulldown resistors, request the RTC peripherals power domain to be kept on during sleep, and configure pullup/pulldown resistors using ``rtc_gpio_`` functions before entering sleep::
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_en(gpio_num);
If we turn off the ``RTC_PERIPH`` domain, we will use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep. HOLD feature will be acted on the pin internally before the system entering sleep, and this can further reduce power consumption::
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_en(gpio_num);
If certain chips lack the ``RTC_PERIPH`` domain, we can only use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep::
gpio_pullup_dis(gpio_num);
gpio_pulldown_en(gpio_num);
.. warning::
- To use the EXT1 wakeup, the IO pad(s) are configured as RTC IO. Therefore, before using these pads as digital GPIOs, users need to reconfigure them by calling the :cpp:func:`rtc_gpio_deinit` function.
@ -225,7 +244,7 @@ Configuring IOs
Some {IDF_TARGET_NAME} IOs have internal pullups or pulldowns, which are enabled by default. If an external circuit drives this pin in Deep-sleep mode, current consumption may increase due to current flowing through these pullups and pulldowns.
.. only:: SOC_RTCIO_HOLD_SUPPORTED
.. only:: SOC_RTCIO_HOLD_SUPPORTED and SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
To isolate a pin to prevent extra current draw, call :cpp:func:`rtc_gpio_isolate` function.

25
docs/zh_CN/api-reference/system/sleep_modes.rst
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@ -73,7 +73,7 @@ RTC 控制器中内嵌定时器，可用于在预定义的时间到达后唤醒
可调用 :cpp:func:`esp_sleep_enable_touchpad_wakeup` 函数来启用该唤醒源。
.. only:: SOC_PM_SUPPORT_EXT0_WAKEUP or SOC_PM_SUPPORT_EXT1_WAKEUP
.. only:: SOC_PM_SUPPORT_EXT0_WAKEUP
外部唤醒 (ext0)
^^^^^^^^^^^^^^^^^^^^^^
@ -90,20 +90,39 @@ RTC 控制器中内嵌定时器，可用于在预定义的时间到达后唤醒
.. warning:: 从睡眠模式中唤醒后，用于唤醒的 IO pad 将被配置为 RTC IO。因此，在将该 pad 用作数字 GPIO 之前，请调用 :cpp:func:`rtc_gpio_deinit` 函数对其进行重新配置。
.. only:: SOC_PM_SUPPORT_EXT1_WAKEUP
外部唤醒 (ext1)
^^^^^^^^^^^^^^^^^^^^^^
RTC 控制器中包含使用多个 RTC GPIO 触发唤醒的逻辑。您可以从以下两个逻辑函数中选择其一，用于触发唤醒：
.. only:: esp32
- 当任意一个所选管脚为高电平时唤醒(ESP_EXT1_WAKEUP_ANY_HIGH)
- 当所有所选管脚为低电平时唤醒 (ESP_EXT1_WAKEUP_ALL_LOW)
此唤醒源由 RTC 控制器实现。这种模式下的 RTC 外设和 RTC 内存可以被断电。但如果 RTC 外设被断电，内部上拉和下拉电阻将被禁用。想要使用内部上拉和下拉电阻，需要 RTC 外设电源域在睡眠期间保持开启，并在进入睡眠前使用函数 ``rtc_gpio_`` 配置上拉或下拉电阻。
.. only:: esp32s2 or esp32s3 or esp32c6 or esp32h2
- 当任意一个所选管脚为高电平时唤醒(ESP_EXT1_WAKEUP_ANY_HIGH)
- 当任意一个所选管脚为低电平时唤醒(ESP_EXT1_WAKEUP_ANY_LOW)
此唤醒源由 RTC 控制器实现。这种模式下的 RTC 外设和 RTC 内存可以被断电。然而，如果RTC外设被断电，如果我们不使用 HOLD 功能，内部上拉和下拉电阻将被禁用。想要使用内部上拉和下拉电阻，需要 RTC 外设电源域在睡眠期间保持开启，并在进入睡眠前使用函数 ``rtc_gpio_`` 配置上拉或下拉电阻。
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
gpio_pullup_dis(gpio_num);
gpio_pulldown_en(gpio_num);
如果我们关闭 ``RTC_PERIPH`` 域，我们将使用 HOLD 功能在睡眠期间维持引脚上的上拉和下拉电阻。所选管脚的 HOLD 功能会在系统真正进入睡眠前被开启，这有助于进一步减小睡眠时的功耗。
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_en(gpio_num);
如果某些芯片缺少 ``RTC_PERIPH`` 域，我们只能使用 HOLD 功能来在睡眠期间维持引脚上的上拉和下拉电阻。
gpio_pullup_dis(gpio_num);
gpio_pulldown_en(gpio_num);
.. warning::
- 使用 EXT1 唤醒源时，用于唤醒的 IO pad 将被配置为 RTC IO。因此，在将该 pad 用作数字 GPIO 之前，请调用 :cpp:func:`rtc_gpio_deinit` 函数对其进行重新配置。
@ -225,7 +244,7 @@ Flash 断电
一些 {IDF_TARGET_NAME} IO 在默认情况下启用内部上拉或下拉电阻。如果这些管脚在 Deep-sleep 模式下中受外部电路驱动，电流流经这些上下拉电阻时，可能会增加电流消耗。
.. only:: SOC_RTCIO_HOLD_SUPPORTED
.. only:: SOC_RTCIO_HOLD_SUPPORTED and SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
想要隔离这些管脚以避免额外的电流消耗，请调用 :cpp:func:`rtc_gpio_isolate` 函数。

2
examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c
View File

@ -221,7 +221,7 @@ static int deep_sleep(int argc, char **argv)
#endif
}
#if SOC_RTCIO_HOLD_SUPPORTED
#if CONFIG_IDF_TARGET_ESP32
rtc_gpio_isolate(GPIO_NUM_12);
#endif
esp_deep_sleep_start();

8
examples/system/.build-test-rules.yml
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@ -32,15 +32,9 @@ examples/system/console/basic:
temporary: true
reason: lack of runners
examples/system/deep_sleep:
disable:
- if: IDF_TARGET in ["esp32h2"]
temporary: true
reason: target(s) not supported yet # IDF-6268
examples/system/deep_sleep_wake_stub:
disable:
- if: IDF_TARGET in ["esp32c2", "esp32h2"]
- if: IDF_TARGET in ["esp32c2"]
temporary: true
reason: target(s) is not supported yet

4
examples/system/deep_sleep/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# Deep Sleep Example

202
examples/system/deep_sleep/main/Kconfig.projbuild
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@ -32,20 +32,192 @@ menu "Example Configuration"
floating pins. When triggering a wake up, connect one or both of the pins to HIGH. Note that floating
pins may trigger a wake up.
config EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
bool "Use internal pull-up/downs for EXT1 wakeup source"
default n
depends on EXAMPLE_EXT1_WAKEUP
help
When using EXT1 wakeup source without external pull-up/downs, you may want to make use of the internal
ones.
menu "EXT1 wakeup configuration"
visible if EXAMPLE_EXT1_WAKEUP
However, the RTC IO reside in the RTC Periph power domain. Enable this option to force that power domain
ON during deep sleep. Note that this will increase some power comsumption, so it's still suggested to use
external ones instead.
config EXAMPLE_EXT1_WAKEUP_PIN_1
int "Enable wakeup from PIN_1"
depends on !IDF_TARGET_ESP32
default 2 if !IDF_TARGET_ESP32H2
default 10 if IDF_TARGET_ESP32H2
range 0 7 if IDF_TARGET_ESP32C6
range 7 14 if IDF_TARGET_ESP32H2
range 0 21 if IDF_TARGET_ESP32S2
range 0 21 if IDF_TARGET_ESP32S3
EXT0 wakeup source resides in the same power domain as RTCIO (RTC Periph), so internal pull-up/downs are
always available. There's no need to explicitly force it on for EXT0.
choice EXAMPLE_EXT1_WAKEUP_PIN_1_SEL
prompt "Enable wakeup from PIN_1"
default EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_2
depends on IDF_TARGET_ESP32
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_0
bool "GPIO 0"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_2
bool "GPIO 2"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_4
bool "GPIO 4"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_12
bool "GPIO 12"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_13
bool "GPIO 13"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_14
bool "GPIO 14"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_15
bool "GPIO 15"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_25
bool "GPIO 25"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_26
bool "GPIO 26"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_27
bool "GPIO 27"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_32
bool "GPIO 32"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_33
bool "GPIO 33"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_34
bool "GPIO 34"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_35
bool "GPIO 35"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_36
bool "GPIO 36"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_37
bool "GPIO 37"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_38
bool "GPIO 38"
config EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_39
bool "GPIO 39"
endchoice
config EXAMPLE_EXT1_WAKEUP_PIN_1
int
depends on IDF_TARGET_ESP32
default 0 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_0
default 2 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_2
default 4 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_4
default 12 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_12
default 13 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_13
default 14 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_14
default 15 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_15
default 25 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_25
default 26 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_26
default 27 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_27
default 32 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_32
default 33 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_33
default 34 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_34
default 35 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_35
default 36 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_36
default 37 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_37
default 38 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_38
default 39 if EXAMPLE_EXT1_WAKEUP_PIN_1_SEL_39
config EXAMPLE_EXT1_WAKEUP_PIN_2
int "Enable wakeup from PIN_2"
depends on !IDF_TARGET_ESP32
default 4 if !IDF_TARGET_ESP32H2
default 11 if IDF_TARGET_ESP32H2
range 0 7 if IDF_TARGET_ESP32C6
range 7 14 if IDF_TARGET_ESP32H2
range 0 21 if IDF_TARGET_ESP32S2
range 0 21 if IDF_TARGET_ESP32S3
choice EXAMPLE_EXT1_WAKEUP_PIN_2_SEL
prompt "Enable wakeup from PIN_2"
default EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_4
depends on IDF_TARGET_ESP32
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_0
bool "GPIO 0"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_2
bool "GPIO 2"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_4
bool "GPIO 4"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_12
bool "GPIO 12"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_13
bool "GPIO 13"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_14
bool "GPIO 14"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_15
bool "GPIO 15"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_25
bool "GPIO 25"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_26
bool "GPIO 26"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_27
bool "GPIO 27"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_32
bool "GPIO 32"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_33
bool "GPIO 33"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_34
bool "GPIO 34"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_35
bool "GPIO 35"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_36
bool "GPIO 36"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_37
bool "GPIO 37"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_38
bool "GPIO 38"
config EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_39
bool "GPIO 39"
endchoice
config EXAMPLE_EXT1_WAKEUP_PIN_2
int
depends on IDF_TARGET_ESP32
default 0 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_0
default 2 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_2
default 4 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_4
default 12 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_12
default 13 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_13
default 14 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_14
default 15 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_15
default 25 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_25
default 26 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_26
default 27 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_27
default 32 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_32
default 33 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_33
default 34 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_34
default 35 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_35
default 36 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_36
default 37 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_37
default 38 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_38
default 39 if EXAMPLE_EXT1_WAKEUP_PIN_2_SEL_39
choice EXAMPLE_EXT1_WAKEUP_MODE_SEL
prompt "Select wakeup mode from EXT1"
default ESP_EXT1_WAKEUP_ANY_HIGH
config ESP_EXT1_WAKEUP_ANY_LOW
bool "GPIO any low level"
depends on !IDF_TARGET_ESP32
config ESP_EXT1_WAKEUP_ALL_LOW
bool "GPIO all low level"
depends on IDF_TARGET_ESP32
config ESP_EXT1_WAKEUP_ANY_HIGH
bool "GPIO any high level"
endchoice
config EXAMPLE_EXT1_WAKEUP_MODE
int
default 0 if ESP_EXT1_WAKEUP_ANY_LOW
default 0 if ESP_EXT1_WAKEUP_ALL_LOW
default 1 if ESP_EXT1_WAKEUP_ANY_HIGH
config EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
bool "Use internal pull-up/downs for EXT1 wakeup source"
default n
depends on EXAMPLE_EXT1_WAKEUP
help
When using EXT1 wakeup source without external pull-up/downs, you may want to make use of
the internal ones.
if we turn off the RTC_PERIPH domain or if certain chips lack the RTC_PERIPH domain,
we will use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep.
but if we turn on the RTC_PERIPH domain, we don not need to use HOLD feature and this will
increase some power comsumption.
EXT0 wakeup source resides in the same power domain as RTCIO (RTC Periph), so internal
pull-up/downs are always available. There's no need to explicitly force it on for EXT0.
endmenu
config EXAMPLE_GPIO_WAKEUP
bool "Enable wakeup from GPIO"
@ -60,11 +232,9 @@ menu "Example Configuration"
config EXAMPLE_GPIO_WAKEUP_PIN
int "Enable wakeup from GPIO"
default 0 if !IDF_TARGET_ESP32H2
default 7 if IDF_TARGET_ESP32H2
default 0
range 0 7 if IDF_TARGET_ESP32C6
range 7 14 if IDF_TARGET_ESP32H2
range 0 5 if !IDF_TARGET_ESP32C6 && !IDF_TARGET_ESP32H2
range 0 5 if !IDF_TARGET_ESP32C6
config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL
bool "Enable GPIO high-level wakeup"

45
examples/system/deep_sleep/main/ext_wakeup.c
View File

@ -9,6 +9,7 @@
#include "sdkconfig.h"
#include "driver/rtc_io.h"
#if CONFIG_EXAMPLE_EXT0_WAKEUP
#if CONFIG_IDF_TARGET_ESP32
const int ext_wakeup_pin_0 = 25;
@ -32,24 +33,46 @@ void example_deep_sleep_register_ext0_wakeup(void)
#if CONFIG_EXAMPLE_EXT1_WAKEUP
void example_deep_sleep_register_ext1_wakeup(void)
{
const int ext_wakeup_pin_1 = 2;
const int ext_wakeup_pin_1 = CONFIG_EXAMPLE_EXT1_WAKEUP_PIN_1;
const int ext_wakeup_pin_2 = CONFIG_EXAMPLE_EXT1_WAKEUP_PIN_2;
const uint64_t ext_wakeup_pin_1_mask = 1ULL << ext_wakeup_pin_1;
const int ext_wakeup_pin_2 = 4;
const uint64_t ext_wakeup_pin_2_mask = 1ULL << ext_wakeup_pin_2;
printf("Enabling EXT1 wakeup on pins GPIO%d, GPIO%d\n", ext_wakeup_pin_1, ext_wakeup_pin_2);
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask, ESP_EXT1_WAKEUP_ANY_HIGH));
const esp_sleep_ext1_wakeup_mode_t ext_wakeup_mode = CONFIG_EXAMPLE_EXT1_WAKEUP_MODE;
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask, ext_wakeup_mode));
/* If there are no external pull-up/downs, tie wakeup pins to inactive level with internal pull-up/downs via RTC IO
* during deepsleep. However, RTC IO relies on the RTC_PERIPH power domain. Keeping this power domain on will
* increase some power comsumption. */
* increase some power comsumption. However, if we turn off the RTC_PERIPH domain or if certain chips lack the RTC_PERIPH
* domain, we will use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep.*/
#if CONFIG_EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON));
ESP_ERROR_CHECK(rtc_gpio_pullup_dis(ext_wakeup_pin_1));
ESP_ERROR_CHECK(rtc_gpio_pulldown_en(ext_wakeup_pin_1));
ESP_ERROR_CHECK(rtc_gpio_pullup_dis(ext_wakeup_pin_2));
ESP_ERROR_CHECK(rtc_gpio_pulldown_en(ext_wakeup_pin_2));
#endif //CONFIG_EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (ext_wakeup_mode) {
ESP_ERROR_CHECK(rtc_gpio_pullup_dis(ext_wakeup_pin_1));
ESP_ERROR_CHECK(rtc_gpio_pulldown_en(ext_wakeup_pin_1));
ESP_ERROR_CHECK(rtc_gpio_pullup_dis(ext_wakeup_pin_2));
ESP_ERROR_CHECK(rtc_gpio_pulldown_en(ext_wakeup_pin_2));
} else {
ESP_ERROR_CHECK(rtc_gpio_pulldown_dis(ext_wakeup_pin_1));
ESP_ERROR_CHECK(rtc_gpio_pullup_en(ext_wakeup_pin_1));
ESP_ERROR_CHECK(rtc_gpio_pulldown_dis(ext_wakeup_pin_2));
ESP_ERROR_CHECK(rtc_gpio_pullup_en(ext_wakeup_pin_2));
}
#else
if (ext_wakeup_mode) {
ESP_ERROR_CHECK(gpio_pullup_dis(ext_wakeup_pin_1));
ESP_ERROR_CHECK(gpio_pulldown_en(ext_wakeup_pin_1));
ESP_ERROR_CHECK(gpio_pullup_dis(ext_wakeup_pin_2));
ESP_ERROR_CHECK(gpio_pulldown_en(ext_wakeup_pin_2));
} else {
ESP_ERROR_CHECK(gpio_pulldown_dis(ext_wakeup_pin_1));
ESP_ERROR_CHECK(gpio_pullup_en(ext_wakeup_pin_1));
ESP_ERROR_CHECK(gpio_pulldown_dis(ext_wakeup_pin_2));
ESP_ERROR_CHECK(gpio_pullup_en(ext_wakeup_pin_2));
}
#endif
#endif // CONFIG_EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
}
#endif // CONFIG_EXAMPLE_EXT1_WAKEUP

15
examples/system/deep_sleep/pytest_deep_sleep.py
View File

@ -12,7 +12,18 @@ touch_wake_up_support = ['esp32', 'esp32s2']
CONFIGS = [
pytest.param('esp32_singlecore', marks=[pytest.mark.esp32]),
pytest.param('basic', marks=[pytest.mark.esp32, pytest.mark.esp32s2, pytest.mark.esp32s3, pytest.mark.esp32c3, pytest.mark.esp32c6, pytest.mark.esp32c2]),
pytest.param(
'basic',
marks=[
pytest.mark.esp32,
pytest.mark.esp32s2,
pytest.mark.esp32s3,
pytest.mark.esp32c3,
pytest.mark.esp32c6,
pytest.mark.esp32h2,
pytest.mark.esp32c2,
],
),
]
@ -23,7 +34,7 @@ def test_deep_sleep(dut: Dut) -> None:
def expect_enable_deep_sleep_touch() -> None:
# different targets configure different wake pin(s)
wake_pads = {
'esp32': [8,9],
'esp32': [8, 9],
'esp32s2': [9],
}[dut.target]

4
examples/system/deep_sleep_wake_stub/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
# Deep Sleep Wake Stub Example

1
examples/system/deep_sleep_wake_stub/pytest_deep_sleep_wake_stub.py
View File

@ -13,6 +13,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32s3
@pytest.mark.esp32c3
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.generic
@pytest.mark.parametrize('config', ['default',], indirect=True)
def test_deep_sleep_wake_stub(config: str, dut: Dut) -> None: