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407 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
78165c541e Merge branch 'bugfix/bootloader_uart_custom_gpio' into 'master' 
bootloader: fixed the issue custom_uart_gpio doesn't take effect

Closes IDF-4606

See merge request espressif/esp-idf!16910
 2022-03-02 02:35:14 +08:00
songruojing
d4334cc109 uart: fixed incorrect channel number on ESP32S2, S3 and C3 2022-03-01 18:21:27 +08:00
KonstantinKondrashov
7d097511fa soc: Fix efuse_hal_get_chip_revision for esp32 2022-03-01 16:55:43 +08:00
Kevin (Lao Kaiyao)
cc1d89ebba Merge branch 'feature/i2c_support_on_esp8684_esp32h2' into 'master' 
i2c: support i2c on esp32c2 and esp32h2

Closes IDF-3918

See merge request espressif/esp-idf!16444
 2022-02-28 13:59:02 +08:00
Konstantin Kondrashov
44e5ac2c59 Merge branch 'feature/efuse_hal' into 'master' 
hal: Adds efuse hal layer

See merge request espressif/esp-idf!16354
 2022-02-28 13:38:43 +08:00
KonstantinKondrashov
9605f3eb1a soc: Adds efuse hal 
Replaced eFuse ROM funcs with hal layer
 2022-02-24 22:20:09 +08:00
laokaiyao
7da023ceae i2c: support esp32c2 2022-02-23 15:19:37 +08:00
morris
116197040f i2s: update copyright 2022-02-21 21:28:48 +08:00
Zim Kalinowski
67f51a4ce5 Merge branch 'bugfix/riscv_i2c_description' into 'master' 
i2c: fix the controller count in the header description

Closes IDFGH-6476

See merge request espressif/esp-idf!16718
 2022-01-26 03:13:07 +00:00
Omar Chebib
bb730292d4 i2c: fix the controller count in the header description 
Closes https://github.com/espressif/esp-idf/issues/8133
 2022-01-13 18:25:41 +08:00
Armando
6a74cb695d spi: support spi on 8684 2022-01-12 11:30:29 +08:00
morris
24acdf23ee soc: move peripheral base address into reg_base.h 2022-01-06 21:43:12 +08:00
morris
8cdcb4e291 rmt: move RMT item definition from soc to driver 2022-01-06 21:43:12 +08:00
laokaiyao
4f28b33bbc apll: add lock for apll 2021-12-29 10:13:13 +08:00
laokaiyao
af4e448928 i2s: impove the clock division calculation 
Reported from: https://esp32.com/viewtopic.php?f=25&t=24542&p=87595#p87595
 2021-12-29 10:13:13 +08:00
morris
b170aba93a timer: fix wrong kconfig soc caps 2021-12-23 11:39:32 +08:00
Marius Vikhammer
82325f6037 docs: update docs to be able to build with esp8684 2021-12-20 10:32:49 +08:00
Armando
4dc0d6b2fe adc: support adc dma driver on all chips 2021-12-16 00:19:15 +00:00
Cao Sen Miao
e81841318f CI: Enable ESP8684 build stage CI on master 2021-12-13 19:18:47 +08:00
Marius Vikhammer
c6d60615c6 build-system: include soc_caps defines into kconfig 
Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into
a format that can be included in kconfig.
 2021-12-06 12:37:07 +08:00
Cao Sen Miao
ce1ee3d8ae psram: add ESP32-D0WD-R2-V3 support 2021-11-12 13:52:24 +08:00
Omar Chebib
aa2ca7dd94 LEDC: improved support for ESP32-C3 and refactored divisor calculation 
As ESP32C3 does not have support for REF_TICK source clock, it is now not
possible to select it anymore.
Auto cfg clock has been improved for all boards.
 2021-11-11 12:21:15 +08:00
morris
83d16aa00c gdma: support IRAM interrupt 2021-11-08 16:14:51 +08:00
Cao Sen Miao
36f6d16b8d ESP8684: add soc, riscv, newlib support 2021-11-06 17:33:44 +08:00
Wei Tian Hua
347e04cf73 Merge branch 'doc/make_classic_bt_API_ref_only_for_esp32' into 'master' 
Doc/Make Classic BT related document links only visible for ESP32

Closes IDFGH-5008, IDFGH-6022, and AUD-3378

See merge request espressif/esp-idf!15635
 2021-10-29 02:27:24 +00:00
weitianhua
0ea06fa336 Remove dummy defines of Classic BT 2021-10-28 19:26:46 +08:00
weitianhua
64aa94d823 Make Classic BT related document links only visible for ESP32 2021-10-27 15:28:47 +08:00
Alexey Gerenkov
111ba5bbe6 trax: Adds ESP32-S3 support 2021-10-22 23:36:28 +03:00
morris
e2275b1f63 gptimer: clean up hal and ll for driver-ng 2021-10-20 18:40:08 +08:00
laokaiyao
f4705f8eb4 touch sensor: update copyright notice 2021-10-08 11:45:57 +08:00
laokaiyao
a1cadba191 touch_sensor: apply general check 2021-10-08 11:32:12 +08:00
fuzhibo
589646a31e update touch with review advice 2021-10-08 10:39:46 +08:00
fuzhibo
057b9d61b5 driver(touch): support touch sensor for esp32s3 platform 2021-10-08 10:39:46 +08:00
Jiang Jiang Jian
f5ae8b0533 Merge branch 'feature/ledc_use_rtc8m_or_xtal_lightsleep' into 'master' 
support RTC8M and XTAL power domain in light sleep mode

Closes IDF-3419

See merge request espressif/esp-idf!15152
 2021-09-27 04:02:29 +00:00
Li Shuai
f5b39a7cde esp_hw_support: No voltage drop during light sleep to ensure stable output clock of rtc8m oscillator 2021-09-16 14:40:46 +08:00
Armando
c45c6f52f1 adc: support adc efuse-based calibration on esp32s3 2021-09-14 11:42:50 +08:00
Li Shuai
e44ead5356 Power Management: add RTC8M power domain to control whether internal 8m oscillator is powered down during sleep 2021-09-13 17:36:54 +08:00
morris
9d97d01679 Merge branch 'bugfix/mcpwm_cpp_reserved_word' into 'master' 
bugfix/mcpwm: rename invalid keyword 'operator'

Closes IDFGH-5840

See merge request espressif/esp-idf!15159
 2021-09-13 03:10:04 +00:00
SalimTerryLi
d9f4ae02f1
mcpwm: rename keyword 'operator' which is not valid in cpp 
Closes https://github.com/espressif/esp-idf/issues/7542
 2021-09-10 12:41:42 +08:00
baohongde
006a10b050 components/doc: Update doc about high-level interrupt 
some bugfix.
 2021-09-09 20:40:09 +08:00
baohongde
6d63fe06fa components/os: add config option to choose system check intterupt level. 2021-09-09 11:29:12 +08:00
baohongde
d1db2df316 components/bt: High level interrupt in bluetooth 
components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt

components/os: high level interrupt(5)

components/os: hli_api: meta queue: fix out of bounds access, check for overflow

components/os: hli: don't spill registers, instead save them to a separate region

Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).

Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.

components/bt: using high level interrupt in lc

components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`

components/bt: optimize code structure

components/os: Modify the BT assert process to adapt to coredump and HLI

components/os: Disable exception mode after saving special registers

To store some registers first, avoid stuck due to live lock after disabling exception mode

components/os: using dport instead of AHB in BT to fix live lock

components/bt: Fix hli queue send error

components/bt: Fix CI fail

# Conflicts:
#	components/bt/CMakeLists.txt
#	components/bt/component.mk
#	components/bt/controller/bt.c
#	components/bt/controller/lib
#	components/esp_common/src/int_wdt.c
#	components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
#	components/soc/esp32/include/soc/soc.h
 2021-09-09 11:29:06 +08:00
laokaiyao
c5afd7ce34 i2s: fix write failure on ESP32 in 32bit slave mode 2021-09-03 17:36:44 +08:00
SalimTerryLi
874a720286
soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one 
update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
 2021-08-30 13:50:58 +08:00
Michael (XIAO Xufeng)
375145ecdb Merge branch 'feature/mcpwm_bldc_hall_example' into 'master' 
mcpwm: bldc hall example

Closes IDF-3648

See merge request espressif/esp-idf!14578
 2021-08-26 08:28:27 +00:00
Song Ruo Jing
fe5c87cb3c Merge branch 'bugfix/enable_gpio_20' into 'master' 
gpio: Enable IO20 on ESP32

Closes IDFGH-5140

See merge request espressif/esp-idf!14881
 2021-08-25 07:25:37 +00:00
morris
3bfd8f5d5f mcpwm: update register file according to TRM 2021-08-24 15:38:46 +08:00
Alberto García Hierro
6deaefde69 Enable IO20 on ESP32 
Some newer ESP32 variants (like ESP32-PICO-V3 and ESP32-PICO-MINI-02)
do implement this pin and it can be used as a normal GPIO.

Fixes #6016
Fixes #6837

Closes https://github.com/espressif/esp-idf/pull/6918
 2021-08-20 14:05:38 +08:00
morris
bb87fd8f08 Merge branch 'refactor/pcnt_driver_esp32s3' into 'master' 
pcnt: soc update and hal refactor

See merge request espressif/esp-idf!14698
 2021-08-20 04:23:15 +00:00
morris
1656cee69d i2s: correct soc info 
1. remove non-exist I2S instance
2. update soc_caps.h, i2s_ll.h
 2021-08-10 21:06:59 +08:00
suda-morris
9920271c21 pcnt: update pcnt soc data for all targets 2021-08-10 17:19:21 +08:00
Wang Meng Yang
8652b1d576 Merge branch 'bugfix/btdm_esp32_ble_white_list_connection_fail' into 'master' 
Fixed ESP32 BLE can't resolve the peer address when enable white list

See merge request espressif/esp-idf!14348
 2021-08-09 06:46:08 +00:00
Michael (XIAO Xufeng)
947980ecac Merge branch 'bugfix/uart_set_pin_use_iomux' into 'master' 
uart: uart_set_pin function will now use IOMUX whenever possible

Closes IDF-3183

See merge request espressif/esp-idf!14318
 2021-08-05 04:17:29 +00:00
xiewenxiang
1cc0f6aac5 Fixed ESP32 BLE can't resolve the peer address when enable white list 2021-08-04 22:00:38 +08:00
Omar Chebib
779e7400b0 uart: uart_set_pin function will now use IOMUX whenever possible 
By using IOMUX instead of GPIO Matrix for UART, it is now possible
on ESP32 boards to use the UART as a wake up source even if it is
not used as a console.
For other boards where this issue was not present, using IOMUX has
the advantage to be faster than using GPIO matrix, so a highest
baudrate can be used
 2021-08-04 12:48:30 +08:00
laokaiyao
d51b85989b doc/i2s: update i2s programming guide on s3 & c3 2021-08-04 10:20:03 +08:00
houwenxiang
2f1247e1c4 driver: support I2S on ESP32-S3 & ESP32-C3 
1. refactor I2S driver.
  2. support TDM mode for esp2s3 & esp32c3.
 2021-08-04 10:20:03 +08:00
Konstantin Kondrashov
4972605b16 esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt 2021-08-03 14:35:29 +08:00
morris
88c87bfe56 mcpwm: update hal and soc naming 2021-07-26 22:32:45 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Angus Gratton
0f1b24891b Merge branch 'bugfix/esp32_u4wdh_quad_io' into 'master' 
bootloader: Fix selection of Quad I/O modes on ESP32-U4WDH chip

Closes IDFGH-4353

See merge request espressif/esp-idf!13111
 2021-06-07 04:50:54 +00:00
Angus Gratton
dc6b950257 doc: Add performance guides for execuion speed, binary size, RAM usage 
Closes https://github.com/espressif/esp-idf/issues/7007
Closes https://github.com/espressif/esp-idf/issues/6715
Closes https://github.com/espressif/esp-idf/issues/3781
Closes https://github.com/espressif/esp-idf/issues/2566
 2021-06-03 13:55:34 +10:00
Ivan Grokhotkov
17c65dad27 soc: add esp32s3 sdmmc support 
* sync the latest struct header file from ESP32
* add soc_caps.h macros to distinguish between IO MUX and GPIO Matrix
  support in SDMMC on different chips.
* store GPIO matrix signal numbers in sdmmc_slot_info_t
 2021-05-10 23:21:27 +02:00
Cao Sen Miao
0d81edb174 spi_flash: refactoring flash encryption into new api 2021-04-25 17:09:25 +08:00
Ivan Grokhotkov
ea7d020f20 Merge branch 'feature/ubsan' into 'master' 
system: add option to enable undefined behavior sanitizer (UBSAN)

Closes IDF-166 and IDF-1824

See merge request espressif/esp-idf!11318
 2021-04-23 09:27:42 +00:00
Ivan Grokhotkov
da90775d98 hal: mpu: fix signed overflow error 2021-04-22 23:33:47 +02:00
Darian Leung
54eb152a96 TWAI: Simply caps and remove unused caps 2021-04-16 18:36:18 +08:00
Angus Gratton
268b23db96 bootloader: Fix selection of Quad I/O modes on ESP32-U4WDH chip 
Closes https://github.com/espressif/esp-idf/issues/6191
 2021-04-12 18:49:17 +10:00
morris
75dfd970b4 dac: added DAC support macro 
Remove DAC support on ESP32-S3
 2021-04-12 12:04:46 +08:00
Armando
9b9ea71ff9 spi: remove HSPI macro on esp32c3 and esp32s3 2021-04-06 13:42:49 +08:00
Michael (XIAO Xufeng)
3a90d51831 Merge branch 'refactor/using_isr_callback_in_timer_example' into 'master' 
TIMG: clean up timer example and add example test

Closes IDF-2722, IDF-2766, and IDF-2347

See merge request espressif/esp-idf!12218
 2021-03-22 06:36:32 +00:00
morris
f5ca47c0fc mcpwm: rename macros related to soc capbility 2021-03-16 21:53:59 +08:00
morris
5a520cacf1 timer_group: correct timer_ll_set_divider 2021-03-16 17:56:37 +08:00
Angus Gratton
fd164b82b6 Merge branch 'refactor/move_from_xtensa' into 'master' 
Movements from xtensa

Closes IDF-2164

See merge request espressif/esp-idf!10556
 2021-03-11 00:24:25 +00:00
Renz Bagaporo
1efdcd69d9 xtensa: move out trax 2021-02-26 19:45:48 +08:00
Xia Xiaotian
f53c0c5b87 esp_wifi: store PHY digital registers before disabling PHY and load 
them after enabling PHY
 2021-02-26 11:29:50 +08:00
morris
7b37158ede rmt: distinguish group and channel in HAL layer 2021-02-25 12:42:23 +08:00
morris
6dc7f95342 mcpwm: fix wrong meta information 2021-02-22 20:23:35 +08:00
Angus Gratton
2ec04b57de soc esp32: Removes parentheses from RTC_MEM_xyz macros that expand directly to single numbers 
Not necessary in these cases, and prevents parens from expanding into the
assembly code such as added in 562ab01046  -
a pattern which is accepted by GCC assembler but illegal syntax for LLVM assembler.

As reported https://github.com/espressif/llvm-project/issues/35#issuecomment-726853574
 2021-02-08 10:08:01 +11:00
Michael (XIAO Xufeng)
d7d1dee208 system: reset dma when soft reset 2021-01-25 04:51:40 +00:00
Angus Gratton
fe8a891de9 Merge branch 'feature/support_esp32c3_master_cmake_secure_boot' into 'master' 
bootloader/esp32c3: Support secure boot

Closes IDF-2115

See merge request espressif/esp-idf!11797
 2021-01-21 08:42:49 +08:00
KonstantinKondrashov
88c5fe49b8 soc: Adds a soc_caps define for all chips to define the number of boot key digests 2021-01-19 20:51:13 +08:00
Li Shuai
aa7fd175b9 light sleep: light sleep support for esp32c3 2021-01-19 14:50:58 +08:00
ninh
27aa6c289f components/pm: Add slp gpio configure workaround 2021-01-15 15:34:45 +08:00
morris
e6d23a35ec gdma: dynamic alloc DMA channels 2021-01-13 10:52:27 +08:00
ninh
dc7bdb9857 adjust lightsleep overhead time and cali slowclk 2021-01-06 03:40:28 +00:00
Marius Vikhammer
eb788deb03 esp_hw_support: merge C3 changes to master 
Merge RTC related C3 changes to master
 2020-12-30 12:20:41 +08:00
Angus Gratton
c3ba995f2c Merge branch 'ci/ccomp_performance_tests' into 'master' 
unit_test: Refactor all performance tests that rely on cache compensated timer

See merge request espressif/esp-idf!11709
 2020-12-24 13:44:52 +08:00
Angus Gratton
fa892eb017 soc: Explain units for rtc_clk_cal() function, fix typo 2020-12-23 09:53:24 +11:00
Cao Sen Miao
e338a2e3df rtc: add function to en/disable the rtc clock 2020-12-23 09:53:24 +11:00
Marius Vikhammer
0a95151a75 unit_test: Refactor all performance tests that rely on cache compensated timer 
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.

This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
 2020-12-22 18:56:24 +11:00
Cao Sen Miao
0736c91d68 soc: Remove cache constants from soc.h 2020-12-17 15:34:13 +11:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer 
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
 2020-12-10 09:04:47 +00:00
Angus Gratton
c29d93986d soc: Add initial ESP32-C3 support 
From internal commit 7761d6e8
 2020-11-30 11:12:56 +11:00
Armando
fb8b905539 uart: add uart support on esp32s3 2020-11-24 19:12:51 +08:00
morris
c5fe158929 doc: fix wrong register description regarding to ethernet SMI 2020-11-16 13:30:49 +08:00
Michael (XIAO Xufeng)
14944b181e Merge branch 'fix/soc_caps_spi_dummy_output_esp32' into 'master' 
soc_caps.h: remove spi cap that is defined to 0

See merge request espressif/esp-idf!11203
 2020-11-16 10:39:27 +08:00
Michael (XIAO Xufeng)
099fca515d Merge branch 'bugfix/move_crypto_caps' into 'master' 
SHA/RSA: moved all caps to soc_caps.h

Closes IDF-2300

See merge request espressif/esp-idf!11032
 2020-11-13 11:06:44 +08:00
Angus Gratton
935e4b4d62 Merge branch 'feature/riscv_arch' into 'master' 
Add RISC-V support

Closes IDF-2359

See merge request espressif/esp-idf!11140
 2020-11-13 07:50:31 +08:00
Angus Gratton
420aef1ffe Updates for riscv support 
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
 2020-11-13 07:49:11 +11:00