The files updated according to code review discussions.
In the sleep_modes.c removed immidiate disable of ULP mode and leave just trigger deactivation.
The esp_sleep.h is updated to have the same defines for source as esp_sleep_wakeup_cause_t.
Updated documentation in sleep_modes.rst file to include cross references and address esp_sleep_wakeup_cause_t type.
The get_time_ms() is updated to explicitly use fabs(dt) instead of abs(dt) in test_sleep.c.
Some other minor changes in test_sleep.c unit test.
(TW#18952)
Closes https://github.com/espressif/esp-idf/issues/1677
It is not possible to generate 1 MHz REF_TICK from 2 MHz APB clock
(this is a limitation of REF_TICK divider circuit). Since switching
REF_TICK frequency is something we would like to avoid (to maintain
UART output even with DFS), 2 MHz frequency has been marked as
unsupported.
The issue would manifest itself in cases when switching from PM
configuration like {active=160MHz, idle=80MHz} to {active=80MHz,
idle=80Mhz}. After the configuration was changed, PM logic would
think that current frequency was 80MHz and would not do any further
switching. In fact, frequency was still 160MHz.
The old code calculated MAX() of two enum values, but CPU frequency
enum values are not ordered (2MHz goes after 240MHz). This caused
incorrect configuration to be set.
1. External 32kHz crystal is started for too long or it may not start at all. It is often observed at the first start.
2. At the first start, it is possible that the crystal did not start. And the recorded period was recorded as 0. Which led to a division error by zero during the transition to the deep sleep mode (Maybe somewhere else).
3. Added a unit test to test a new method of oscillation an external crystal.
4. Added a new method of oscillating of an external crystal. The legs of the crystal are fed with a 32 kHz frequency.
The new method eliminates these errors.
Added unit test: `\esp-idf\components\soc\esp32\test\test_rtc_clk.c`: `make TEST_COMPONENTS=soc`
- 8 Test starting external RTC crystal. Will pass.
`Bootstrap cycles for external 32kHz crystal` - is specified in the file Kconfig by default 100.
QA tested a new method of oscillation the crystal on 25 boards. The supply of square waves on the crystal showed a 100% result in contrast to the previous method of launching the crystal. After the tests, the old method was deleted.
Closes TW19143
- separate mode stats from lock stats by an extra comment line
- add CPU frequency column to the mode stats
- don’t print a row for light sleep if light sleep is not enabled
s_cpu_freq_by_mode array was statically initialised with 80MHz CPU
frequency in CPU_MAX and APB_MAX modes, but sdkconfig setting for the
CPU frequency could have been different. For the case of 240MHz CPU
frequency, this would cause a frequency switch between 240MHz and
80MHz to happen, even though such switch is not supported in the fast
path switching functions used by the DFS implementation.
This fixes the issue by moving initialisation into esp_pm_impl_init,
which is called at startup before the first mode switch can happen.
Fixes https://github.com/espressif/esp-idf/issues/1729.
The files updated according to code review discussions.
In the sleep_modes.c removed immidiate disable of ULP mode and leave just trigger deactivation.
The esp_sleep.h is updated to have the same defines for source as esp_sleep_wakeup_cause_t.
Updated documentation in sleep_modes.rst file to include cross references.
Some minor changes in test_sleep.c unit test.
(TW#18952)
Closes https://github.com/espressif/esp-idf/issues/1677
Added function esp_sleep_disable_wakeup_source() to deactivate wakeup trigger for selected source.
Updated documentation for this function in sleep_modes.rst file.
Updated unit test to check this functionality for light sleep.
The test_sleep.c unit test is updated to add reliability for unit testing.
(TW#18952)
Closes https://github.com/espressif/esp-idf/issues/1677
The timer wakeup function once activated cannot be disabled later using existing api. If user wants to use different wakeup sources after first sleep but it does not work. This change disables timer wakeup trigger in configuration that will be set into appropriate RTC registers in esp_light_sleep_start() function.
Added function esp_sleep_disable_wakeup_source() to deactivate wakeup trigger for selected source.
Updated documentation for this function in sleep_modes.rst file to pass make html.
Updated unit test to check this functionality for light sleep.
The test_sleep.c unit test is updated to add reliability for auto unit testing.
(TW#18952)
Closes https://github.com/espressif/esp-idf/issues/1677
tools/gen_esp_err_to_name.py generates
components/esp32/esp_err_to_name.c for lookup of the error codes from
all of the IDF project and easily identify all codes in one place
1. Put some lwip udp rx/tx relating functions to IRAM
2. Put some wifi rx/tx relating functions to IRAMa
3. Reduce wifi dynamic malloc from 4 to 1 for each ebuf
4. Update iperf example accordingly
5. Update libphy.a to v383
close github issue#1037 WiFi Promiscuous filter breaks w/
WIFI_PROMIS_FILTER_MASK_ALL and issue#1404
esp_wifi_set_promiscuous_filter set WIFI_PROMIS_FILTER_MASK_ALL error
When INT WDT fires, panicHandler is invoked. In OCD mode, panicHandler
sets a breakpoint on the PC from the exception frame and returns.
However in case of INT WDT, interrupt flag is still set in TIMERG1
peripheral, which causes INT WDT to trigger again. This causes an
endless stream of "Core 0 panic'ed (Interrupt wdt timeout on CPU1)"
messages. OpenOCD also gets terribly confused at this point.
Disable watchdogs when exiting panic handler in OCD mode.
Clear TIMERG1 WDT interrupt flag to prevent re-entry into panic handler.
libc time function now rely on esp_timer_get_time as the source of
high-resolution time, rather than FRC1 timer. Internally, on the ESP32
esp_timer implementation uses FRC2 timer.
- Change help text and labels in Kconfig to use "high-resolution timer"
instead of FRC1. Keep existing Kconfig option name to be backwards
compatible.
- Change references to "FRC1" in the source code to "FRC".
A function to change "in IRAM" status for an existing interrupt handle, without going through free/allocate of the interrupt.
mOS HW timer implementation requires this to make HW timers safe to re-set from an IRAM ISR.
1. Add a hide API for station to receive and process probe request
frame.
2. Fix an issue that wifi/bt coexistence crashes in PSRAM version.
3. Fix an issue that the API for clearing vendor ie can not work.
4. Fix an issue that wifi stop and reboot leads watchdog.
Timer callback can delete the timer. If CONFIG_ESP_TIMER_PROFILING was
enabled, this caused an access to invalid (freed) memory.
This fix adds a pointer to track the timer while executing the callback.
This is needed so that we can check if callback deletes the timer,
in which case we won't try updating profiling counters for this timer
after the callback is done.
Renamed the internal rc to __err_rc to avoid clashes with local variables.
This code would not do the expected thing with the original ESP_ERROR_CHECK macro:
esp_err_t my_func(esp_err_t x)
{
assert(x == 23);
}
esp_err_t rc = 23; //some value that is important fo the user
ESP_ERROR_CHECK(my_func(rc));
The macro will expand to:
esp_err_t rc = (my_func(rc));
And the code will assert, as my_func will receive a random value - whatever is in the internal macro rc temp variable. This is due to the C weirdness of allowing this code:
int x = x; //x has a random value.
This commit reverts the revert on the new task watchdog API. It also
fixes the following bug which caused the reversion.
- sdkconfig TASK_WDT_TIMEOUT_S has been reverted from the unit of ms back to the
unit of seconds. Fixes bug where projects using the new API without rebuilding sdkconfig
would cause the old default value of 5 to be interpreted in ms.
This commit also adds the following features to the task watchdog
- Updated idle hook registration to be compatible with dual core hooks
- Updated dual core hooks to support deregistration for cpu
- Legacy mode has been removed and esp_task_wdt_feed() is now replaced by
esp_task_wdt_reset(). esp_task_wdt_feed() is deprecated
- Idle hooks to reset are now registered/deregistered when the idle tasks are
added/deleted from the Task Watchdog instead of at Task Watchdog init/deinit
- Updated example
1. V366, fix a problem which initialize current can reach 800mA.
2. V365, fix a problem for pll_cap tracking in Coexist (BT & WIFI)
mode. The problem will make Coexist (BT & WIFI) WIFI AP mode TX
Fail in high temperature(>70).
3. V364, fix a bug of BT and Wifi coexist (hung in function of
force_wifi_mode())
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.
With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.
In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
1. Fix WiFi timer enable twice issue
2. Fix a softAP compatibility issue
3. Fix ebuf alloc counter issue
4. remove nvs_flash_init() in esp_wifi_init()
5. Fix scan only find few APs after set bssid
6. Fix can not connect to hidden SoftAP
7. Remove group key entry before connecting ot AP
Moves the ets_timer_arm() / ets_timer_disarm() code paths to RAM
Overhead is 740 bytes of IRAM, 0 bytes DRAM
(For comparison: If all of esp_timer.c is moved to RAM, overhead is 1068 bytes IRAM and 480 bytes DRAM.)
Some frameworks based on ESP-IDF need to be able to decide whether to
initialize SPI RAM after the application has started. This change splits
out part of esp_spiram_init which manipulate cache MMU into a separate
function. Applications can disable cache, call esp_spiram_init_cache,
re-enable cache, and then call esp_spiram_init.
Disabling and re-enabling the cache can be achieved using functions
provided in esp_spi_flash.h.
This commit fixes bugs with the dual core changes to freeRTOS tick and idle hooks.
Interrupt watchdog now registers tick hooks to both cores.
API for cross core tick and idle hook registration were also added
The way these hooks are implemented at the moment, once you register a tick or idle task hook, it is run by both cores, leading to intermittent crashes that are difficult to explain (and debug). One solution is to register the hook with the core that is currently running, which is what this patch attempts to do.
Merges https://github.com/espressif/esp-idf/pull/781
