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Merge branch 'bugfix/uart1_console' into 'master'
Fixes for console output on UART1 See merge request !1649
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1b619c0ec8
@ -796,24 +796,20 @@ static void IRAM_ATTR flash_gpio_configure()
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if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
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// For ESP32D2WD the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32D2WD");
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//flash clock signal should come from IO MUX.
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// flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
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// For ESP32PICOD2 the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32PICOD2");
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//flash clock signal should come from IO MUX.
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// flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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// For ESP32PICOD4 the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32PICOD4");
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//flash clock signal should come from IO MUX.
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// flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else {
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ESP_LOGI(TAG, "Detected ESP32");
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
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gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
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@ -187,7 +187,7 @@ void esp_perip_clk_init(void)
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common_perip_clk = DPORT_WDG_CLK_EN |
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DPORT_I2S0_CLK_EN |
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#if CONFIG_CONSOLE_UART_NUM != 0
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DPORT_UART0_CLK_EN |
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DPORT_UART_CLK_EN |
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#endif
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#if CONFIG_CONSOLE_UART_NUM != 1
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DPORT_UART1_CLK_EN |
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