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Merge branch 'bugfix/phy_init_remove_descriptions' into 'master'

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phy init: remove descriptions of PHY init parameters

See merge request !1363
This commit is contained in:
Jiang Jiang Jian 2017-10-12 19:00:10 +08:00
commit dbee895741
2 changed files with 108 additions and 214 deletions
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107
components/esp32/include/esp_phy_init.h
View File

@ -30,112 +30,7 @@ extern "C" {
* @brief Structure holding PHY init parameters
*/
typedef struct {
uint8_t param_ver_id; /*!< init_data structure version */
uint8_t crystal_select; /*!< 0: 40MHz, 1: 26 MHz, 2: 24 MHz, 3: auto */
uint8_t wifi_rx_gain_swp_step_1; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_2; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_3; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_4; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_5; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_6; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_7; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_8; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_9; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_10; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_11; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_12; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_13; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_14; /*!< do not change */
uint8_t wifi_rx_gain_swp_step_15; /*!< do not change */
uint8_t bt_rx_gain_swp_step_1; /*!< do not change */
uint8_t bt_rx_gain_swp_step_2; /*!< do not change */
uint8_t bt_rx_gain_swp_step_3; /*!< do not change */
uint8_t bt_rx_gain_swp_step_4; /*!< do not change */
uint8_t bt_rx_gain_swp_step_5; /*!< do not change */
uint8_t bt_rx_gain_swp_step_6; /*!< do not change */
uint8_t bt_rx_gain_swp_step_7; /*!< do not change */
uint8_t bt_rx_gain_swp_step_8; /*!< do not change */
uint8_t bt_rx_gain_swp_step_9; /*!< do not change */
uint8_t bt_rx_gain_swp_step_10; /*!< do not change */
uint8_t bt_rx_gain_swp_step_11; /*!< do not change */
uint8_t bt_rx_gain_swp_step_12; /*!< do not change */
uint8_t bt_rx_gain_swp_step_13; /*!< do not change */
uint8_t bt_rx_gain_swp_step_14; /*!< do not change */
uint8_t bt_rx_gain_swp_step_15; /*!< do not change */
uint8_t gain_cmp_1; /*!< do not change */
uint8_t gain_cmp_6; /*!< do not change */
uint8_t gain_cmp_11; /*!< do not change */
uint8_t gain_cmp_ext2_1; /*!< do not change */
uint8_t gain_cmp_ext2_6; /*!< do not change */
uint8_t gain_cmp_ext2_11; /*!< do not change */
uint8_t gain_cmp_ext3_1; /*!< do not change */
uint8_t gain_cmp_ext3_6; /*!< do not change */
uint8_t gain_cmp_ext3_11; /*!< do not change */
uint8_t gain_cmp_bt_ofs_1; /*!< do not change */
uint8_t gain_cmp_bt_ofs_6; /*!< do not change */
uint8_t gain_cmp_bt_ofs_11; /*!< do not change */
uint8_t target_power_qdb_0; /*!< 78 means target power is 78/4=19.5dbm */
uint8_t target_power_qdb_1; /*!< 76 means target power is 76/4=19dbm */
uint8_t target_power_qdb_2; /*!< 74 means target power is 74/4=18.5dbm */
uint8_t target_power_qdb_3; /*!< 68 means target power is 68/4=17dbm */
uint8_t target_power_qdb_4; /*!< 64 means target power is 64/4=16dbm */
uint8_t target_power_qdb_5; /*!< 52 means target power is 52/4=13dbm */
uint8_t target_power_index_mcs0; /*!< target power index is 0, means target power is target_power_qdb_0 19.5dbm; (1m,2m,5.5m,11m,6m,9m) */
uint8_t target_power_index_mcs1; /*!< target power index is 0, means target power is target_power_qdb_0 19.5dbm; (12m) */
uint8_t target_power_index_mcs2; /*!< target power index is 1, means target power is target_power_qdb_1 19dbm; (18m) */
uint8_t target_power_index_mcs3; /*!< target power index is 1, means target power is target_power_qdb_1 19dbm; (24m) */
uint8_t target_power_index_mcs4; /*!< target power index is 2, means target power is target_power_qdb_2 18.5dbm; (36m) */
uint8_t target_power_index_mcs5; /*!< target power index is 3, means target power is target_power_qdb_3 17dbm; (48m) */
uint8_t target_power_index_mcs6; /*!< target power index is 4, means target power is target_power_qdb_4 16dbm; (54m) */
uint8_t target_power_index_mcs7; /*!< target power index is 5, means target power is target_power_qdb_5 13dbm */
uint8_t pwr_ind_11b_en; /*!< 0: 11b power is same as mcs0 and 6m, 1: 11b power different with OFDM */
uint8_t pwr_ind_11b_0; /*!< 1m, 2m power index [0~5] */
uint8_t pwr_ind_11b_1; /*!< 5.5m, 11m power index [0~5] */
uint8_t chan_backoff_en; /*!< 0: channel backoff disable, 1:channel backoff enable */
uint8_t chan1_power_backoff_qdb; /*!< 4 means backoff is 1db */
uint8_t chan2_power_backoff_qdb; /*!< see chan1_power_backoff_qdb */
uint8_t chan3_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan4_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan5_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan6_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan7_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan8_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan9_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan10_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan11_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan12_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan13_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan14_power_backoff_qdb; /*!< chan1_power_backoff_qdb */
uint8_t chan1_rate_backoff_index; /*!< if bit i is set, backoff data rate is target_power_qdb_i */
uint8_t chan2_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan3_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan4_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan5_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan6_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan7_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan8_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan9_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan10_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan11_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan12_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan13_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t chan14_rate_backoff_index; /*!< see chan1_rate_backoff_index */
uint8_t spur_freq_cfg_msb_1; /*!< first spur: */
uint8_t spur_freq_cfg_1; /*!< spur_freq_cfg = (spur_freq_cfg_msb_1 <<8) | spur_freq_cfg_1 */
uint8_t spur_freq_cfg_div_1; /*!< spur_freq=spur_freq_cfg/spur_freq_cfg_div_1 */
uint8_t spur_freq_en_h_1; /*!< the seventh bit for total enable */
uint8_t spur_freq_en_l_1; /*!< each bit for 1 channel, and use [spur_freq_en_h, spur_freq_en_l] to select the spur's channel priority */
uint8_t spur_freq_cfg_msb_2; /*!< second spur: */
uint8_t spur_freq_cfg_2; /*!< spur_freq_cfg = (spur_freq_cfg_msb_2 <<8) | spur_freq_cfg_2 */
uint8_t spur_freq_cfg_div_2; /*!< spur_freq=spur_freq_cfg/spur_freq_cfg_div_2 */
uint8_t spur_freq_en_h_2; /*!< the seventh bit for total enable */
uint8_t spur_freq_en_l_2; /*!< each bit for 1 channel, and use [spur_freq_en_h, spur_freq_en_l] to select the spur's channel priority */
uint8_t spur_freq_cfg_msb_3; /*!< third spur: */
uint8_t spur_freq_cfg_3; /*!< spur_freq_cfg = (spur_freq_cfg_msb_3 <<8) | spur_freq_cfg_3 */
uint8_t spur_freq_cfg_div_3; /*!< spur_freq=spur_freq_cfg/spur_freq_cfg_div_3 */
uint8_t spur_freq_en_h_3; /*!< the seventh bit for total enable */
uint8_t spur_freq_en_l_3; /*!< each bit for 1 channel, and use [spur_freq_en_h, spur_freq_en_l] to select the spur's channel priority, */
uint8_t reserved[23]; /*!< reserved for future expansion */
uint8_t params[128]; /*!< opaque PHY initialization parameters */
} esp_phy_init_data_t;
/**

215
components/esp32/phy_init_data.h
View File

@ -26,114 +26,113 @@ static const char phy_init_magic_pre[] = PHY_INIT_MAGIC;
/**
* @brief Structure containing default recommended PHY initialization parameters.
*/
static const esp_phy_init_data_t phy_init_data= {
.param_ver_id = 1,
.crystal_select = 3,
.wifi_rx_gain_swp_step_1 = 0x05,
.wifi_rx_gain_swp_step_2 = 0x04,
.wifi_rx_gain_swp_step_3 = 0x06,
.wifi_rx_gain_swp_step_4 = 0x05,
.wifi_rx_gain_swp_step_5 = 0x01,
.wifi_rx_gain_swp_step_6 = 0x06,
.wifi_rx_gain_swp_step_7 = 0x05,
.wifi_rx_gain_swp_step_8 = 0x04,
.wifi_rx_gain_swp_step_9 = 0x06,
.wifi_rx_gain_swp_step_10 = 0x04,
.wifi_rx_gain_swp_step_11 = 0x05,
.wifi_rx_gain_swp_step_12 = 0x00,
.wifi_rx_gain_swp_step_13 = 0x00,
.wifi_rx_gain_swp_step_14 = 0x00,
.wifi_rx_gain_swp_step_15 = 0x00,
.bt_rx_gain_swp_step_1 = 0x05,
.bt_rx_gain_swp_step_2 = 0x04,
.bt_rx_gain_swp_step_3 = 0x06,
.bt_rx_gain_swp_step_4 = 0x05,
.bt_rx_gain_swp_step_5 = 0x01,
.bt_rx_gain_swp_step_6 = 0x06,
.bt_rx_gain_swp_step_7 = 0x05,
.bt_rx_gain_swp_step_8 = 0x00,
.bt_rx_gain_swp_step_9 = 0x00,
.bt_rx_gain_swp_step_10 = 0x00,
.bt_rx_gain_swp_step_11 = 0x00,
.bt_rx_gain_swp_step_12 = 0x00,
.bt_rx_gain_swp_step_13 = 0x00,
.bt_rx_gain_swp_step_14 = 0x00,
.bt_rx_gain_swp_step_15 = 0x00,
.gain_cmp_1 = 0x0a,
.gain_cmp_6 = 0x0a,
.gain_cmp_11 = 0x0c,
.gain_cmp_ext2_1 = 0xf0,
.gain_cmp_ext2_6 = 0xf0,
.gain_cmp_ext2_11 = 0xf0,
.gain_cmp_ext3_1 = 0xe0,
.gain_cmp_ext3_6 = 0xe0,
.gain_cmp_ext3_11 = 0xe0,
.gain_cmp_bt_ofs_1 = 0x18,
.gain_cmp_bt_ofs_6 = 0x18,
.gain_cmp_bt_ofs_11 = 0x18,
.target_power_qdb_0 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 78),
.target_power_qdb_1 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 76),
.target_power_qdb_2 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 74),
.target_power_qdb_3 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 68),
.target_power_qdb_4 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 60),
.target_power_qdb_5 = LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52),
.target_power_index_mcs0 = 0,
.target_power_index_mcs1 = 0,
.target_power_index_mcs2 = 1,
.target_power_index_mcs3 = 1,
.target_power_index_mcs4 = 2,
.target_power_index_mcs5 = 3,
.target_power_index_mcs6 = 4,
.target_power_index_mcs7 = 5,
.pwr_ind_11b_en = 0,
.pwr_ind_11b_0 = 0,
.pwr_ind_11b_1 = 0,
.chan_backoff_en = 0,
.chan1_power_backoff_qdb = 0,
.chan2_power_backoff_qdb = 0,
.chan3_power_backoff_qdb = 0,
.chan4_power_backoff_qdb = 0,
.chan5_power_backoff_qdb = 0,
.chan6_power_backoff_qdb = 0,
.chan7_power_backoff_qdb = 0,
.chan8_power_backoff_qdb = 0,
.chan9_power_backoff_qdb = 0,
.chan10_power_backoff_qdb = 0,
.chan11_power_backoff_qdb = 0,
.chan12_power_backoff_qdb = 0,
.chan13_power_backoff_qdb = 0,
.chan14_power_backoff_qdb = 0,
.chan1_rate_backoff_index = 0,
.chan2_rate_backoff_index = 0,
.chan3_rate_backoff_index = 0,
.chan4_rate_backoff_index = 0,
.chan5_rate_backoff_index = 0,
.chan6_rate_backoff_index = 0,
.chan7_rate_backoff_index = 0,
.chan8_rate_backoff_index = 0,
.chan9_rate_backoff_index = 0,
.chan10_rate_backoff_index = 0,
.chan11_rate_backoff_index = 0,
.chan12_rate_backoff_index = 0,
.chan13_rate_backoff_index = 0,
.chan14_rate_backoff_index = 0,
.spur_freq_cfg_msb_1 = 0,
.spur_freq_cfg_1 = 0,
.spur_freq_cfg_div_1 = 0,
.spur_freq_en_h_1 = 0,
.spur_freq_en_l_1 = 0,
.spur_freq_cfg_msb_2 = 0,
.spur_freq_cfg_2 = 0,
.spur_freq_cfg_div_2 = 0,
.spur_freq_en_h_2 = 0,
.spur_freq_en_l_2 = 0,
.spur_freq_cfg_msb_3 = 0,
.spur_freq_cfg_3 = 0,
.spur_freq_cfg_div_3 = 0,
.spur_freq_en_h_3 = 0,
.spur_freq_en_l_3 = 0,
.reserved = {0}
};
static const esp_phy_init_data_t phy_init_data= { {
1,
3,
0x05,
0x04,
0x06,
0x05,
0x01,
0x06,
0x05,
0x04,
0x06,
0x04,
0x05,
0x00,
0x00,
0x00,
0x00,
0x05,
0x04,
0x06,
0x05,
0x01,
0x06,
0x05,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x0a,
0x0a,
0x0c,
0xf0,
0xf0,
0xf0,
0xe0,
0xe0,
0xe0,
0x18,
0x18,
0x18,
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 78),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 76),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 74),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 68),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 60),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52),
0,
0,
1,
1,
2,
3,
4,
5,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
} };
static const char phy_init_magic_post[] = PHY_INIT_MAGIC;