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Merge branch 'feature/spiram_init_in_app' into 'master'
spiram: expose function to initialize SPI RAM cache See merge request !1281
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commit
d3bb9de36a
@ -150,6 +150,7 @@ void IRAM_ATTR call_start_cpu0()
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}
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#if CONFIG_SPIRAM_BOOT_INIT
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esp_spiram_init_cache();
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if (esp_spiram_init() != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
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abort();
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@ -27,6 +27,17 @@
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*/
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esp_err_t esp_spiram_init();
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/**
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* @brief Configure Cache/MMU for access to external SPI RAM.
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*
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* Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
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* option is enabled. Applications which need to enable SPI RAM at run time
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* can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
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*
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* @attention this function must be called with flash cache disabled.
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*/
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void esp_spiram_init_cache();
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/**
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* @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
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@ -76,4 +87,4 @@ void esp_spiram_writeback_cache();
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esp_err_t esp_spiram_reserve_dma_pool(size_t size);
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#endif
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#endif
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@ -91,9 +91,7 @@ bool esp_spiram_test()
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}
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}
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esp_err_t esp_spiram_init()
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void IRAM_ATTR esp_spiram_init_cache()
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{
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//Enable external RAM in MMU
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cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
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@ -102,7 +100,11 @@ esp_err_t esp_spiram_init()
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
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cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
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#endif
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}
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esp_err_t esp_spiram_init()
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{
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esp_err_t r;
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r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
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if (r != ESP_OK) {
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@ -202,4 +204,4 @@ void IRAM_ATTR esp_spiram_writeback_cache()
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#endif
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#endif
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