update gpio_sig at `spics_out` array in each spi_periph.c of chips later than s2
then `spi_bus_add_device` can correctly distribute gpio_signals for cs_signal
Closes https://github.com/espressif/esp-idf/issues/8876
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
By using IOMUX instead of GPIO Matrix for UART, it is now possible
on ESP32 boards to use the UART as a wake up source even if it is
not used as a console.
For other boards where this issue was not present, using IOMUX has
the advantage to be faster than using GPIO matrix, so a highest
baudrate can be used
* sync the latest struct header file from ESP32
* add soc_caps.h macros to distinguish between IO MUX and GPIO Matrix
support in SDMMC on different chips.
* store GPIO matrix signal numbers in sdmmc_slot_info_t
add usb hal/soc, usb_ll files and esp32s3 target for usb
move usb_hal.h into soc common folder
soc/hal: fix soc and periph for usb
tinyusb: fix tinyusb io header
hal: usb_ll fix pull up/down config for esp32s3
soc/hal: fix peripheral addresses
Add support to tasks stacks in RTC DRAM. Before this fix, any stack
in RTC DRAM would have been considered as corrupted, whichi is not
the case.
Fix a bug related to wrong parameters passed to esp_core_dump_get_stack.
Fix a bug reading fake stack memory, triggering a memory violation.
* Closes https://github.com/espressif/esp-idf/issues/6751
* Merges https://github.com/espressif/esp-idf/pull/6750
freertos/port: update the port files and split into xtensa and riscv ports
freertos: separated cpu files from rest of the kernel sources
freertos/port_xtensa: separated private include files into a folder
freertos/tasks: added task create pinned to core function do not break current IDF API
freertos/tasks: mimiced task create pinned function into tasks.c to do not break the IDF API.
freertos: freertos component now compiling
freertos: freertos component now building
freertos: moved critical sections outside from FR kernel section to portable section
portmacro_xtensa: add void indentifier on functions that take no arguments
freertos: fix critical sections implementation to match with their function prototype
freertos: add cmake changes of freertos into make
freertos: remove portDONT_DISCARD attribute from switch context function, it was breaking the docs building.
freertos: fix conflicitng types of vApplicationSleep function
license: update the license of freertos
freertos: Doxygen comments refactored to render them correctly on docs
freertos: added new functions of freertos into the documentation
freertos: added message buffers and stream buffers to documentation
sysview: update freertos system view to the compatible with version 10
freertos: fixed event group documentation rendering
freertos: update static task structure to match the actual tcb size
freertos: removed backported test functions
freertos/smp: brought SMP code to FreeRTOS 10 port
freertos/portmacro: added missing crosscore interrupt for yielding tasks
freertos: replaced soft-critical sections with hard-critical sections used by SMP
freertos: placed muxes inside of kernel objects
freertos: replaced original FR critical sections with SMP enabled spinlocks critical sections
freertos: moved xtensa port files to a separated folder
freertos: added multiple instance of global variables required to SMP
freertos: added SMP modifications on specific tasks module functions
freertos: added TLS deletion function to task module
freertos/tls: initialize TLS deletion callback to avoid crashing when calling task delete
freertos: modified vTaskDelete to do not erase current task that runs on other core
freertos: reverted taskhandle and timerhandle as void* type
freertos: fixed de-referencing void pointer to get run time counter
freertos: fix system view trace enter macro arguments
freertos: Replaced soft critical sections with spinlocks on event_groups
freertos: fixed tick function to avoid calling tick hooks twice
freertos: Nofity give checking per CPU if schedule is suspended
freertos: added mpu release on TCB deletion
freertos: Added SMP changes when deleting a TCB on idle task
freertos/license: update freertos license in COPYRIGHT.rst
freertos: unicore configurations can use task create pinned to core, it will be always pinned to core 0
freertos/portmacro: added cpu_hal_get_core_id() function instead of inline assembly
freertos/xtensa: update xtensa specific files used in master branch
newlib/locks: revert the preemption checking in lock acquisition and release
ref_clock: fix initial state of ref_clock interrupt handler
freertos: added missing critical sections and yielding checkings
freertos: remove magic numbers in vTaskDelete
freertos: added missing critical section in prvIsQueueEmpty
This fixes the issue where XTOS_SET_INTLEVEL would lower INTLEVEL from
4 to 3, when eTaskGetState is invoked during the core dump, triggered
from the interrupt watchdog.
- for ESP32 only enabled in case of unicore config
- capability wise this region (8K) is same as DRAM, except non-DMA capable
- also fixed small issue in reserved memory region processing when (start == end)
This commit updates the watchdog timers (MWDT and RWDT)
in the following ways:
- Add seprate LL for MWDT and RWDT.
- Add a combined WDT HAL for all Watchdog Timers
- Update int_wdt.c and task_wdt.c to use WDT HAL
- Remove most dependencies on LL or direct register access
in other components. They will now use the WDT HAL
- Update use of watchdogs (including RTC WDT) in bootloader and
startup code to use the HAL layer.
Goal is that multiple faults would be required to bypass a boot-time signature check.
- Also strengthens some address range checks for safe app memory addresses
- Change pre-enable logic to also check the bootloader signature before enabling SBV2 on ESP32
Add some additional checks for invalid sections:
- Sections only partially in DRAM or IRAM are invalid
- If a section is in D/IRAM, allow the possibility only some is in D/IRAM
- Only pass sections that are entirely in the same type of RTC memory region
spin_lock: cleaned-up port files and removed portmux files
components/soc: decoupled compare and set operations from FreeRTOS
soc/spinlock: filled initial implementation of spinlock refactor
It will decouple the spinlocks into separated components with not depencences of freertos
an similar interface was provided focusing the readabillity and maintenance, also
naming to spinlocks were adopted. On FreeRTOS side the legacy portMUX macros
gained a form of wrapper functions that calls the spinlocks component thus
minimizing the impact on RTOS side.
This feature aims to close IDF-967
soc/spinlock: spinlocks passed on unit test, missing test corner cases
components/compare_set: added better function namings plus minor performance optimization on spinlocks
soc/spinlock: code reordering to remove ISC C90 mix error
freertos/portmacro: gor rid of critical sections multiline macros, placed inline functions instead
soc/spinlock: improved spinlock performance from internal RAM
For cases where the spinlock is executed from IRAM, there is no
need to check where the spinlock object is placed on memory,
removing this checks caused a great improvement on performance.
The following commit refactors the CAN driver such that
it is split into HAL and Lowlevel layers. The following
changes have also been made:
- Added bit field members to can_message_t as alternative
to message flags. Updated examples and docs accordingly
- Register field names and fields of can_dev_t updated
