Commit Graph

52 Commits

Author SHA1 Message Date
Konstantin Kondrashov
8b418d4b09 feat(esp_system): Print backtrace for both CPUs when cache error does not determine CPU 2024-04-30 15:20:58 +03:00
Konstantin Kondrashov
3f89072af1 feat(all): Use PRIx macro in all logs 2024-03-12 11:15:53 +02:00
Marius Vikhammer
06850e0e1e refactor(system): removed esp_system from astyle ignore list and reformated it 2024-01-30 15:17:15 +08:00
Marius Vikhammer
9f1d001849 Merge branch 'feat/cache_error_c6_h2' into 'master'
fix(panic): fixed cache error being reported as illegal instruction

Closes IDF-6398, IDF-5657, IDF-7015, and IDF-6733

See merge request 
2023-12-21 10:32:06 +08:00
Chip Weinberger
3686689a2a feat(esp_system): Add esp_backtrace_print_all_tasks()
This commit adds esp_backtrace_print_all_tasks() which prints the backtraces
of all tasks at runtime.

Closes https://github.com/espressif/esp-idf/issues/9708
CLoses https://github.com/espressif/esp-idf/pull/11575

[Omar Chebib: Prevent task switching while printing backtraces of tasks.]
[Omar Chebib: Ensure all task stacks are flushed from register to RAM.]
[Omar Chebib: Removed esp_task_snapshot_to_backtrace_frame() as task snapshot is private API.]
[Omar Chebib: Added test case for esp_backtrace_print_all_tasks().]

Signed-off-by: Omar Chebib <omar.chebib@espressif.com>
2023-12-12 19:54:17 +08:00
Marius Vikhammer
9a6de4cb3e fix(panic): fixed cache error being reported as illegal instruction
On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.

Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.
2023-12-04 10:49:00 +08:00
Darian Leung
a5d5ee7445 change(xtensa): Deprecate ".../xtensa_context.h" include path
This commit deprecates the "freertos/xtensa_context.h" and "xtensa/xtensa_context.h"
include paths. Users should use "xtensa_context.h" instead.

- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_api.h"
- Add warning to compatibility header
2023-11-30 21:58:52 +08:00
Sudeep Mohanty
d38f100223 change(freertos/idf): Deprecate some FreeRTOS IDF addition functions
This commit deprecates xTaskGetAffinity(), xTaskGetCurrentTaskHandleForCPU()
and xTaskGetIdleTaskHandleForCPU() APIs for IDF-FreeRTOS kernel.
Instead, users are directed to use alternatives. All other
components in IDF using these functions have been updated accordingly.
2023-11-03 14:54:06 +01:00
KonstantinKondrashov
7a878bdc50 feat(esp_system): Support IPC_ISR for ESP32P4 2023-09-15 23:38:12 +08:00
Armando
de77ab3061 change(soc): added SOC_ prefix to mmu defs 2023-09-05 15:47:26 +08:00
Paul Guyot
ceb121fd57 esp_system: Fix a race-condition in esp_ipc_isr (in QEMU env)
The race condition is very unlikely on real hardware but can be observed with
qemu under heavy load.
Also add missing `memw` instructions which are generated by the C compiler but
absent in the assembly code.

Signed-off-by: Paul Guyot <pguyot@kallisys.net>
Signed-off-by: KonstantinKondrashov <konstantin@espressif.com>

Merges https://github.com/espressif/esp-idf/pull/11447
Closes https://github.com/espressif/esp-idf/issues/11433
2023-05-24 19:08:29 +08:00
Zim Kalinowski
fb7aafd348 esp_system: fix and reenable no-format warning 2023-03-28 13:42:44 +02:00
Jakob Hasse
03bc6488de bugfix(esp_system): made watchpoint setting configuration-dependent
esp_execute_shared_stack_function always restored the stack watchpoint
regardless of CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK. This would lead
to an abondoned but active watchpoint on a former stack once the task
calling esp_execute_shared_stack_function is deleted, if
CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is inactive.
This has been fixed now.

Closes https://github.com/espressif/esp-idf/issues/10414
2023-03-13 14:24:15 +08:00
Alexey Gerenkov
47c2c13de5 build: Adds support for universal Clang toolchain 2022-11-23 13:25:16 +03:00
Guillaume Souchere
9b8c558e63 Merge branch 'bugfix/backtrace_formatting_add_missing_space' into 'master'
Reverts Backtrace: format to what it used to be

Closes IDFGH-7580

See merge request 
2022-07-07 16:51:47 +08:00
Darian Leung
95955ed170 esp_system: Workaround esp_ipc_isr_stall_other_cpu() deadlock with SMP FreeRTOS
SMP FreeRTOS uses a single kernel lock for all critical sections. There is a known
issue with esp_ipc_isr_stall_other_cpu() that can cause dead if the other CPU is
already in a critical section.

This commit adds a temporary workaround to reduce the chance of deadlock by taking
the SMP FreeRTOS kernel lock first before stalling the other CPU.

See IDF-5257 for more details.
2022-06-17 15:37:07 +08:00
Mitch Bradley
8d9e110a04 Reverts Backtrace: format to what it used to be
Was:  Backtrace: N:M N:M N:M ...
Now:  Backtrace:N:MN:M N:M ...

The problem with the new format is that it is hard to parse and
breaks the parser that is used by PlatformIO.  The old format
is much more reasonable.  I do not see how the pattern in IDFDUT.py
can work with the new format, due to the missing space after the :
2022-06-10 18:33:46 -10:00
Konstantin Kondrashov
b824f68b35 Merge branch 'feature/move_dport_workaround_to_g0' into 'master'
dport_access: Move DPORT workaround to G0

Closes IDF-2177

See merge request 
2022-06-01 12:11:12 +08:00
KonstantinKondrashov
ac4c7d99fe dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
Darian Leung
daa950d9ed freertos: Replace portSET_INTERRUPT_MASK_FROM_ISR() call for SMP
The behavior of portSET_INTERRUPT_MASK_FROM_ISR() has changed in SMP FreeRTOS. It's
previous behavior is now implemented in portDISABLE_INTERRUPTS() and portRESTORE_INTERRUPTS().

This commit replaces all portSET_INTERRUPT_MASK_FROM_ISR() and portCLEAR_INTERRUPT_MASK_FROM_ISR()
calls with portDISABLE_INTERRUPTS() and portRESTORE_INTERRUPTS() respectively
2022-05-30 06:11:24 +08:00
Armando
c1cbd7bbf6 cache/mmu: implememnt cache and mmu hal APIs in bootloader 2022-03-11 22:43:11 +08:00
Darian Leung
57fd78f5ba freertos: Remove legacy data types
This commit removes the usage of all legacy FreeRTOS data types that
are exposed via configENABLE_BACKWARD_COMPATIBILITY. Legacy types can
still be used by enabling CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY.
2022-02-09 23:05:45 +08:00
morris
ef00bd59dc esp_rom: extract int matrix route and cpu ticks getter 2022-02-09 13:52:20 +08:00
Darian Leung
3336b057d6 xtensa: Move saving of a0 register to match upstream
Upstream xtensa exception handling will save PS, PC, and a0 registers
together when saving a minimal context. This commit ppdates the xtensa
exception handling to match upstream behavior.
2022-02-03 17:08:14 +08:00
KonstantinKondrashov
f49787ac9f esp_system: ipc_isr does not use its own initialization task, it is done from ipc_task()
It helps to reduce the memory usage at startup.

Closes https://github.com/espressif/esp-idf/issues/8111
2022-01-13 21:28:08 +08:00
Sudeep Mohanty
e22b4007d3 esp_hw_support: Removed deprecated CPU util functions
The following files were deleted:
- components/esp_hw_support/include/soc/cpu.h
- components/soc/esp32s3/include/soc/cpu.h

The following functions are deprecated:
- get_sp()

The following functions declared in soc/cpu.h are now moved to esp_cpu.h:
- esp_cpu_configure_region_protection()

The following functions declared in soc/cpu.h are now moved to components/xtensa/include/esp_cpu_utils.h:
- esp_cpu_process_stack_pc()

All files with soc/cpu.h inclusion are updated to include esp_cpu.h instead.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2021-12-28 16:58:37 +05:30
Martin Vychodil
dd938eb952 System/Security: Memprot API unified (ESP32C3)
Unified Memory protection API for all PMS-aware chips (ESP32C3)

Closes JIRA IDF-3849
2021-12-21 01:50:36 +01:00
Cao Sen Miao
7f0a746e6a move brownout trax cache_int_err to private folder 2021-11-26 18:27:53 +08:00
KonstantinKondrashov
209702d055 esp_ipc: Update documentation and API descriptions
This commit updates the documentation and API descriptions of
the esp_ipc and esp_ipc_isr features.
2021-11-18 21:34:50 +08:00
Omar Chebib
9d5923a13e IPC: Move ipc sources to esp_system
IPC shall be put back into esp_system as it is an 'OS additions'.
2021-11-11 10:30:01 +08:00
Alexey Gerenkov
bb9cd84cdc debug_stubs: Refactor and add support for RISCV 2021-11-04 01:33:24 +03:00
Alexey Gerenkov
111ba5bbe6 trax: Adds ESP32-S3 support 2021-10-22 23:36:28 +03:00
Mahavir Jain
bdeaeb8d7f esp_system: enable "cache disable but cache accessed" interrupt for ESP32-S3 2021-10-20 15:16:25 +05:30
Zim Kalinowski
584806a78a updated copyright text 2021-10-11 11:38:35 +08:00
Zim Kalinowski
f2b538b9e7 Merge branch 'master' into feature/github-7517 2021-10-09 18:58:27 +08:00
David Čermák
9f957cbfe2 Merge branch 'bugfix/memprot_panic_print_const_correction' into 'master'
panic: Fix minor const string correction on meprot panic print

See merge request 
2021-09-13 06:13:33 +00:00
David Cermak
0ee4c235eb panic/memprot: Fix minor const string correction on panic print 2021-09-09 11:46:21 +02:00
baohongde
d1db2df316 components/bt: High level interrupt in bluetooth
components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt

components/os: high level interrupt(5)

components/os: hli_api: meta queue: fix out of bounds access, check for overflow

components/os: hli: don't spill registers, instead save them to a separate region

Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).

Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.

components/bt: using high level interrupt in lc

components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`

components/bt: optimize code structure

components/os: Modify the BT assert process to adapt to coredump and HLI

components/os: Disable exception mode after saving special registers

To store some registers first, avoid stuck due to live lock after disabling exception mode

components/os: using dport instead of AHB in BT to fix live lock

components/bt: Fix hli queue send error

components/bt: Fix CI fail

# Conflicts:
#	components/bt/CMakeLists.txt
#	components/bt/component.mk
#	components/bt/controller/bt.c
#	components/bt/controller/lib
#	components/esp_common/src/int_wdt.c
#	components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
#	components/soc/esp32/include/soc/soc.h
2021-09-09 11:29:06 +08:00
boarchuz
ec70bc0523 fix compiler warning with silent panic option 2021-09-04 14:46:26 +10:00
Martin Vychodil
58aed7df98 ESP32S2: No assert()/abort() in Memprot API, use esp_err_t instead
JIRA IDF-3634
2021-08-26 09:20:00 +02:00
Angus Gratton
c22eb769e7 Merge branch 'bugfix/panic_instrprohibited' into 'master'
esp_system: fix instrprohibited panic backtrace regression

See merge request 
2021-04-07 05:14:19 +00:00
Renz Bagaporo
75624c5355 esp_system: fix instrprohibited panic backtrace regression
First PC should have been ignored in the case of InstProhibited panic
when printing backtrace.
2021-04-05 22:05:27 +08:00
Angus Gratton
6b57f33858 Merge branch 'refactor/movements_from_target_components' into 'master'
Movement from target components 1

See merge request 
2021-04-05 02:37:21 +00:00
Renz Bagaporo
301c48b6b2 esp_system: remove duplicate panic backtrace code 2021-04-01 07:22:57 +00:00
Renz Bagaporo
7d85c42e52 esp32: move brownout and cache err int setup 2021-03-31 19:13:03 +08:00
Renz Bagaporo
1efdcd69d9 xtensa: move out trax 2021-02-26 19:45:48 +08:00
Renz Bagaporo
7e0e91bf76 arch: move debug helpers 2021-02-26 13:34:29 +08:00
Renz Bagaporo
91a5770fd2 arch: move shared stack implementation to esp_system 2021-02-26 13:34:29 +08:00
Martin Vychodil
69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
2021-01-27 08:44:03 +01:00
Omar Chebib
c218f669ba panic on RISC-V: Take into account Merge Request comments 2020-12-31 15:46:17 +08:00