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Merge branch 'refactor/movements_from_target_components' into 'master'

Browse Source 
Movement from target components 1

See merge request espressif/esp-idf!12482
This commit is contained in:
Angus Gratton 2021-04-05 02:37:21 +00:00
commit 6b57f33858
132 changed files with 1033 additions and 2526 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
components/bt/controller/esp32c3/bt.c
View File

@ -40,7 +40,7 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/soc_memory_layout.h"
#include "esp_clk.h"
#include "esp32c3/clk.h"
#include "esp_coexist_internal.h"
#include "esp32c3/rom/rom_layout.h"
#include "esp_timer.h"

2
components/bt/controller/esp32s3/bt.c
View File

@ -41,7 +41,7 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/soc_memory_layout.h"
#include "esp_clk.h"
#include "esp32c3/clk.h"
#include "esp_coexist_internal.h"
#if CONFIG_BT_ENABLED

0
components/esp32/test/test_stack_check_cxx.cpp → components/cxx/test/test_stack_check_cxx.cpp
View File

9
components/esp32/CMakeLists.txt
View File

@ -12,16 +12,11 @@ if(BOOTLOADER_BUILD)
else()
# Regular app build
set(srcs
"cache_err_int.c"
"cache_sram_mmu.c"
"clk.c"
"crosscore_int.c"
"dport_access.c"
"esp_himem.c"
"hw_random.c"
"spiram.c"
"spiram_psram.c"
"system_api_esp32.c")
"spiram_psram.c")
set(include_dirs "include")
@ -31,11 +26,9 @@ else()
# esp_timer is added here because cpu_start.c uses esp_timer
set(priv_requires app_trace app_update bootloader_support esp_system log mbedtls nvs_flash pthread
spi_flash vfs espcoredump esp_common perfmon esp_timer esp_ipc esp_pm)
set(fragments linker.lf ld/esp32_fragments.lf)
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS "${include_dirs}"
LDFRAGMENTS "${fragments}"
REQUIRES "${requires}"
PRIV_REQUIRES "${priv_requires}"
REQUIRED_IDF_TARGETS esp32)

48
components/esp32/Kconfig
View File

@ -373,42 +373,6 @@ menu "ESP32-specific"
default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS
default 0x0
choice ESP32_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
receive a universally administered MAC address. These are generated sequentially by adding 0
and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
addresses, respectively.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 2 or 4 per device.)
config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_BT
config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
bool "Four"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
select ESP_MAC_ADDR_UNIVERSE_BT
select ESP_MAC_ADDR_UNIVERSE_ETH
endchoice
config ESP32_UNIVERSAL_MAC_ADDRESSES
int
default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
config ESP32_ULP_COPROC_ENABLED
@ -487,18 +451,6 @@ menu "ESP32-specific"
default 6 if ESP32_BROWNOUT_DET_LVL_SEL_6
default 7 if ESP32_BROWNOUT_DET_LVL_SEL_7
#Reduce PHY TX power when brownout reset
config ESP32_REDUCE_PHY_TX_POWER
bool "Reduce PHY TX power when brownout reset"
depends on ESP32_BROWNOUT_DET
default y
help
When brownout reset occurs, reduce PHY TX power to keep the code running
# Note about the use of "FRC1" name: currently FRC1 timer is not used for
# high resolution timekeeping anymore. Instead the esp_timer API is used.
# FRC1 name in the option name is kept for compatibility.
choice ESP32_TIME_SYSCALL
prompt "Timers used for gettimeofday function"
default ESP32_TIME_SYSCALL_USE_RTC_FRC1

52
components/esp32/clk.c
View File

@ -1,52 +0,0 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "soc/rtc.h"
#include "esp32/clk.h"
#define MHZ (1000000)
// g_ticks_us defined in ROMs for PRO and APP CPU
extern uint32_t g_ticks_per_us_pro;
#ifndef CONFIG_FREERTOS_UNICORE
extern uint32_t g_ticks_per_us_app;
#endif
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return g_ticks_per_us_pro * MHZ;
}
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(g_ticks_per_us_pro, 80) * MHZ;
}
int IRAM_ATTR esp_clk_xtal_freq(void)
{
return rtc_clk_xtal_freq_get() * MHZ;
}
void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
{
/* Update scale factors used by esp_rom_delay_us */
g_ticks_per_us_pro = ticks_per_us;
#ifndef CONFIG_FREERTOS_UNICORE
g_ticks_per_us_app = ticks_per_us;
#endif
}

2
components/esp32/component.mk
View File

@ -17,8 +17,6 @@ COMPONENT_ADD_LDFLAGS += -L $(COMPONENT_PATH)/ld \
-u ld_include_panic_highint_hdl \
$(addprefix -T ,$(LINKER_SCRIPTS)) \
COMPONENT_ADD_LDFRAGMENTS += ld/esp32_fragments.lf linker.lf
# final linking of project ELF depends on all binary libraries, and
# all linker scripts (except esp32_out.ld, as this is code generated here.)
COMPONENT_ADD_LINKER_DEPS := $(addprefix ld/, $(filter-out $(COMPONENT_BUILD_DIR)/esp32.project.ld, $(LINKER_SCRIPTS))) \

69
components/esp32/hw_random.c
View File

@ -1,69 +0,0 @@
// Copyright 2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <stddef.h>
#include <string.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "hal/cpu_hal.h"
#include "esp32/clk.h"
#include "soc/wdev_reg.h"
uint32_t IRAM_ATTR esp_random(void)
{
/* The PRNG which implements WDEV_RANDOM register gets 2 bits
* of extra entropy from a hardware randomness source every APB clock cycle
* (provided WiFi or BT are enabled). To make sure entropy is not drained
* faster than it is added, this function needs to wait for at least 16 APB
* clock cycles after reading previous word. This implementation may actually
* wait a bit longer due to extra time spent in arithmetic and branch statements.
*
* As a (probably unncessary) precaution to avoid returning the
* RNG state as-is, the result is XORed with additional
* WDEV_RND_REG reads while waiting.
*/
/* This code does not run in a critical section, so CPU frequency switch may
* happens while this code runs (this will not happen in the current
* implementation, but possible in the future). However if that happens,
* the number of cycles spent on frequency switching will certainly be more
* than the number of cycles we need to wait here.
*/
uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
static uint32_t last_ccount = 0;
uint32_t ccount;
uint32_t result = 0;
do {
ccount = cpu_hal_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
last_ccount = ccount;
return result ^ REG_READ(WDEV_RND_REG);
}
void esp_fill_random(void *buf, size_t len)
{
assert(buf != NULL);
uint8_t *buf_bytes = (uint8_t *)buf;
while (len > 0) {
uint32_t word = esp_random();
uint32_t to_copy = MIN(sizeof(word), len);
memcpy(buf_bytes, &word, to_copy);
buf_bytes += to_copy;
len -= to_copy;
}
}

33
components/esp32/include/esp32/cache_err_int.h
View File

@ -1,33 +0,0 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/**
* @brief initialize cache invalid access interrupt
*
* This function enables cache invalid access interrupt source and connects it
* to interrupt input number ETS_MEMACCESS_ERR_INUM (see soc/soc.h). It is called
* from the startup code.
*/
void esp_cache_err_int_init(void);
/**
* @brief get the CPU which caused cache invalid access interrupt
* @return
* - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
* - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
* - (-1) otherwise
*/
int esp_cache_err_get_cpuid(void);

120
components/esp32/ld/esp32_fragments.lf
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@ -1,120 +0,0 @@
[sections:text]
entries:
.text+
.literal+
[sections:data]
entries:
.data+
[sections:bss]
entries:
.bss+
[sections:common]
entries:
COMMON
[sections:legacy_bss]
entries:
.dynsbss
.sbss+
.gnu.linkonce.sb+
.scommon
.sbss2+
.gnu.linkonce.sb2+
.dynbss
.share.mem
.gnu.linkonce.b+
[sections:rodata]
entries:
.rodata+
[sections:rtc_text]
entries:
.rtc.text+
.rtc.literal
[sections:rtc_data]
entries:
.rtc.data+
[sections:rtc_rodata]
entries:
.rtc.rodata+
[sections:rtc_bss]
entries:
.rtc.bss
[sections:iram]
entries:
.iram1+
[sections:iram_data]
entries:
.iram.data+
[sections:iram_bss]
entries:
.iram.bss+
[sections:extram_bss]
entries:
.ext_ram.bss+
[sections:dram]
entries:
.dram1+
[scheme:default]
entries:
if APP_BUILD_USE_FLASH_SECTIONS = y:
text -> flash_text
rodata -> flash_rodata
else:
text -> iram0_text
rodata -> dram0_data
data -> dram0_data
bss -> dram0_bss
common -> dram0_bss
if ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y:
extram_bss -> extern_ram
else:
extram_bss -> dram0_bss
legacy_bss -> dram0_bss
iram -> iram0_text
iram_data -> iram0_data
iram_bss -> iram0_bss
dram -> dram0_data
rtc_text -> rtc_text
rtc_data -> rtc_data
rtc_rodata -> rtc_data
rtc_bss -> rtc_bss
[scheme:rtc]
entries:
text -> rtc_text
data -> rtc_data
rodata -> rtc_data
bss -> rtc_bss
common -> rtc_bss
[scheme:noflash]
entries:
text -> iram0_text
rodata -> dram0_data
[scheme:noflash_data]
entries:
rodata -> dram0_data
[scheme:noflash_text]
entries:
text -> iram0_text
[mapping:default]
archive: *
entries:
* (default)

14
components/esp32/project_include.cmake
View File

@ -15,17 +15,3 @@ if(CONFIG_SPIRAM_CACHE_WORKAROUND)
idf_build_set_property(COMPILE_OPTIONS "-mfix-esp32-psram-cache-strategy=nops" APPEND)
endif()
endif()
# Check toolchain is configured properly in cmake
if(NOT ( ${CMAKE_SYSTEM_NAME} STREQUAL "Generic" AND ${CMAKE_C_COMPILER} MATCHES xtensa))
message(FATAL_ERROR "Internal error, toolchain has not been set correctly by project "
"(or an invalid CMakeCache.txt file has been generated somehow)")
endif()
#
# Warn if the toolchain version doesn't match
#
# TODO: make these platform-specific for diff toolchains
get_expected_ctng_version(expected_toolchain expected_gcc)
gcc_version_check("${expected_gcc}")
crosstool_version_check("${expected_toolchain}")

5
components/esp32/sdkconfig.rename
View File

@ -6,9 +6,6 @@ CONFIG_SPIRAM_SUPPORT CONFIG_ESP32_SPIRAM_SUPP
CONFIG_MEMMAP_TRACEMEM CONFIG_ESP32_MEMMAP_TRACEMEM
CONFIG_MEMMAP_TRACEMEM_TWOBANKS CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS
CONFIG_TRACEMEM_RESERVE_DRAM CONFIG_ESP32_TRACEMEM_RESERVE_DRAM
CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
CONFIG_TWO_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
CONFIG_ESP32_RTC_CLOCK_SOURCE CONFIG_ESP32_RTC_CLK_SRC
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC CONFIG_ESP32_RTC_CLK_SRC_INT_RC
@ -31,7 +28,5 @@ CONFIG_BROWNOUT_DET_LVL_SEL_5 CONFIG_ESP32_BROWNOUT_DE
CONFIG_BROWNOUT_DET_LVL_SEL_6 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6
CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7
CONFIG_BROWNOUT_DET_LVL CONFIG_ESP32_BROWNOUT_DET_LVL
CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP32_REDUCE_PHY_TX_POWER
# SPI RAM config
CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP

12
components/esp32c3/CMakeLists.txt
View File

@ -11,16 +11,11 @@ if(BOOTLOADER_BUILD)
else()
# Regular app build
set(srcs "cache_err_int.c"
"clk.c"
"crosscore_int.c"
"dport_access.c"
set(srcs "dport_access.c"
"esp_hmac.c"
"esp_ds.c"
"esp_crypto_lock.c"
"hw_random.c"
"memprot.c"
"system_api_esp32c3.c")
"memprot.c")
set(include_dirs "include")
set(requires driver efuse soc riscv) #unfortunately rom/uart uses SOC registers directly
@ -32,11 +27,8 @@ else()
app_trace app_update bootloader_support log mbedtls nvs_flash
pthread spi_flash vfs espcoredump esp_common esp_timer)
set(fragments linker.lf ld/esp32c3_fragments.lf)
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS "${include_dirs}"
LDFRAGMENTS "${fragments}"
REQUIRES "${requires}"
PRIV_REQUIRES "${priv_requires}"
REQUIRED_IDF_TARGETS esp32c3)

37
components/esp32c3/Kconfig
View File

@ -48,43 +48,6 @@ menu "ESP32C3-Specific"
default 2 if ESP32C3_REV_MIN_2
default 3 if ESP32C3_REV_MIN_3
choice ESP32C3_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
receive a universally administered MAC address. These are generated sequentially by adding 0
and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
addresses, respectively.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 2 or 4 per device.)
config ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_BT
config ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
bool "Four"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
select ESP_MAC_ADDR_UNIVERSE_BT
select ESP_MAC_ADDR_UNIVERSE_ETH
endchoice
config ESP32C3_UNIVERSAL_MAC_ADDRESSES
int
default 2 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
config ESP32C3_DEBUG_OCDAWARE
bool "Make exception and panic handlers JTAG/OCD aware"
default y

38
components/esp32c3/clk.c
View File

@ -1,38 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "soc/rtc.h"
#include "esp32c3/clk.h"
#include "esp32c3/rom/ets_sys.h"
#define MHZ (1000000)
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return ets_get_cpu_frequency() * MHZ;
}
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(80, ets_get_cpu_frequency()) * MHZ;
}
int IRAM_ATTR esp_clk_xtal_freq(void)
{
return rtc_clk_xtal_freq_get() * MHZ;
}

100
components/esp32c3/crosscore_int.c
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@ -1,100 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "hal/cpu_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#define REASON_YIELD BIT(0)
#define REASON_FREQ_SWITCH BIT(1)
#define REASON_PRINT_BACKTRACE BIT(2)
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t reason[portNUM_PROCESSORS];
// TODO ESP32-C3 IDF-2449
static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
{
portYIELD_FROM_ISR();
}
static void IRAM_ATTR esp_crosscore_isr(void *arg)
{
uint32_t my_reason_val;
//A pointer to the correct reason array item is passed to this ISR.
volatile uint32_t *my_reason = arg;
//Clear the interrupt first.
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
//Grab the reason and clear it.
portENTER_CRITICAL_ISR(&reason_spinlock);
my_reason_val = *my_reason;
*my_reason = 0;
portEXIT_CRITICAL_ISR(&reason_spinlock);
//Check what we need to do.
if (my_reason_val & REASON_YIELD) {
esp_crosscore_isr_handle_yield();
}
if (my_reason_val & REASON_FREQ_SWITCH) {
/* Nothing to do here; the frequency switch event was already
* handled by a hook in xtensa_vectors.S. Could be used in the future
* to allow DFS features without the extra latency of the ISR hook.
*/
}
// TODO: ESP32-C3 IDF-2986
// if (my_reason_val & REASON_PRINT_BACKTRACE) {
// esp_backtrace_print(100);
// }
}
// Initialize the crosscore interrupt on this core.
void esp_crosscore_int_init(void)
{
portENTER_CRITICAL(&reason_spinlock);
reason[cpu_hal_get_core_id()] = 0;
portEXIT_CRITICAL(&reason_spinlock);
ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[0], NULL));
}
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
{
assert(core_id < portNUM_PROCESSORS);
//Mark the reason we interrupt the other CPU
portENTER_CRITICAL(&reason_spinlock);
reason[core_id] |= reason_mask;
portEXIT_CRITICAL(&reason_spinlock);
//Poke the other CPU.
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
}
void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
{
esp_crosscore_int_send(core_id, REASON_YIELD);
}
void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
{
esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
}
void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
{
esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
}

68
components/esp32c3/hw_random.c
View File

@ -1,68 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <stddef.h>
#include <string.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "esp32c3/clk.h"
#include "soc/wdev_reg.h"
#include "hal/cpu_hal.h"
uint32_t IRAM_ATTR esp_random(void)
{
/* The PRNG which implements WDEV_RANDOM register gets 2 bits
* of extra entropy from a hardware randomness source every APB clock cycle
* (provided WiFi or BT are enabled). To make sure entropy is not drained
* faster than it is added, this function needs to wait for at least 16 APB
* clock cycles after reading previous word. This implementation may actually
* wait a bit longer due to extra time spent in arithmetic and branch statements.
*
* As a (probably unncessary) precaution to avoid returning the
* RNG state as-is, the result is XORed with additional
* WDEV_RND_REG reads while waiting.
*/
/* This code does not run in a critical section, so CPU frequency switch may
* happens while this code runs (this will not happen in the current
* implementation, but possible in the future). However if that happens,
* the number of cycles spent on frequency switching will certainly be more
* than the number of cycles we need to wait here.
*/
uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
static uint32_t last_ccount = 0;
uint32_t ccount;
uint32_t result = 0;
do {
ccount = cpu_hal_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
last_ccount = ccount;
return result ^ REG_READ(WDEV_RND_REG);
}
void esp_fill_random(void *buf, size_t len)
{
assert(buf != NULL);
uint8_t *buf_bytes = (uint8_t *)buf;
while (len > 0) {
uint32_t word = esp_random();
uint32_t to_copy = MIN(sizeof(word), len);
memcpy(buf_bytes, &word, to_copy);
buf_bytes += to_copy;
len -= to_copy;
}
}

33
components/esp32c3/include/esp32c3/cache_err_int.h
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@ -1,33 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/**
* @brief initialize cache invalid access interrupt
*
* This function enables cache invalid access interrupt source and connects it
* to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
* from the startup code.
*/
void esp_cache_err_int_init(void);
/**
* @brief get the CPU which caused cache invalid access interrupt
* @return
* - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
* - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
* - (-1) otherwise
*/
int esp_cache_err_get_cpuid(void);

84
components/esp32c3/include/esp32c3/clk.h
View File

@ -1,84 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file esp_clk.h
*
* This file contains declarations of clock related functions.
*/
/**
* @brief Get the calibration value of RTC slow clock
*
* The value is in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
*
* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
* This value is used by timekeeping functions (such as gettimeofday) to
* calculate current time based on RTC counter value.
* @param value calibration value obtained using rtc_clk_cal
*/
void esp_clk_slowclk_cal_set(uint32_t value);
/**
* @brief Return current CPU clock frequency
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return CPU clock frequency, in Hz
*/
int esp_clk_cpu_freq(void);
/**
* @brief Return current APB clock frequency
*
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return APB clock frequency, in Hz
*/
int esp_clk_apb_freq(void);
/**
* @brief Read value of RTC counter, converting it to microseconds
* @attention The value returned by this function may change abruptly when
* calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
* function. This should not happen unless application calls esp_clk_slowclk_cal_set.
* In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time(void);
#ifdef __cplusplus
}
#endif

77
components/esp32c3/include/esp_clk.h
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@ -1,77 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
/**
* @file esp_clk.h
*
* This file contains declarations of clock related functions.
*/
/**
* @brief Get the calibration value of RTC slow clock
*
* The value is in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
*
* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
* This value is used by timekeeping functions (such as gettimeofday) to
* calculate current time based on RTC counter value.
* @param value calibration value obtained using rtc_clk_cal
*/
void esp_clk_slowclk_cal_set(uint32_t value);
/**
* @brief Return current CPU clock frequency
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return CPU clock frequency, in Hz
*/
int esp_clk_cpu_freq(void);
/**
* @brief Return current APB clock frequency
*
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return APB clock frequency, in Hz
*/
int esp_clk_apb_freq(void);
/**
* @brief Read value of RTC counter, converting it to microseconds
* @attention The value returned by this function may change abruptly when
* calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
* function. This should not happen unless application calls esp_clk_slowclk_cal_set.
* In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time(void);

99
components/esp32c3/ld/esp32c3_fragments.lf
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@ -1,99 +0,0 @@
[sections:text]
entries:
.text+
.literal+
[sections:data]
entries:
.data+
[sections:bss]
entries:
.bss+
[sections:common]
entries:
COMMON
[sections:rodata]
entries:
.rodata+
[sections:rtc_text]
entries:
.rtc.text+
.rtc.literal
[sections:rtc_data]
entries:
.rtc.data+
[sections:rtc_rodata]
entries:
.rtc.rodata+
[sections:rtc_bss]
entries:
.rtc.bss
[sections:iram]
entries:
.iram1+
[sections:iram_data]
entries:
.iram.data+
[sections:iram_bss]
entries:
.iram.bss+
[sections:dram]
entries:
.dram1+
[scheme:default]
entries:
if APP_BUILD_USE_FLASH_SECTIONS = y:
text -> flash_text
rodata -> flash_rodata
else:
text -> iram0_text
rodata -> dram0_data
data -> dram0_data
bss -> dram0_bss
common -> dram0_bss
iram -> iram0_text
iram_data -> iram0_data
iram_bss -> iram0_bss
dram -> dram0_data
rtc_text -> rtc_text
rtc_data -> rtc_data
rtc_rodata -> rtc_data
rtc_bss -> rtc_bss
[scheme:rtc]
entries:
text -> rtc_text
data -> rtc_data
rodata -> rtc_data
bss -> rtc_bss
common -> rtc_bss
[scheme:noflash]
entries:
text -> iram0_text
rodata -> dram0_data
[scheme:noflash_data]
entries:
rodata -> dram0_data
[scheme:noflash_text]
entries:
text -> iram0_text
[mapping:default]
archive: *
entries:
* (default)

9
components/esp32c3/linker.lf
View File

@ -1,9 +0,0 @@
[mapping:gcc]
archive: libgcc.a
entries:
lib2funcs (noflash_text)
[mapping:gcov]
archive: libgcov.a
entries:
* (noflash)

25
components/esp32c3/test/test_stack_check.c
View File

@ -1,25 +0,0 @@
#include "unity.h"
#if CONFIG_COMPILER_STACK_CHECK
static void recur_and_smash(void)
{
static int cnt;
volatile uint8_t buf[50];
volatile int num = sizeof(buf)+10;
if (cnt++ < 1) {
recur_and_smash();
}
for (int i = 0; i < num; i++) {
buf[i] = 0;
}
}
TEST_CASE("stack smashing protection", "[stack_check] [ignore]")
{
recur_and_smash();
}
#endif

25
components/esp32c3/test/test_stack_check_cxx.cpp
View File

@ -1,25 +0,0 @@
#include "unity.h"
#if CONFIG_COMPILER_STACK_CHECK
static void recur_and_smash_cxx(void)
{
static int cnt;
volatile uint8_t buf[50];
volatile int num = sizeof(buf)+10;
if (cnt++ < 1) {
recur_and_smash_cxx();
}
for (int i = 0; i < num; i++) {
buf[i] = 0;
}
}
TEST_CASE("stack smashing protection CXX", "[stack_check] [ignore]")
{
recur_and_smash_cxx();
}
#endif

10
components/esp32s2/CMakeLists.txt
View File

@ -11,15 +11,10 @@ if(BOOTLOADER_BUILD)
else()
# Regular app build
set(srcs "cache_err_int.c"
"memprot.c"
"clk.c"
"crosscore_int.c"
set(srcs "memprot.c"
"dport_access.c"
"hw_random.c"
"spiram.c"
"spiram_psram.c"
"system_api_esp32s2.c"
"esp_crypto_lock.c"
"esp_hmac.c"
"esp_ds.c")
@ -34,11 +29,8 @@ else()
app_trace app_update bootloader_support esp_system log mbedtls nvs_flash
pthread spi_flash vfs espcoredump esp_common esp_timer)
set(fragments linker.lf ld/esp32s2_fragments.lf)
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS "${include_dirs}"
LDFRAGMENTS "${fragments}"
REQUIRES "${requires}"
PRIV_REQUIRES "${priv_requires}"
REQUIRED_IDF_TARGETS esp32s2)

31
components/esp32s2/Kconfig
View File

@ -221,37 +221,6 @@ menu "ESP32S2-specific"
default 0x0
choice ESP32S2_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is Two, all interfaces (WiFi station, WiFi softap) receive a
universally administered MAC address. They are generated sequentially by adding 0, and 1 (respectively)
to the final octet of the base MAC address. If the number of universal MAC addresses is one,
only WiFi station receives a universally administered MAC address.
It's generated by adding 0 to the base MAC address.
The WiFi softap receives local MAC addresses. It's derived from the universal WiFi station MAC addresses.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 1 or 2 per device.)
config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
bool "One"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
endchoice
config ESP32S2_UNIVERSAL_MAC_ADDRESSES
int
default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
config ESP32S2_ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default "n"

46
components/esp32s2/clk.c
View File

@ -1,46 +0,0 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "soc/rtc.h"
#include "esp32s2/clk.h"
#define MHZ (1000000)
// g_ticks_us defined in ROMs
extern uint32_t g_ticks_per_us_pro;
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return g_ticks_per_us_pro * MHZ;
}
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(g_ticks_per_us_pro, 80) * MHZ;
}
int IRAM_ATTR esp_clk_xtal_freq(void)
{
return rtc_clk_xtal_freq_get() * MHZ;
}
void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
{
/* Update scale factors used by esp_rom_delay_us */
g_ticks_per_us_pro = ticks_per_us;
}

109
components/esp32s2/crosscore_int.c
View File

@ -1,109 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <string.h>
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "esp_debug_helpers.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/periph_defs.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#define REASON_YIELD BIT(0)
#define REASON_FREQ_SWITCH BIT(1)
#define REASON_PRINT_BACKTRACE BIT(2)
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t reason;
/*
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
*/
static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
{
portYIELD_FROM_ISR();
}
static void IRAM_ATTR esp_crosscore_isr(void *arg) {
uint32_t my_reason_val;
//A pointer to the correct reason item is passed to this ISR.
volatile uint32_t *my_reason=arg;
//Clear the interrupt first.
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
//Grab the reason and clear it.
portENTER_CRITICAL_ISR(&reason_spinlock);
my_reason_val=*my_reason;
*my_reason=0;
portEXIT_CRITICAL_ISR(&reason_spinlock);
//Check what we need to do.
if (my_reason_val & REASON_YIELD) {
esp_crosscore_isr_handle_yield();
}
if (my_reason_val & REASON_FREQ_SWITCH) {
/* Nothing to do here; the frequency switch event was already
* handled by a hook in xtensa_vectors.S. Could be used in the future
* to allow DFS features without the extra latency of the ISR hook.
*/
}
if (my_reason_val & REASON_PRINT_BACKTRACE) {
esp_backtrace_print(100);
}
}
//Initialize the crosscore interrupt on this core.
void esp_crosscore_int_init(void) {
portENTER_CRITICAL(&reason_spinlock);
reason = 0;
portEXIT_CRITICAL(&reason_spinlock);
ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason, NULL));
}
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
assert(core_id<portNUM_PROCESSORS);
//Mark the reason we interrupt the current CPU
portENTER_CRITICAL(&reason_spinlock);
reason |= reason_mask;
portEXIT_CRITICAL(&reason_spinlock);
//Poke the current CPU.
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
}
void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
{
esp_crosscore_int_send(core_id, REASON_YIELD);
}
void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
{
esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
}
void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
{
esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
}

84
components/esp32s2/include/esp32s2/clk.h
View File

@ -1,84 +0,0 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file esp_clk.h
*
* This file contains declarations of clock related functions.
*/
/**
* @brief Get the calibration value of RTC slow clock
*
* The value is in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
*
* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
* This value is used by timekeeping functions (such as gettimeofday) to
* calculate current time based on RTC counter value.
* @param value calibration value obtained using rtc_clk_cal
*/
void esp_clk_slowclk_cal_set(uint32_t value);
/**
* @brief Return current CPU clock frequency
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return CPU clock frequency, in Hz
*/
int esp_clk_cpu_freq(void);
/**
* @brief Return current APB clock frequency
*
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return APB clock frequency, in Hz
*/
int esp_clk_apb_freq(void);
/**
* @brief Read value of RTC counter, converting it to microseconds
* @attention The value returned by this function may change abruptly when
* calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
* function. This should not happen unless application calls esp_clk_slowclk_cal_set.
* In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time(void);
#ifdef __cplusplus
}
#endif

83
components/esp32s2/include/esp_clk.h
View File

@ -1,83 +0,0 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file esp_clk.h
*
* This file contains declarations of clock related functions.
*/
/**
* @brief Get the calibration value of RTC slow clock
*
* The value is in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
*
* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
* This value is used by timekeeping functions (such as gettimeofday) to
* calculate current time based on RTC counter value.
* @param value calibration value obtained using rtc_clk_cal
*/
void esp_clk_slowclk_cal_set(uint32_t value);
/**
* @brief Return current CPU clock frequency
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return CPU clock frequency, in Hz
*/
int esp_clk_cpu_freq(void);
/**
* @brief Return current APB clock frequency
*
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return APB clock frequency, in Hz
*/
int esp_clk_apb_freq(void);
/**
* @brief Read value of RTC counter, converting it to microseconds
* @attention The value returned by this function may change abruptly when
* calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
* function. This should not happen unless application calls esp_clk_slowclk_cal_set.
* In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time(void);
#ifdef __cplusplus
}
#endif

9
components/esp32s2/linker.lf
View File

@ -1,9 +0,0 @@
[mapping:gcc]
archive: libgcc.a
entries:
lib2funcs (noflash_text)
[mapping:gcov]
archive: libgcov.a
entries:
* (noflash)

66
components/esp32s2/test/test_random.c
View File

@ -1,66 +0,0 @@
#include <stdio.h>
#include <string.h>
#include "unity.h"
#include "esp_system.h"
/* Note: these are just sanity tests, not the same as
entropy tests
*/
TEST_CASE("call esp_random()", "[random]")
{
const size_t NUM_RANDOM = 128; /* in most cases this is massive overkill */
uint32_t zeroes = UINT32_MAX;
uint32_t ones = 0;
for (int i = 0; i < NUM_RANDOM - 1; i++) {
uint32_t r = esp_random();
ones |= r;
zeroes &= ~r;
}
/* assuming a 'white' random distribution, we can expect
usually at least one time each bit will be zero and at
least one time each will be one. Statistically this
can still fail, just *very* unlikely to. */
TEST_ASSERT_EQUAL_HEX32(0, zeroes);
TEST_ASSERT_EQUAL_HEX32(UINT32_MAX, ones);
}
TEST_CASE("call esp_fill_random()", "[random]")
{
const size_t NUM_BUF = 200;
const size_t BUF_SZ = 16;
uint8_t buf[NUM_BUF][BUF_SZ];
uint8_t zero_buf[BUF_SZ];
uint8_t one_buf[BUF_SZ];
bzero(buf, sizeof(buf));
bzero(one_buf, sizeof(zero_buf));
memset(zero_buf, 0xFF, sizeof(one_buf));
for (int i = 0; i < NUM_BUF; i++) {
esp_fill_random(buf[i], BUF_SZ);
}
/* No two 128-bit buffers should be the same
(again, statistically this could happen but it's very unlikely) */
for (int i = 0; i < NUM_BUF; i++) {
for (int j = 0; j < NUM_BUF; j++) {
if (i != j) {
TEST_ASSERT_NOT_EQUAL(0, memcmp(buf[i], buf[j], BUF_SZ));
}
}
}
/* Do the same all bits are zero and one at least once test across the buffers */
for (int i = 0; i < NUM_BUF; i++) {
for (int x = 0; x < BUF_SZ; x++) {
zero_buf[x] &= ~buf[i][x];
one_buf[x] |= buf[i][x];
}
}
for (int x = 0; x < BUF_SZ; x++) {
TEST_ASSERT_EQUAL_HEX8(0, zero_buf[x]);
TEST_ASSERT_EQUAL_HEX8(0xFF, one_buf[x]);
}
}

25
components/esp32s2/test/test_stack_check.c
View File

@ -1,25 +0,0 @@
#include "unity.h"
#if CONFIG_COMPILER_STACK_CHECK
static void recur_and_smash(void)
{
static int cnt;
volatile uint8_t buf[50];
volatile int num = sizeof(buf)+10;
if (cnt++ < 1) {
recur_and_smash();
}
for (int i = 0; i < num; i++) {
buf[i] = 0;
}
}
TEST_CASE("stack smashing protection", "[stack_check] [ignore]")
{
recur_and_smash();
}
#endif

25
components/esp32s2/test/test_stack_check_cxx.cpp
View File

@ -1,25 +0,0 @@
#include "unity.h"
#if CONFIG_COMPILER_STACK_CHECK
static void recur_and_smash_cxx(void)
{
static int cnt;
volatile uint8_t buf[50];
volatile int num = sizeof(buf)+10;
if (cnt++ < 1) {
recur_and_smash_cxx();
}
for (int i = 0; i < num; i++) {
buf[i] = 0;
}
}
TEST_CASE("stack smashing protection CXX", "[stack_check] [ignore]")
{
recur_and_smash_cxx();
}
#endif

12
components/esp32s3/CMakeLists.txt
View File

@ -12,17 +12,11 @@ if(BOOTLOADER_BUILD)
else()
# Regular app build
set(srcs "cache_err_int.c"
"clk.c"
"crosscore_int.c"
"dport_access.c"
set(srcs "dport_access.c"
"esp_crypto_lock.c"
"hw_random.c"
"memprot.c"
"spiram.c"
"spiram_psram.c"
"system_api_esp32s3.c")
"spiram_psram.c")
set(include_dirs "include")
set(requires driver efuse soc xtensa) #unfortunately rom/uart uses SOC registers directly
@ -32,11 +26,9 @@ else()
# esp_timer is added here because cpu_start.c uses esp_timer
set(priv_requires app_trace app_update bootloader_support log mbedtls nvs_flash pthread
spi_flash vfs espcoredump esp_common perfmon esp_timer esp_ipc)
set(fragments linker.lf ld/esp32s3_fragments.lf)
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS "${include_dirs}"
LDFRAGMENTS "${fragments}"
REQUIRES "${requires}"
PRIV_REQUIRES "${priv_requires}"
REQUIRED_IDF_TARGETS esp32s3)

36
components/esp32s3/Kconfig
View File

@ -282,42 +282,6 @@ menu "ESP32S3-Specific"
default 0x0
choice ESP32S3_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
receive a universally administered MAC address. These are generated sequentially by adding 0
and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
addresses, respectively.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 2 or 4 per device.)
config ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_BT
config ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR
bool "Four"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
select ESP_MAC_ADDR_UNIVERSE_BT
select ESP_MAC_ADDR_UNIVERSE_ETH
endchoice
config ESP32S3_UNIVERSAL_MAC_ADDRESSES
int
default 2 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR
config ESP32S3_ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default "n"

38
components/esp32s3/clk.c
View File

@ -1,38 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "esp32s3/clk.h"
#include "esp32s3/rom/ets_sys.h"
#include "soc/rtc.h"
#define MHZ (1000000)
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return ets_get_cpu_frequency() * MHZ;
}
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(ets_get_cpu_frequency(), 80) * MHZ;
}
int IRAM_ATTR esp_clk_xtal_freq(void)
{
return rtc_clk_xtal_freq_get() * MHZ;
}

111
components/esp32s3/crosscore_int.c
View File

@ -1,111 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "esp_debug_helpers.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "hal/cpu_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#define REASON_YIELD BIT(0)
#define REASON_FREQ_SWITCH BIT(1)
#define REASON_PRINT_BACKTRACE BIT(2)
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t reason[portNUM_PROCESSORS];
static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
{
portYIELD_FROM_ISR();
}
static void IRAM_ATTR esp_crosscore_isr(void *arg)
{
uint32_t my_reason_val;
//A pointer to the correct reason array item is passed to this ISR.
volatile uint32_t *my_reason = arg;
//Clear the interrupt first.
if (cpu_hal_get_core_id() == 0) {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
} else {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
}
//Grab the reason and clear it.
portENTER_CRITICAL_ISR(&reason_spinlock);
my_reason_val = *my_reason;
*my_reason = 0;
portEXIT_CRITICAL_ISR(&reason_spinlock);
//Check what we need to do.
if (my_reason_val & REASON_YIELD) {
esp_crosscore_isr_handle_yield();
}
if (my_reason_val & REASON_FREQ_SWITCH) {
/* Nothing to do here; the frequency switch event was already
* handled by a hook in xtensa_vectors.S. Could be used in the future
* to allow DFS features without the extra latency of the ISR hook.
*/
}
if (my_reason_val & REASON_PRINT_BACKTRACE) {
esp_backtrace_print(100);
}
}
// Initialize the crosscore interrupt on this core.
void esp_crosscore_int_init(void)
{
portENTER_CRITICAL(&reason_spinlock);
reason[cpu_hal_get_core_id()] = 0;
portEXIT_CRITICAL(&reason_spinlock);
if (cpu_hal_get_core_id() == 0) {
ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[0], NULL));
} else {
ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[1], NULL));
}
}
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
{
assert(core_id < portNUM_PROCESSORS);
//Mark the reason we interrupt the other CPU
portENTER_CRITICAL(&reason_spinlock);
reason[core_id] |= reason_mask;
portEXIT_CRITICAL(&reason_spinlock);
//Poke the other CPU.
if (core_id == 0) {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
} else {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
}
}
void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
{
esp_crosscore_int_send(core_id, REASON_YIELD);
}
void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
{
esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
}
void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
{
esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
}

69
components/esp32s3/hw_random.c
View File

@ -1,69 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <stddef.h>
#include <string.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "hal/cpu_hal.h"
#include "esp32s3/clk.h"
#include "soc/wdev_reg.h"
uint32_t IRAM_ATTR esp_random(void)
{
/* The PRNG which implements WDEV_RANDOM register gets 2 bits
* of extra entropy from a hardware randomness source every APB clock cycle
* (provided WiFi or BT are enabled). To make sure entropy is not drained
* faster than it is added, this function needs to wait for at least 16 APB
* clock cycles after reading previous word. This implementation may actually
* wait a bit longer due to extra time spent in arithmetic and branch statements.
*
* As a (probably unncessary) precaution to avoid returning the
* RNG state as-is, the result is XORed with additional
* WDEV_RND_REG reads while waiting.
*/
/* This code does not run in a critical section, so CPU frequency switch may
* happens while this code runs (this will not happen in the current
* implementation, but possible in the future). However if that happens,
* the number of cycles spent on frequency switching will certainly be more
* than the number of cycles we need to wait here.
*/
uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
static uint32_t last_ccount = 0;
uint32_t ccount;
uint32_t result = 0;
do {
ccount = cpu_hal_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
last_ccount = ccount;
return result ^ REG_READ(WDEV_RND_REG);
}
void esp_fill_random(void *buf, size_t len)
{
assert(buf != NULL);
uint8_t *buf_bytes = (uint8_t *)buf;
while (len > 0) {
uint32_t word = esp_random();
uint32_t to_copy = MIN(sizeof(word), len);
memcpy(buf_bytes, &word, to_copy);
buf_bytes += to_copy;
len -= to_copy;
}
}

33
components/esp32s3/include/esp32s3/cache_err_int.h
View File

@ -1,33 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/**
* @brief initialize cache invalid access interrupt
*
* This function enables cache invalid access interrupt source and connects it
* to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
* from the startup code.
*/
void esp_cache_err_int_init(void);
/**
* @brief get the CPU which caused cache invalid access interrupt
* @return
* - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
* - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
* - (-1) otherwise
*/
int esp_cache_err_get_cpuid(void);

84
components/esp32s3/include/esp32s3/clk.h
View File

@ -1,84 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file esp_clk.h
*
* This file contains declarations of clock related functions.
*/
/**
* @brief Get the calibration value of RTC slow clock
*
* The value is in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
*
* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
* This value is used by timekeeping functions (such as gettimeofday) to
* calculate current time based on RTC counter value.
* @param value calibration value obtained using rtc_clk_cal
*/
void esp_clk_slowclk_cal_set(uint32_t value);
/**
* @brief Return current CPU clock frequency
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return CPU clock frequency, in Hz
*/
int esp_clk_cpu_freq(void);
/**
* @brief Return current APB clock frequency
*
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return APB clock frequency, in Hz
*/
int esp_clk_apb_freq(void);
/**
* @brief Read value of RTC counter, converting it to microseconds
* @attention The value returned by this function may change abruptly when
* calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
* function. This should not happen unless application calls esp_clk_slowclk_cal_set.
* In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time(void);
#ifdef __cplusplus
}
#endif

77
components/esp32s3/include/esp_clk.h
View File

@ -1,77 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
/**
* @file esp_clk.h
*
* This file contains declarations of clock related functions.
*/
/**
* @brief Get the calibration value of RTC slow clock
*
* The value is in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
*
* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
* in Q13.19 fixed-point format).
* This value is used by timekeeping functions (such as gettimeofday) to
* calculate current time based on RTC counter value.
* @param value calibration value obtained using rtc_clk_cal
*/
void esp_clk_slowclk_cal_set(uint32_t value);
/**
* @brief Return current CPU clock frequency
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return CPU clock frequency, in Hz
*/
int esp_clk_cpu_freq(void);
/**
* @brief Return current APB clock frequency
*
* When frequency switching is performed, this frequency may change.
* However it is guaranteed that the frequency never changes with a critical
* section.
*
* @return APB clock frequency, in Hz
*/
int esp_clk_apb_freq(void);
/**
* @brief Read value of RTC counter, converting it to microseconds
* @attention The value returned by this function may change abruptly when
* calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
* function. This should not happen unless application calls esp_clk_slowclk_cal_set.
* In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time(void);

99
components/esp32s3/ld/esp32s3_fragments.lf
View File

@ -1,99 +0,0 @@
[sections:text]
entries:
.text+
.literal+
[sections:data]
entries:
.data+
[sections:bss]
entries:
.bss+
[sections:common]
entries:
COMMON
[sections:rodata]
entries:
.rodata+
[sections:rtc_text]
entries:
.rtc.text+
.rtc.literal
[sections:rtc_data]
entries:
.rtc.data+
[sections:rtc_rodata]
entries:
.rtc.rodata+
[sections:rtc_bss]
entries:
.rtc.bss
[sections:iram]
entries:
.iram1+
[sections:iram_data]
entries:
.iram.data+
[sections:iram_bss]
entries:
.iram.bss+
[sections:dram]
entries:
.dram1+
[scheme:default]
entries:
if APP_BUILD_USE_FLASH_SECTIONS = y:
text -> flash_text
rodata -> flash_rodata
else:
text -> iram0_text
rodata -> dram0_data
data -> dram0_data
bss -> dram0_bss
common -> dram0_bss
iram -> iram0_text
iram_data -> iram0_data
iram_bss -> iram0_bss
dram -> dram0_data
rtc_text -> rtc_text
rtc_data -> rtc_data
rtc_rodata -> rtc_data
rtc_bss -> rtc_bss
[scheme:rtc]
entries:
text -> rtc_text
data -> rtc_data
rodata -> rtc_data
bss -> rtc_bss
common -> rtc_bss
[scheme:noflash]
entries:
text -> iram0_text
rodata -> dram0_data
[scheme:noflash_data]
entries:
rodata -> dram0_data
[scheme:noflash_text]
entries:
text -> iram0_text
[mapping:default]
archive: *
entries:
* (default)

9
components/esp32s3/linker.lf
View File

@ -1,9 +0,0 @@
[mapping:gcc]
archive: libgcc.a
entries:
lib2funcs (noflash_text)
[mapping:gcov]
archive: libgcov.a
entries:
* (noflash)

3
components/esp_common/CMakeLists.txt
View File

@ -5,7 +5,8 @@ list(APPEND srcs "src/esp_err_to_name.c")
# Note: esp_ipc, esp_pm added as a public requirement to keep compatibility as to be located here.
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS include
REQUIRES ${target})
REQUIRES ${target}
LDFRAGMENTS "common.lf" "soc.lf")
set_property(TARGET ${COMPONENT_LIB} APPEND PROPERTY LINK_INTERFACE_MULTIPLICITY 4)

34
components/esp_common/common.lf Normal file
View File

@ -0,0 +1,34 @@
# Sections emitted by compiler by default.
[sections:text]
entries:
.text+
.literal+
[sections:data]
entries:
.data+
[sections:bss]
entries:
.bss+
[sections:common]
entries:
COMMON
[sections:legacy_bss]
entries:
.dynsbss
.sbss+
.gnu.linkonce.sb+
.scommon
.sbss2+
.gnu.linkonce.sb2+
.dynbss
.share.mem
.gnu.linkonce.b+
[sections:rodata]
entries:
.rodata+

2
components/esp_common/component.mk
View File

@ -4,3 +4,5 @@
COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_SRCDIRS := src
COMPONENT_ADD_LDFRAGMENTS += common.lf soc.lf

6
components/esp_common/project_include.cmake Normal file
View File

@ -0,0 +1,6 @@
#
# Warn if the toolchain version doesn't match
#
get_expected_ctng_version(expected_toolchain expected_gcc)
gcc_version_check("${expected_gcc}")
crosstool_version_check("${expected_toolchain}")

43
components/esp_common/soc.lf Normal file
View File

@ -0,0 +1,43 @@
# Sections that can be placed in memory regions common
# to supported SoCs. This is here since some of counterpart attributes
# are in esp_attr.h.
#
# Ideally esp_attr.h would be split between this component and `soc`.
# Those moved to `soc` are the counterpart attributes to these sections.
[sections:rtc_text]
entries:
.rtc.text+
.rtc.literal
[sections:rtc_data]
entries:
.rtc.data+
[sections:rtc_rodata]
entries:
.rtc.rodata+
[sections:rtc_bss]
entries:
.rtc.bss
[sections:iram]
entries:
.iram1+
[sections:iram_data]
entries:
.iram.data+
[sections:iram_bss]
entries:
.iram.bss+
[sections:dram]
entries:
.dram1+
[sections:extram_bss]
entries:
.ext_ram.bss+

4
components/esp_hw_support/CMakeLists.txt
View File

@ -7,11 +7,11 @@ endif()
set(srcs "compare_set.c" "cpu_util.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "clk_ctrl_os.c" "mac_addr.c")
list(APPEND srcs "esp_clk.c" "clk_ctrl_os.c" "mac_addr.c" "hw_random.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS include
INCLUDE_DIRS include include/soc
REQUIRES ${requires}
PRIV_REQUIRES efuse
LDFRAGMENTS linker.lf)

3
components/esp_hw_support/Kconfig
View File

@ -11,5 +11,8 @@ menu "Hardware Settings"
config ESP_MAC_ADDR_UNIVERSE_ETH
bool
# Insert chip-specific MAC config
rsource "./port/$IDF_TARGET/Kconfig.mac"
endmenu
endmenu

2
components/esp_hw_support/component.mk
View File

@ -1,5 +1,5 @@
COMPONENT_SRCDIRS := . port/$(IDF_TARGET)
COMPONENT_ADD_INCLUDEDIRS := . include port/$(IDF_TARGET)/private_include
COMPONENT_ADD_INCLUDEDIRS := . include include/soc port/$(IDF_TARGET)/private_include
COMPONENT_ADD_LDFRAGMENTS := linker.lf
port/$(IDF_TARGET)/rtc_clk.o: CFLAGS += -fno-jump-tables -fno-tree-switch-conversion

139
components/esp_hw_support/esp_clk.c Normal file
View File

@ -0,0 +1,139 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "soc/rtc.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/rtc.h"
#include "esp32/clk.h"
#include "esp32/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#include "esp32s2/clk.h"
#include "esp32s2/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#include "esp32s3/clk.h"
#include "esp32s3/rtc.h"
#include "esp32s3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#include "esp32c3/clk.h"
#include "esp32c3/rtc.h"
#endif
#define MHZ (1000000)
// g_ticks_us defined in ROMs for PRO and APP CPU
extern uint32_t g_ticks_per_us_pro;
#if CONFIG_IDF_TARGET_ESP32
#ifndef CONFIG_FREERTOS_UNICORE
extern uint32_t g_ticks_per_us_app;
#endif
#endif
static _lock_t s_esp_rtc_time_lock;
static RTC_DATA_ATTR uint64_t s_esp_rtc_time_us = 0, s_rtc_last_ticks = 0;
int IRAM_ATTR esp_clk_cpu_freq(void)
{
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
return ets_get_cpu_frequency() * MHZ;
#else
return g_ticks_per_us_pro * MHZ;
#endif
}
int IRAM_ATTR esp_clk_apb_freq(void)
{
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
return MIN(ets_get_cpu_frequency(), 81) * MHZ;
#else
return MIN(g_ticks_per_us_pro, 80) * MHZ;
#endif
}
int IRAM_ATTR esp_clk_xtal_freq(void)
{
return rtc_clk_xtal_freq_get() * MHZ;
}
#ifndef CONFIG_IDF_TARGET_ESP32C3
void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
{
/* Update scale factors used by esp_rom_delay_us */
g_ticks_per_us_pro = ticks_per_us;
#if CONFIG_IDF_TARGET_ESP32
#ifndef CONFIG_FREERTOS_UNICORE
g_ticks_per_us_app = ticks_per_us;
#endif
#endif
}
#endif
uint64_t esp_rtc_get_time_us(void)
{
_lock_acquire(&s_esp_rtc_time_lock);
const uint32_t cal = esp_clk_slowclk_cal_get();
const uint64_t rtc_this_ticks = rtc_time_get();
const uint64_t ticks = rtc_this_ticks - s_rtc_last_ticks;
/* RTC counter result is up to 2^48, calibration factor is up to 2^24,
* for a 32kHz clock. We need to calculate (assuming no overflow):
* (ticks * cal) >> RTC_CLK_CAL_FRACT
*
* An overflow in the (ticks * cal) multiplication would cause time to
* wrap around after approximately 13 days, which is probably not enough
* for some applications.
* Therefore multiplication is split into two terms, for the lower 32-bit
* and the upper 16-bit parts of "ticks", i.e.:
* ((ticks_low + 2^32 * ticks_high) * cal) >> RTC_CLK_CAL_FRACT
*/
const uint64_t ticks_low = ticks & UINT32_MAX;
const uint64_t ticks_high = ticks >> 32;
const uint64_t delta_time_us = ((ticks_low * cal) >> RTC_CLK_CAL_FRACT) +
((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT));
s_esp_rtc_time_us += delta_time_us;
s_rtc_last_ticks = rtc_this_ticks;
_lock_release(&s_esp_rtc_time_lock);
return s_esp_rtc_time_us;
}
void esp_clk_slowclk_cal_set(uint32_t new_cal)
{
#if defined(CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER)
/* To force monotonic time values even when clock calibration value changes,
* we adjust esp_rtc_time
*/
esp_rtc_get_time_us();
#endif // CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER
REG_WRITE(RTC_SLOW_CLK_CAL_REG, new_cal);
}
uint32_t esp_clk_slowclk_cal_get(void)
{
return REG_READ(RTC_SLOW_CLK_CAL_REG);
}
uint64_t esp_clk_rtc_time(void)
{
#ifdef CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER
return esp_rtc_get_time_us();
#else
return 0;
#endif
}

11
components/esp32s2/hw_random.c → components/esp_hw_support/hw_random.c
View File

@ -19,9 +19,18 @@
#include <sys/param.h>
#include "esp_attr.h"
#include "hal/cpu_hal.h"
#include "esp32s2/clk.h"
#include "soc/wdev_reg.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/clk.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/clk.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/clk.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/clk.h"
#endif
uint32_t IRAM_ATTR esp_random(void)
{
/* The PRNG which implements WDEV_RANDOM register gets 2 bits

72
components/esp_hw_support/include/esp_chip_info.h Normal file
View File

@ -0,0 +1,72 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdbool.h>
#include <stdint.h>
#include "sdkconfig.h"
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Chip models
*/
typedef enum {
CHIP_ESP32 = 1, //!< ESP32
CHIP_ESP32S2 = 2, //!< ESP32-S2
CHIP_ESP32S3 = 4, //!< ESP32-S3
CHIP_ESP32C3 = 5, //!< ESP32-C3
} esp_chip_model_t;
/* Chip feature flags, used in esp_chip_info_t */
#define CHIP_FEATURE_EMB_FLASH BIT(0) //!< Chip has embedded flash memory
#define CHIP_FEATURE_WIFI_BGN BIT(1) //!< Chip has 2.4GHz WiFi
#define CHIP_FEATURE_BLE BIT(4) //!< Chip has Bluetooth LE
#define CHIP_FEATURE_BT BIT(5) //!< Chip has Bluetooth Classic
/**
* @brief The structure represents information about the chip
*/
typedef struct {
esp_chip_model_t model; //!< chip model, one of esp_chip_model_t
uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags
uint8_t cores; //!< number of CPU cores
uint8_t revision; //!< chip revision number
} esp_chip_info_t;
/**
* @brief Fill an esp_chip_info_t structure with information about the chip
* @param[out] out_info structure to be filled
*/
void esp_chip_info(esp_chip_info_t* out_info);
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
/**
* @brief Cache lock bug exists or not
*
* @return
* - ture : bug exists
* - false : bug not exists
*/
bool soc_has_cache_lock_bug(void);
#endif
#ifdef __cplusplus
}
#endif

0
components/esp32/include/esp_clk.h → components/esp_hw_support/include/esp_clk.h
View File

0
components/esp32/include/esp_intr.h → components/esp_hw_support/include/esp_intr.h
View File

134
components/esp_hw_support/include/esp_mac.h Normal file
View File

@ -0,0 +1,134 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "esp_err.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ESP_MAC_WIFI_STA,
ESP_MAC_WIFI_SOFTAP,
ESP_MAC_BT,
ESP_MAC_ETH,
} esp_mac_type_t;
/** @cond */
#define TWO_UNIVERSAL_MAC_ADDR 2
#define FOUR_UNIVERSAL_MAC_ADDR 4
#if CONFIG_IDF_TARGET_ESP32
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32S2
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32S3
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32C3
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES
#endif
/** @endcond */
/**
* @brief Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or
* external storage e.g. flash and EEPROM.
*
* Base MAC address is used to generate the MAC addresses used by the networking interfaces.
* If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC
* address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing
* WiFi/BT/Ethernet.
*
* @note Base MAC must be a unicast MAC (least significant bit of first byte must be zero).
*
* @note If not using a valid OUI, set the "locally administered" bit
* (bit value 0x02 in the first byte) to avoid collisions.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_ARG If mac is NULL or is not a unicast MAC
*/
esp_err_t esp_base_mac_addr_set(const uint8_t *mac);
/**
* @brief Return base MAC address which is set using esp_base_mac_addr_set.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_MAC base MAC address has not been set
*/
esp_err_t esp_base_mac_addr_get(uint8_t *mac);
/**
* @brief Return base MAC address which was previously written to BLK3 of EFUSE.
*
* Base MAC address is used to generate the MAC addresses used by the networking interfaces.
* This API returns the custom base MAC address which was previously written to BLK3 of EFUSE.
* Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also
* possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE
* ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE
*/
esp_err_t esp_efuse_mac_get_custom(uint8_t *mac);
/**
* @brief Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
*/
esp_err_t esp_efuse_mac_get_default(uint8_t *mac);
/**
* @brief Read base MAC address and set MAC address of the interface.
*
* This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address
* from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,
* bluetooth and ethernet.
*
* @param mac MAC address of the interface, length: 6 bytes.
* @param type type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet.
*
* @return ESP_OK on success
*/
esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type);
/**
* @brief Derive local MAC address from universal MAC address.
*
* This function derives a local MAC address from an universal MAC address.
* A `definition of local vs universal MAC address can be found on Wikipedia
* <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`.
* In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage.
* Local MAC address is derived from the universal MAC address.
*
* @param local_mac Derived local MAC address, length: 6 bytes.
* @param universal_mac Source universal MAC address, length: 6 bytes.
*
* @return ESP_OK on success
*/
esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac);
#ifdef __cplusplus
}
#endif

2
components/esp32/include/esp32/clk.h → components/esp_hw_support/include/esp_private/esp_clk.h
View File

@ -20,7 +20,7 @@ extern "C" {
#endif
/**
* @file esp32/clk.h
* @file esp_clk.h
*
* This file contains declarations of clock related functions.
*/

54
components/esp_hw_support/include/esp_random.h Normal file
View File

@ -0,0 +1,54 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stddef.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get one random 32-bit word from hardware RNG
*
* The hardware RNG is fully functional whenever an RF subsystem is running (ie Bluetooth or WiFi is enabled). For
* random values, call this function after WiFi or Bluetooth are started.
*
* If the RF subsystem is not used by the program, the function bootloader_random_enable() can be called to enable an
* entropy source. bootloader_random_disable() must be called before RF subsystem or I2S peripheral are used. See these functions'
* documentation for more details.
*
* Any time the app is running without an RF subsystem (or bootloader_random) enabled, RNG hardware should be
* considered a PRNG. A very small amount of entropy is available due to pre-seeding while the IDF
* bootloader is running, but this should not be relied upon for any use.
*
* @return Random value between 0 and UINT32_MAX
*/
uint32_t esp_random(void);
/**
* @brief Fill a buffer with random bytes from hardware RNG
*
* @note This function has the same restrictions regarding available entropy as esp_random()
*
* @param buf Pointer to buffer to fill with random numbers.
* @param len Length of buffer in bytes
*/
void esp_fill_random(void *buf, size_t len);
#ifdef __cplusplus
}
#endif

7
components/esp32s2/include/esp_intr.h → components/esp_hw_support/include/soc/esp32/clk.h
View File

@ -1,9 +1,9 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -13,5 +13,4 @@
// limitations under the License.
#pragma once
#warning esp_intr.h is deprecated, please include esp_intr_alloc.h instead
#include "esp_intr_alloc.h"
#include "esp_private/esp_clk.h"

21
components/esp32c3/include/esp32c3/brownout.h → components/esp_hw_support/include/soc/esp32c3/clk.h
View File

@ -1,4 +1,4 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -12,20 +12,5 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_BROWNOUT_H
#define __ESP_BROWNOUT_H
#ifdef __cplusplus
extern "C" {
#endif
void esp_brownout_init(void);
void esp_brownout_disable(void);
#ifdef __cplusplus
}
#endif
#endif
#pragma once
#include "esp_private/esp_clk.h"

21
components/esp32s3/include/esp32s3/brownout.h → components/esp_hw_support/include/soc/esp32s2/clk.h
View File

@ -1,4 +1,4 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -12,20 +12,5 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_BROWNOUT_H
#define __ESP_BROWNOUT_H
#ifdef __cplusplus
extern "C" {
#endif
void esp_brownout_init(void);
void esp_brownout_disable(void);
#ifdef __cplusplus
}
#endif
#endif
#pragma once
#include "esp_private/esp_clk.h"

23
components/esp32/include/esp32/brownout.h → components/esp_hw_support/include/soc/esp32s3/clk.h
View File

@ -1,9 +1,9 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -12,20 +12,5 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_BROWNOUT_H
#define __ESP_BROWNOUT_H
#ifdef __cplusplus
extern "C" {
#endif
void esp_brownout_init(void);
void esp_brownout_disable(void);
#ifdef __cplusplus
}
#endif
#endif
#pragma once
#include "esp_private/esp_clk.h"

3
components/esp_hw_support/port/esp32/CMakeLists.txt
View File

@ -8,7 +8,8 @@ set(srcs
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"rtc_wdt.c")
"rtc_wdt.c"
"chip_info.c")
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")

36
components/esp_hw_support/port/esp32/Kconfig.mac Normal file
View File

@ -0,0 +1,36 @@
choice ESP32_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
receive a universally administered MAC address. These are generated sequentially by adding 0
and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
addresses, respectively.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 2 or 4 per device.)
config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_BT
config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
bool "Four"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
select ESP_MAC_ADDR_UNIVERSE_BT
select ESP_MAC_ADDR_UNIVERSE_ETH
endchoice
config ESP32_UNIVERSAL_MAC_ADDRESSES
int
default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR

52
components/esp_hw_support/port/esp32/chip_info.c Normal file
View File

@ -0,0 +1,52 @@
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <string.h>
#include "esp_chip_info.h"
#include "soc/soc.h"
#include "soc/efuse_reg.h"
#include "esp_efuse.h"
void esp_chip_info(esp_chip_info_t* out_info)
{
uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG);
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32;
out_info->revision = esp_efuse_get_chip_ver();
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
out_info->cores = 2;
} else {
out_info->cores = 1;
}
out_info->features = CHIP_FEATURE_WIFI_BGN;
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
}
uint32_t package = esp_efuse_get_pkg_ver();
if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
out_info->features |= CHIP_FEATURE_EMB_FLASH;
}
}
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
inline bool soc_has_cache_lock_bug(void)
{
return (esp_efuse_get_chip_ver() == 3);
}
#endif

1
components/esp_hw_support/port/esp32c3/CMakeLists.txt
View File

@ -5,6 +5,7 @@ set(srcs "cpu_util_esp32c3.c"
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"chip_info.c"
)
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")

36
components/esp_hw_support/port/esp32c3/Kconfig.mac Normal file
View File

@ -0,0 +1,36 @@
choice ESP32C3_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
receive a universally administered MAC address. These are generated sequentially by adding 0
and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
addresses, respectively.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 2 or 4 per device.)
config ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_BT
config ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
bool "Four"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
select ESP_MAC_ADDR_UNIVERSE_BT
select ESP_MAC_ADDR_UNIVERSE_ETH
endchoice
config ESP32C3_UNIVERSAL_MAC_ADDRESSES
int
default 2 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR

26
components/esp_hw_support/port/esp32c3/chip_info.c Normal file
View File

@ -0,0 +1,26 @@
// Copyright 2013-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <string.h>
#include "esp_chip_info.h"
#include "esp_efuse.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32C3;
out_info->revision = esp_efuse_get_chip_ver();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}

4
components/esp_hw_support/port/esp32s2/CMakeLists.txt
View File

@ -9,7 +9,9 @@ set(srcs
"rtc_sleep.c"
"rtc_time.c"
"rtc_wdt.c"
"regi2c_ctrl.c")
"regi2c_ctrl.c"
"chip_info.c"
)
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")

30
components/esp_hw_support/port/esp32s2/Kconfig.mac Normal file
View File

@ -0,0 +1,30 @@
choice ESP32S2_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is Two, all interfaces (WiFi station, WiFi softap) receive a
universally administered MAC address. They are generated sequentially by adding 0, and 1 (respectively)
to the final octet of the base MAC address. If the number of universal MAC addresses is one,
only WiFi station receives a universally administered MAC address.
It's generated by adding 0 to the base MAC address.
The WiFi softap receives local MAC addresses. It's derived from the universal WiFi station MAC addresses.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 1 or 2 per device.)
config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
bool "One"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
endchoice
config ESP32S2_UNIVERSAL_MAC_ADDRESSES
int
default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO

40
components/esp_hw_support/port/esp32s2/chip_info.c Normal file
View File

@ -0,0 +1,40 @@
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <string.h>
#include "esp_chip_info.h"
#include "esp_efuse.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
uint32_t pkg_ver = esp_efuse_get_pkg_ver();
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S2;
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN;
switch (pkg_ver) {
case 0: // ESP32-S2
break;
case 1: // ESP32-S2FH16
// fallthrough
case 2: // ESP32-S2FH32
out_info->features |= CHIP_FEATURE_EMB_FLASH;
break;
default: // New package, features unknown
break;
}
}

4
components/esp_hw_support/port/esp32s3/CMakeLists.txt
View File

@ -8,7 +8,9 @@ set(srcs
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"rtc_wdt.c")
"rtc_wdt.c"
"chip_info.c"
)
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")

35
components/esp_hw_support/port/esp32s3/Kconfig.mac Normal file
View File

@ -0,0 +1,35 @@
choice ESP32S3_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
receive a universally administered MAC address. These are generated sequentially by adding 0
and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
addresses, respectively.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 2 or 4 per device.)
config ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_BT
config ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR
bool "Four"
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
select ESP_MAC_ADDR_UNIVERSE_BT
select ESP_MAC_ADDR_UNIVERSE_ETH
endchoice
config ESP32S3_UNIVERSAL_MAC_ADDRESSES
int
default 2 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR

24
components/esp_hw_support/port/esp32s3/chip_info.c Normal file
View File

@ -0,0 +1,24 @@
// Copyright 2013-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <string.h>
#include "esp_chip_info.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S3;
out_info->cores = 2;
out_info->features = CHIP_FEATURE_WIFI_BGN;
}

6
components/esp_hw_support/sdkconfig.rename Normal file
View File

@ -0,0 +1,6 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
CONFIG_TWO_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR

0
components/esp32/test/test_random.c → components/esp_hw_support/test/test_random.c
View File

6
components/esp_pm/linker.lf
View File

@ -12,6 +12,9 @@ archive: libesp_hw_support.a
entries:
if PM_SLP_IRAM_OPT = y:
rtc_init:rtc_vddsdio_get_config (noflash)
esp_clk:esp_clk_slowclk_cal_set (noflash)
esp_clk:esp_clk_slowclk_cal_get (noflash)
esp_clk:esp_rtc_get_time_us (noflash)
[mapping:esp_system_pm]
archive: libesp_system.a
@ -47,9 +50,6 @@ entries:
if PM_SLP_IRAM_OPT = y:
esp_time_impl:esp_time_impl_set_boot_time (noflash)
esp_time_impl:esp_time_impl_get_boot_time (noflash)
esp_time_impl:esp_clk_slowclk_cal_get (noflash)
esp_time_impl:esp_rtc_get_time_us (noflash)
esp_time_impl:esp_clk_slowclk_cal_set (noflash)
esp_time_impl:esp_set_time_from_rtc (noflash)
[mapping:driver_pm]

7
components/esp_system/CMakeLists.txt
View File

@ -10,13 +10,14 @@ if(BOOTLOADER_BUILD)
# Bootloader relies on some Kconfig options defined in esp_system.
idf_component_register(SRCS "${srcs}")
else()
list(APPEND srcs "esp_err.c"
list(APPEND srcs "crosscore_int.c"
"esp_err.c"
"freertos_hooks.c"
"intr_alloc.c"
"int_wdt.c"
"esp_async_memcpy.c"
"panic.c"
"system_api.c"
"esp_system.c"
"startup.c"
"system_time.c"
"stack_check.c"
@ -35,7 +36,7 @@ else()
# link-time registration is used.
esp_pm app_update nvs_flash pthread app_trace esp_gdbstub esp_ipc
espcoredump
LDFRAGMENTS "linker.lf")
LDFRAGMENTS "linker.lf" "app.lf")
add_subdirectory(port)
# After system initialization, `start_app` (and its other cores variant) is called.

53
components/esp32s2/ld/esp32s2_fragments.lf → components/esp_system/app.lf
View File

@ -1,49 +1,3 @@
[sections:text]
entries:
.text+
.literal+
[sections:data]
entries:
.data+
[sections:bss]
entries:
.bss+
[sections:common]
entries:
COMMON
[sections:rodata]
entries:
.rodata+
[sections:rtc_text]
entries:
.rtc.text+
.rtc.literal
[sections:rtc_data]
entries:
.rtc.data+
[sections:rtc_rodata]
entries:
.rtc.rodata+
[sections:rtc_bss]
entries:
.rtc.bss
[sections:iram]
entries:
.iram1+
[sections:dram]
entries:
.dram1+
[scheme:default]
entries:
if APP_BUILD_USE_FLASH_SECTIONS = y:
@ -55,7 +9,14 @@ entries:
data -> dram0_data
bss -> dram0_bss
common -> dram0_bss
if ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y:
extram_bss -> extern_ram
else:
extram_bss -> dram0_bss
legacy_bss -> dram0_bss
iram -> iram0_text
iram_data -> iram0_data
iram_bss -> iram0_bss
dram -> dram0_data
rtc_text -> rtc_text
rtc_data -> rtc_data

2
components/esp_system/component.mk
View File

@ -13,7 +13,7 @@ SOC_NAME := $(IDF_TARGET)
COMPONENT_SRCDIRS := .
COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_PRIV_INCLUDEDIRS := port/include port
COMPONENT_ADD_LDFRAGMENTS += linker.lf
COMPONENT_ADD_LDFRAGMENTS += linker.lf app.lf
ifndef CONFIG_IDF_ENV_FPGA
COMPONENT_OBJEXCLUDE += fpga_overrides.o

66
components/esp32/crosscore_int.c → components/esp_system/crosscore_int.c
View File

@ -12,30 +12,31 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <string.h>
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "esp_debug_helpers.h"
#include "soc/periph_defs.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"
#include "soc/gpio_periph.h"
#include "soc/rtc_periph.h"
#include "hal/cpu_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/portmacro.h"
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
#include "soc/dport_reg.h"
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
#include "soc/system_reg.h"
#endif
#define REASON_YIELD BIT(0)
#define REASON_FREQ_SWITCH BIT(1)
#if !CONFIG_IDF_TARGET_ESP32C3
#define REASON_PRINT_BACKTRACE BIT(2)
#endif
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t reason[ portNUM_PROCESSORS ];
static volatile uint32_t reason[portNUM_PROCESSORS];
/*
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
@ -52,11 +53,24 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
volatile uint32_t *my_reason=arg;
//Clear the interrupt first.
if (xPortGetCoreID()==0) {
#if CONFIG_IDF_TARGET_ESP32
if (cpu_hal_get_core_id()==0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
} else {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
}
#elif CONFIG_IDF_TARGET_ESP32S2
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
#elif CONFIG_IDF_TARGET_ESP32S3
if (cpu_hal_get_core_id()==0) {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
} else {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
}
#elif CONFIG_IDF_TARGET_ESP32C3
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
#endif
//Grab the reason and clear it.
portENTER_CRITICAL_ISR(&reason_spinlock);
my_reason_val=*my_reason;
@ -73,24 +87,30 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
* to allow DFS features without the extra latency of the ISR hook.
*/
}
#if !CONFIG_IDF_TARGET_ESP32C3 // IDF-2986
if (my_reason_val & REASON_PRINT_BACKTRACE) {
esp_backtrace_print(100);
}
#endif
}
//Initialize the crosscore interrupt on this core. Call this once
//on each active core.
void esp_crosscore_int_init(void) {
portENTER_CRITICAL(&reason_spinlock);
reason[xPortGetCoreID()]=0;
reason[cpu_hal_get_core_id()]=0;
portEXIT_CRITICAL(&reason_spinlock);
esp_err_t err __attribute__((unused));
if (xPortGetCoreID()==0) {
esp_err_t err __attribute__((unused)) = ESP_OK;
#if portNUM_PROCESSORS > 1
if (cpu_hal_get_core_id()==0) {
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
} else {
err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
}
assert(err == ESP_OK);
#else
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
#endif
ESP_ERROR_CHECK(err);
}
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
@ -100,11 +120,23 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
reason[core_id] |= reason_mask;
portEXIT_CRITICAL_ISR(&reason_spinlock);
//Poke the other CPU.
#if CONFIG_IDF_TARGET_ESP32
if (core_id==0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
} else {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
}
#elif CONFIG_IDF_TARGET_ESP32S2
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
#elif CONFIG_IDF_TARGET_ESP32S3
if (core_id==0) {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
} else {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
}
#elif CONFIG_IDF_TARGET_ESP32C3
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
#endif
}
void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
@ -117,7 +149,9 @@ void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
}
#if !CONFIG_IDF_TARGET_ESP32C3
void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
{
esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
}
#endif

54
components/esp_system/system_api.c → components/esp_system/esp_system.c
View File

@ -1,3 +1,17 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_system.h"
#include "esp_private/system_internal.h"
#include "esp_heap_caps.h"
@ -16,10 +30,29 @@
#include "esp32c3/memprot.h"
#endif
#define SHUTDOWN_HANDLERS_NO 4
static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
void IRAM_ATTR esp_restart_noos_dig(void)
{
// make sure all the panic handler output is sent from UART FIFO
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
// switch to XTAL (otherwise we will keep running from the PLL)
rtc_clk_cpu_freq_set_xtal();
#if CONFIG_IDF_TARGET_ESP32
esp_cpu_unstall(PRO_CPU_NUM);
#endif
// reset the digital part
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
while (true) {
;
}
}
esp_err_t esp_register_shutdown_handler(shutdown_handler_t handler)
{
for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
@ -44,25 +77,6 @@ esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
return ESP_ERR_INVALID_STATE;
}
void IRAM_ATTR esp_restart_noos_dig(void)
{
// make sure all the panic handler output is sent from UART FIFO
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
// switch to XTAL (otherwise we will keep running from the PLL)
rtc_clk_cpu_freq_set_xtal();
#if CONFIG_IDF_TARGET_ESP32
esp_cpu_unstall(PRO_CPU_NUM);
#endif
// reset the digital part
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
while (true) {
;
}
}
void IRAM_ATTR esp_restart(void)
{

5
components/esp_system/include/esp_private/crosscore_int.h
View File

@ -14,6 +14,8 @@
#ifndef __ESP_CROSSCORE_INT_H
#define __ESP_CROSSCORE_INT_H
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -54,6 +56,8 @@ void esp_crosscore_int_send_yield(int core_id);
*/
void esp_crosscore_int_send_freq_switch(int core_id);
#if !CONFIG_IDF_TARGET_ESP32C3
/**
* Send an interrupt to a CPU indicating it should print its current backtrace
*
@ -63,6 +67,7 @@ void esp_crosscore_int_send_freq_switch(int core_id);
* @param core_id Core that should print its backtrace
*/
void esp_crosscore_int_send_print_backtrace(int core_id);
#endif
#ifdef __cplusplus
}

186
components/esp_system/include/esp_system.h
View File

@ -24,31 +24,17 @@
#include "sdkconfig.h"
// For backward compatibility. These headers
// contains hardware operation functions and definitions
// that were originally declared in this header.
#include "esp_mac.h"
#include "esp_chip_info.h"
#include "esp_random.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ESP_MAC_WIFI_STA,
ESP_MAC_WIFI_SOFTAP,
ESP_MAC_BT,
ESP_MAC_ETH,
} esp_mac_type_t;
/** @cond */
#define TWO_UNIVERSAL_MAC_ADDR 2
#define FOUR_UNIVERSAL_MAC_ADDR 4
#if CONFIG_IDF_TARGET_ESP32
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32S2
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32S3
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32C3
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES
#endif
/** @endcond */
/**
* @brief Reset reasons
*/
@ -138,120 +124,6 @@ uint32_t esp_get_free_internal_heap_size(void);
*/
uint32_t esp_get_minimum_free_heap_size( void );
/**
* @brief Get one random 32-bit word from hardware RNG
*
* The hardware RNG is fully functional whenever an RF subsystem is running (ie Bluetooth or WiFi is enabled). For
* random values, call this function after WiFi or Bluetooth are started.
*
* If the RF subsystem is not used by the program, the function bootloader_random_enable() can be called to enable an
* entropy source. bootloader_random_disable() must be called before RF subsystem or I2S peripheral are used. See these functions'
* documentation for more details.
*
* Any time the app is running without an RF subsystem (or bootloader_random) enabled, RNG hardware should be
* considered a PRNG. A very small amount of entropy is available due to pre-seeding while the IDF
* bootloader is running, but this should not be relied upon for any use.
*
* @return Random value between 0 and UINT32_MAX
*/
uint32_t esp_random(void);
/**
* @brief Fill a buffer with random bytes from hardware RNG
*
* @note This function has the same restrictions regarding available entropy as esp_random()
*
* @param buf Pointer to buffer to fill with random numbers.
* @param len Length of buffer in bytes
*/
void esp_fill_random(void *buf, size_t len);
/**
* @brief Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or
* external storage e.g. flash and EEPROM.
*
* Base MAC address is used to generate the MAC addresses used by the networking interfaces.
* If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC
* address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing
* WiFi/BT/Ethernet.
*
* @note Base MAC must be a unicast MAC (least significant bit of first byte must be zero).
*
* @note If not using a valid OUI, set the "locally administered" bit
* (bit value 0x02 in the first byte) to avoid collisions.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_ARG If mac is NULL or is not a unicast MAC
*/
esp_err_t esp_base_mac_addr_set(const uint8_t *mac);
/**
* @brief Return base MAC address which is set using esp_base_mac_addr_set.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_MAC base MAC address has not been set
*/
esp_err_t esp_base_mac_addr_get(uint8_t *mac);
/**
* @brief Return base MAC address which was previously written to BLK3 of EFUSE.
*
* Base MAC address is used to generate the MAC addresses used by the networking interfaces.
* This API returns the custom base MAC address which was previously written to BLK3 of EFUSE.
* Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also
* possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE
* ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE
*/
esp_err_t esp_efuse_mac_get_custom(uint8_t *mac);
/**
* @brief Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
*/
esp_err_t esp_efuse_mac_get_default(uint8_t *mac);
/**
* @brief Read base MAC address and set MAC address of the interface.
*
* This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address
* from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,
* bluetooth and ethernet.
*
* @param mac MAC address of the interface, length: 6 bytes.
* @param type type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet.
*
* @return ESP_OK on success
*/
esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type);
/**
* @brief Derive local MAC address from universal MAC address.
*
* This function derives a local MAC address from an universal MAC address.
* A `definition of local vs universal MAC address can be found on Wikipedia
* <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`.
* In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage.
* Local MAC address is derived from the universal MAC address.
*
* @param local_mac Derived local MAC address, length: 6 bytes.
* @param universal_mac Source universal MAC address, length: 6 bytes.
*
* @return ESP_OK on success
*/
esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac);
/**
* @brief Trigger a software abort
*
@ -259,50 +131,6 @@ esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac)
*/
void __attribute__((noreturn)) esp_system_abort(const char* details);
/**
* @brief Chip models
*/
typedef enum {
CHIP_ESP32 = 1, //!< ESP32
CHIP_ESP32S2 = 2, //!< ESP32-S2
CHIP_ESP32S3 = 4, //!< ESP32-S3
CHIP_ESP32C3 = 5, //!< ESP32-C3
} esp_chip_model_t;
/* Chip feature flags, used in esp_chip_info_t */
#define CHIP_FEATURE_EMB_FLASH BIT(0) //!< Chip has embedded flash memory
#define CHIP_FEATURE_WIFI_BGN BIT(1) //!< Chip has 2.4GHz WiFi
#define CHIP_FEATURE_BLE BIT(4) //!< Chip has Bluetooth LE
#define CHIP_FEATURE_BT BIT(5) //!< Chip has Bluetooth Classic
/**
* @brief The structure represents information about the chip
*/
typedef struct {
esp_chip_model_t model; //!< chip model, one of esp_chip_model_t
uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags
uint8_t cores; //!< number of CPU cores
uint8_t revision; //!< chip revision number
} esp_chip_info_t;
/**
* @brief Fill an esp_chip_info_t structure with information about the chip
* @param[out] out_info structure to be filled
*/
void esp_chip_info(esp_chip_info_t* out_info);
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
/**
* @brief Cache lock bug exists or not
*
* @return
* - ture : bug exists
* - false : bug not exists
*/
bool soc_has_cache_lock_bug(void);
#endif
#ifdef __cplusplus
}
#endif

2
components/esp_system/linker.lf
View File

@ -6,7 +6,7 @@ entries:
panic_arch (noflash)
reset_reason (noflash)
esp_err (noflash)
system_api:esp_system_abort (noflash)
esp_system:esp_system_abort (noflash)
if ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF:
usb_console:esp_usb_console_write_char (noflash)

2
components/esp_system/port/CMakeLists.txt
View File

@ -1,4 +1,4 @@
target_include_directories(${COMPONENT_LIB} PRIVATE include .)
target_include_directories(${COMPONENT_LIB} PRIVATE include . PUBLIC soc)
set(srcs "cpu_start.c" "panic_handler.c" "brownout.c")
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs})

5
components/esp_system/port/arch/riscv/panic_arch.c
View File

@ -18,15 +18,12 @@
#include "esp_private/panic_internal.h"
#include "esp_private/panic_reason.h"
#include "riscv/rvruntime-frames.h"
#include "cache_err_int.h"
#if CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/cache_err_int.h"
#endif
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#include "esp32c3/memprot.h"
#endif
#define DIM(array) (sizeof(array)/sizeof(*array))
/**

8
components/esp_system/port/arch/xtensa/panic_arch.c
View File

@ -21,21 +21,19 @@
#include "esp_private/panic_reason.h"
#include "soc/soc.h"
#include "cache_err_int.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/cache_err_int.h"
#else
#if !CONFIG_IDF_TARGET_ESP32
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/rtc_cntl_reg.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/cache_err_int.h"
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#include "esp32s2/memprot.h"
#endif
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/cache_err_int.h"
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#include "esp32s3/memprot.h"
#endif

7
components/esp_system/port/cpu_start.c
View File

@ -23,6 +23,7 @@
#include "esp_system.h"
#include "esp_efuse.h"
#include "cache_err_int.h"
#include "esp_clk_internal.h"
#include "esp_rom_efuse.h"
@ -33,14 +34,11 @@
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#include "esp32/rtc.h"
#include "esp32/cache_err_int.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
#include "esp32/spiram.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rtc.h"
#include "esp32s2/brownout.h"
#include "esp32s2/cache_err_int.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/spiram.h"
@ -48,8 +46,6 @@
#include "esp32s2/memprot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rtc.h"
#include "esp32s3/brownout.h"
#include "esp32s3/cache_err_int.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/rtc.h"
#include "esp32s3/spiram.h"
@ -60,7 +56,6 @@
#include "soc/system_reg.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rtc.h"
#include "esp32c3/cache_err_int.h"
#include "esp32s3/rom/cache.h"
#include "esp32c3/rom/rtc.h"
#include "soc/cache_memory.h"

0
components/esp32s2/include/esp32s2/brownout.h → components/esp_system/port/include/brownout.h
View File

11
components/esp32s2/include/esp32s2/cache_err_int.h → components/esp_system/port/include/cache_err_int.h
View File

@ -12,6 +12,8 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
@ -20,14 +22,17 @@ extern "C" {
* @brief initialize cache invalid access interrupt
*
* This function enables cache invalid access interrupt source and connects it
* to interrupt input number ETS_MEMACCESS_ERR_INUM (see soc/soc.h). It is called
* from the startup code.
* to interrupt input number. It is called from the startup code.
*
* On ESP32, the interrupt input number is ETS_MEMACCESS_ERR_INUM. On other targets
* it is ETS_CACHEERR_INUM. See soc/soc.h for more information.
*/
void esp_cache_err_int_init(void);
/**
* @brief get the CPU which caused cache invalid access interrupt
* @brief get the CPU which caused cache invalid access interrupt. Helper function in
* panic handling.
* @return
* - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
* - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt

6
components/esp_system/port/panic_handler.c
View File

@ -25,21 +25,19 @@
#include "hal/soc_hal.h"
#include "hal/cpu_hal.h"
#include "cache_err_int.h"
#include "sdkconfig.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/dport_access.h"
#include "esp32/cache_err_int.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/memprot.h"
#include "esp32s2/cache_err_int.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/memprot.h"
#include "esp32s3/cache_err_int.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/memprot.h"
#include "esp32c3/cache_err_int.h"
#endif
#include "esp_private/panic_internal.h"

2
components/esp_system/port/soc/esp32/CMakeLists.txt
View File

@ -1,6 +1,8 @@
set(srcs "dport_panic_highint_hdl.S"
"clk.c"
"reset_reason.c"
"system_internal.c"
"cache_err_int.c"
"../../arch/xtensa/panic_arch.c"
"../../arch/xtensa/panic_handler_asm.S"
"../../arch/xtensa/expression_with_stack.c"

0
components/esp32/cache_err_int.c → components/esp_system/port/soc/esp32/cache_err_int.c
View File

2
components/esp_system/port/soc/esp32/cache_err_int.h Normal file
View File

@ -0,0 +1,2 @@
#pragma once
#include "cache_err_int.h"

42
components/esp32/system_api_esp32.c → components/esp_system/port/soc/esp32/system_internal.c
View File

@ -1,4 +1,4 @@
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -19,7 +19,6 @@
#include "esp_efuse.h"
#include "esp_log.h"
#include "sdkconfig.h"
#include "esp32/rom/cache.h"
#include "esp_rom_uart.h"
#include "soc/dport_reg.h"
#include "soc/gpio_periph.h"
@ -32,8 +31,10 @@
#include "hal/cpu_hal.h"
#include "freertos/xtensa_api.h"
#include "soc/soc_memory_layout.h"
#include "cache_err_int.h"
#include "esp32/cache_err_int.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
/* "inner" restart function for after RTOS, interrupts & anything else on this
* core are already stopped. Stalls other core, resets hardware,
@ -51,6 +52,8 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
@ -142,36 +145,3 @@ void IRAM_ATTR esp_restart_noos(void)
;
}
}
void esp_chip_info(esp_chip_info_t* out_info)
{
uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG);
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32;
out_info->revision = esp_efuse_get_chip_ver();
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
out_info->cores = 2;
} else {
out_info->cores = 1;
}
out_info->features = CHIP_FEATURE_WIFI_BGN;
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
}
uint32_t package = esp_efuse_get_pkg_ver();
if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
out_info->features |= CHIP_FEATURE_EMB_FLASH;
}
}
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
inline bool soc_has_cache_lock_bug(void)
{
return (esp_efuse_get_chip_ver() == 3);
}
#endif

2
components/esp_system/port/soc/esp32c3/CMakeLists.txt
View File

@ -1,5 +1,7 @@
set(srcs "clk.c"
"reset_reason.c"
"system_internal.c"
"cache_err_int.c"
"../../async_memcpy_impl_gdma.c"
"apb_backup_dma.c"
"../../arch/riscv/expression_with_stack.c"

0
components/esp32c3/cache_err_int.c → components/esp_system/port/soc/esp32c3/cache_err_int.c
View File

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