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esp_rom: extract int matrix route and cpu ticks getter

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This commit is contained in:
morris 2022-01-17 17:44:25 +08:00
parent 4cee573f44
commit ef00bd59dc
50 changed files with 170 additions and 223 deletions
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3
components/bootloader_support/src/bootloader_utility.c
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@ -31,7 +31,6 @@
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/efuse.h"
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/crc.h"
#include "esp32c3/rom/uart.h"
#include "esp32c3/rom/gpio.h"
@ -41,7 +40,6 @@
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/efuse.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/crc.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
@ -51,7 +49,6 @@
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
#include "esp32c2/rom/efuse.h"
#include "esp32c2/rom/ets_sys.h"
#include "esp32c2/rom/crc.h"
#include "esp32c2/rom/rtc.h"
#include "esp32c2/rom/uart.h"

1
components/bt/common/include/bt_common.h
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@ -8,6 +8,7 @@
#define _BT_COMMON_H_
#include <assert.h>
#include <stdbool.h>
#include "bt_user_config.h"
#include "esp_log.h"

3
components/bt/controller/esp32s3/bt.c
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@ -37,6 +37,7 @@
#include "esp_coexist_internal.h"
#include "esp_timer.h"
#include "esp_sleep.h"
#include "esp_rom_sys.h"
#if CONFIG_BT_ENABLED
@ -431,7 +432,7 @@ static inline void esp_bt_power_domain_off(void)
static void interrupt_set_wrapper(int32_t cpu_no, int32_t intr_source, int32_t intr_num, int32_t intr_prio)
{
intr_matrix_set(cpu_no, intr_source, intr_num);
esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
}
static void interrupt_clear_wrapper(int32_t intr_source, int32_t intr_num)

2
components/driver/test/test_gpio.c
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@ -171,7 +171,7 @@ static void prompt_to_continue(const char *str)
char sign[5] = {0};
while (strlen(sign) == 0) {
/* Flush anything already in the RX buffer */
while (esp_rom_uart_rx_one_char((uint8_t *) sign) == ETS_OK) {
while (esp_rom_uart_rx_one_char((uint8_t *) sign) == 0) {
}
/* Read line */
esp_rom_uart_rx_string((uint8_t *) sign, sizeof(sign) - 1);

1
components/esp_http_client/lib/http_header.c
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@ -10,6 +10,7 @@
#include <ctype.h>
#include <stdio.h>
#include <stdarg.h>
#include <stdbool.h>
#include "esp_log.h"
#include "esp_check.h"
#include "http_header.h"

4
components/esp_hw_support/esp_clk.c
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@ -12,6 +12,7 @@
#include "soc/rtc.h"
#include "soc/soc_caps.h"
#include "esp_rom_caps.h"
#include "esp_rom_sys.h"
#include "esp_private/esp_clk.h"
#if CONFIG_IDF_TARGET_ESP32
@ -23,7 +24,6 @@
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#include "esp32s3/rtc.h"
#include "esp32s3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#include "esp32c3/rtc.h"
@ -53,7 +53,7 @@ static RTC_DATA_ATTR uint64_t s_esp_rtc_time_us = 0, s_rtc_last_ticks = 0;
inline static int IRAM_ATTR s_get_cpu_freq_mhz(void)
{
#if ESP_ROM_GET_CLK_FREQ
return ets_get_cpu_frequency();
return esp_rom_get_cpu_ticks_per_us();
#else
return g_ticks_per_us_pro;
#endif

5
components/esp_hw_support/include/esp_mac.h
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@ -9,6 +9,11 @@
#include "esp_err.h"
#include "sdkconfig.h"
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
#ifdef __cplusplus
extern "C" {
#endif

14
components/esp_hw_support/include/soc_log.h
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@ -24,20 +24,6 @@
#define SOC_LOGV(tag, fmt, ...) ESP_EARLY_LOGV(tag, fmt, ##__VA_ARGS__)
#else
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/ets_sys.h"
#endif
#define SOC_LOGE(tag, fmt, ...) esp_rom_printf("%s(err): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGW(tag, fmt, ...) esp_rom_printf("%s(warn): " fmt, tag, ##__VA_ARGS__)

6
components/esp_hw_support/intr_alloc.c
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@ -560,7 +560,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
non_iram_int_mask[cpu]|=(1<<intr);
}
if (source>=0) {
intr_matrix_set(cpu, source, intr);
esp_rom_route_intr_matrix(cpu, source, intr);
}
//Fill return handle data.
@ -735,7 +735,7 @@ esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
}
if (source >= 0) {
//Disabled using int matrix; re-connect to enable
intr_matrix_set(handle->vector_desc->cpu, source, handle->vector_desc->intno);
esp_rom_route_intr_matrix(handle->vector_desc->cpu, source, handle->vector_desc->intno);
} else {
//Re-enable using cpu int ena reg
if (handle->vector_desc->cpu!=cpu_hal_get_core_id()) return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
@ -771,7 +771,7 @@ esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
if (source >= 0) {
if ( disabled ) {
//Disable using int matrix
intr_matrix_set(handle->vector_desc->cpu, source, INT_MUX_DISABLED_INTNO);
esp_rom_route_intr_matrix(handle->vector_desc->cpu, source, INT_MUX_DISABLED_INTNO);
}
} else {
//Disable using per-cpu regs

8
components/esp_hw_support/port/esp32c3/esp_memprot.c
View File

@ -10,7 +10,7 @@
#include "esp_intr_alloc.h"
#include "hal/memprot_ll.h"
#include "riscv/interrupt.h"
#include "esp32c3/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "esp_cpu.h"
#include "esp_fault.h"
#include "esp_attr.h"
@ -616,13 +616,13 @@ static esp_err_t esp_mprot_set_intr_matrix(const esp_mprot_mem_t mem_type)
switch (mem_type) {
case MEMPROT_TYPE_IRAM0_SRAM:
intr_matrix_set(PRO_CPU_NUM, memprot_ll_iram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_iram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
break;
case MEMPROT_TYPE_DRAM0_SRAM:
intr_matrix_set(PRO_CPU_NUM, memprot_ll_dram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_dram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
break;
case MEMPROT_TYPE_IRAM0_RTCFAST:
intr_matrix_set(PRO_CPU_NUM, memprot_ll_rtcfast_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_rtcfast_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
break;
default:
return ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID;

10
components/esp_hw_support/port/esp32s2/memprot.c
View File

@ -19,7 +19,7 @@
#include "esp32s2/memprot.h"
#include "esp_fault.h"
#include "esp_cpu.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp_rom_sys.h"
extern int _iram_text_end;
extern int _data_start;
@ -125,18 +125,18 @@ esp_err_t esp_memprot_intr_init(mem_type_prot_t mem_type)
switch (mem_type) {
case MEMPROT_IRAM0_SRAM:
case MEMPROT_IRAM0_RTCFAST:
intr_matrix_set(PRO_CPU_NUM, memprot_ll_iram0_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_iram0_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
break;
case MEMPROT_DRAM0_SRAM:
case MEMPROT_DRAM0_RTCFAST:
intr_matrix_set(PRO_CPU_NUM, memprot_ll_dram0_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_dram0_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
break;
case MEMPROT_PERI1_RTCSLOW:
intr_matrix_set(PRO_CPU_NUM, memprot_ll_peri1_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_peri1_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
break;
case MEMPROT_PERI2_RTCSLOW_0:
case MEMPROT_PERI2_RTCSLOW_1:
intr_matrix_set(PRO_CPU_NUM, memprot_ll_peri2_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
esp_rom_route_intr_matrix(PRO_CPU_NUM, memprot_ll_peri2_get_intr_source_num(), ETS_MEMACCESS_ERR_INUM);
break;
default:
return ESP_ERR_NOT_SUPPORTED;

2
components/esp_rom/esp32/ld/esp32.rom.api.ld
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@ -43,6 +43,8 @@ PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_set_bp = esp_rom_spiflash_lock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

2
components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
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@ -37,6 +37,8 @@ PROVIDE ( esp_rom_mbedtls_md5_finish_ret = 0x40002a3c );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );

2
components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
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@ -40,6 +40,8 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

2
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
View File

@ -43,6 +43,8 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

2
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld
View File

@ -43,6 +43,8 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

2
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
View File

@ -37,6 +37,8 @@ PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

2
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
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@ -43,6 +43,8 @@ PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );

40
components/esp_rom/include/esp_rom_sys.h
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@ -1,16 +1,8 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
@ -60,6 +52,28 @@ void esp_rom_install_uart_printf(void);
*/
soc_reset_reason_t esp_rom_get_reset_reason(int cpu_no);
/**
* @brief Route peripheral interrupt sources to CPU's interrupt port by matrix
*
* Usually there're 4 steps to use an interrupt:
* 1. Route peripheral interrupt source to CPU. e.g. esp_rom_route_intr_matrix(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM)
* 2. Set interrupt handler for CPU
* 3. Enable CPU interupt
* 4. Enable peripheral interrupt
*
* @param cpu_core The CPU number, which the peripheral interupt will inform to
* @param periph_intr_id The peripheral interrupt source number
* @param cpu_intr_num The CPU interrupt number
*/
void esp_rom_route_intr_matrix(int cpu_core, uint32_t periph_intr_id, uint32_t cpu_intr_num);
/**
* @brief Get the real CPU ticks per us
*
* @return CPU ticks per us
*/
uint32_t esp_rom_get_cpu_ticks_per_us(void);
#ifdef __cplusplus
}
#endif

2
components/esp_system/int_wdt.c
View File

@ -149,7 +149,7 @@ void esp_int_wdt_cpu_init(void)
ESP_INTR_DISABLE(WDT_INT_NUM);
#if SOC_TIMER_GROUPS > 1
intr_matrix_set(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
esp_rom_route_intr_matrix(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
#else
// TODO: Clean up code for ESP32-C2, IDF-4114
ESP_EARLY_LOGW("INT_WDT", "ESP32-C2 only has one timer group");

2
components/esp_system/port/arch/xtensa/esp_ipc_isr.c
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@ -65,7 +65,7 @@ void esp_ipc_isr_init(void)
const uint32_t cpuid = xPortGetCoreID();
uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE + cpuid; // ETS_FROM_CPU_INTR2_SOURCE and ETS_FROM_CPU_INTR3_SOURCE
ESP_INTR_DISABLE(ETS_IPC_ISR_INUM);
intr_matrix_set(cpuid, intr_source, ETS_IPC_ISR_INUM);
esp_rom_route_intr_matrix(cpuid, intr_source, ETS_IPC_ISR_INUM);
ESP_INTR_ENABLE(ETS_IPC_ISR_INUM);
if (cpuid != 0) {

2
components/esp_system/port/cpu_start.c
View File

@ -138,7 +138,7 @@ static void core_intr_matrix_clear(void)
uint32_t core_id = cpu_hal_get_core_id();
for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
intr_matrix_set(core_id, i, ETS_INVALID_INUM);
esp_rom_route_intr_matrix(core_id, i, ETS_INVALID_INUM);
}
}

22
components/esp_system/port/soc/esp32/cache_err_int.c
View File

@ -1,16 +1,8 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
The cache has an interrupt that can be raised as soon as an access to a cached
@ -32,7 +24,7 @@
#include "hal/cpu_hal.h"
#include "esp32/dport_access.h"
#include "esp32/rom/ets_sys.h" // for intr_matrix_set
#include "esp_rom_sys.h"
#include "sdkconfig.h"
@ -45,7 +37,7 @@ void esp_cache_err_int_init(void)
// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
// a call to the panic handler for
// this interrupt.
intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
// Enable invalid cache access interrupt when the cache is disabled.
// When the interrupt happens, we can not determine the CPU where the

6
components/esp_system/port/soc/esp32c2/cache_err_int.c
View File

@ -10,7 +10,7 @@
to panic the CPU, which from a debugging perspective is better than grabbing bad
data from the bus.
*/
#include "esp32c2/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
#include "soc/extmem_reg.h"
@ -46,8 +46,8 @@ void esp_cache_err_int_init(void)
* This error can occur if the dbus performs a request but the icache
* (or simply cache) is disabled.
*/
intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
/* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);

24
components/esp_system/port/soc/esp32c3/cache_err_int.c
View File

@ -1,16 +1,8 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
The cache has an interrupt that can be raised as soon as an access to a cached
@ -18,7 +10,7 @@
to panic the CPU, which from a debugging perspective is better than grabbing bad
data from the bus.
*/
#include "esp32c3/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
#include "soc/extmem_reg.h"
@ -54,8 +46,8 @@ void esp_cache_err_int_init(void)
* This error can occur if the dbus performs a request but the icache
* (or simply cache) is disabled.
*/
intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
/* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);

24
components/esp_system/port/soc/esp32h2/cache_err_int.c
View File

@ -1,16 +1,8 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
The cache has an interrupt that can be raised as soon as an access to a cached
@ -18,7 +10,7 @@
to panic the CPU, which from a debugging perspective is better than grabbing bad
data from the bus.
*/
#include "esp32h2/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
#include "soc/extmem_reg.h"
@ -54,8 +46,8 @@ void esp_cache_err_int_init(void)
* This error can occur if the dbus performs a request but the icache
* (or simply cache) is disabled.
*/
intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
/* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);

22
components/esp_system/port/soc/esp32s2/cache_err_int.c
View File

@ -1,16 +1,8 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
The cache has an interrupt that can be raised as soon as an access to a cached
@ -35,7 +27,7 @@
#include "hal/cpu_hal.h"
#include "esp32s2/dport_access.h"
#include "esp32s2/rom/ets_sys.h" // for intr_matrix_set
#include "esp_rom_sys.h"
#include "sdkconfig.h"
@ -48,7 +40,7 @@ void esp_cache_err_int_init(void)
// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
// a call to the panic handler for
// this interrupt.
intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
// Enable invalid cache access interrupt when the cache is disabled.
// The status bits are cleared first, in case we are restarting after

10
components/esp_system/port/soc/esp32s3/cache_err_int.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -22,7 +22,7 @@
#include "soc/periph_defs.h"
#include "hal/cpu_hal.h"
#include "esp32s3/dport_access.h"
#include "esp32s3/rom/ets_sys.h"
#include "esp_rom_sys.h"
void esp_cache_err_int_init(void)
{
@ -32,7 +32,7 @@ void esp_cache_err_int_init(void)
// We do not register a handler for the interrupt because it is interrupt
// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
// a call to the panic handler for this interrupt.
intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
// Enable invalid cache access interrupt when the cache is disabled.
// When the interrupt happens, we can not determine the CPU where the
@ -58,7 +58,7 @@ void esp_cache_err_int_init(void)
EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);
if (core_id == PRO_CPU_NUM) {
intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
/* On the hardware side, stat by clearing all the bits reponsible for
* enabling cache access error interrupts. */
SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG,
@ -76,7 +76,7 @@ void esp_cache_err_int_init(void)
EXTMEM_CORE0_IBUS_WR_IC_INT_ENA |
EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA);
} else {
intr_matrix_set(core_id, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
/* On the hardware side, stat by clearing all the bits reponsible for
* enabling cache access error interrupts. */

4
components/esp_system/test/test_backtrace.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -88,7 +88,7 @@ static void write_char_crash(char c)
TEST_CASE("Test backtrace with a ROM function", "[reset_reason][reset=StoreProhibited,SW_CPU_RESET]")
{
ets_install_putc1(&write_char_crash);
esp_rom_install_channel_putc(1, write_char_crash);
esp_rom_printf("foo");
}

27
components/esp_timer/src/ets_timer_legacy.c
View File

@ -1,16 +1,8 @@
// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* ets_timer module implements a set of legacy timer APIs which are
@ -29,12 +21,19 @@
#include "freertos/semphr.h"
#include "sdkconfig.h"
#include "esp_timer.h"
// for ETSTimer type
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h" // for ETSTimer type
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/ets_sys.h"
#endif
/* We abuse 'timer_arg' field of ETSTimer structure to hold a pointer to esp_timer */

4
components/esp_wifi/esp32/esp_adapter.c
View File

@ -42,6 +42,8 @@
#include "esp_coexist_adapter.h"
#include "esp32/dport_access.h"
#include "esp_timer.h"
#include "esp_rom_sys.h"
#include "esp32/rom/ets_sys.h"
#define TAG "esp_adapter"
@ -181,7 +183,7 @@ static bool IRAM_ATTR env_is_chip_wrapper(void)
static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio)
{
intr_matrix_set(cpu_no, intr_source, intr_num);
esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
}
static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num)

1
components/esp_wifi/esp32c3/esp_adapter.c
View File

@ -42,6 +42,7 @@
#include "esp_smartconfig.h"
#include "esp_coexist_internal.h"
#include "esp_coexist_adapter.h"
#include "esp32c3/rom/ets_sys.h"
#define TAG "esp_adapter"

4
components/esp_wifi/esp32s2/esp_adapter.c
View File

@ -42,6 +42,8 @@
#include "esp_smartconfig.h"
#include "esp_coexist_internal.h"
#include "esp_coexist_adapter.h"
#include "esp_rom_sys.h"
#include "esp32s2/rom/ets_sys.h"
#define TAG "esp_adapter"
@ -171,7 +173,7 @@ static bool IRAM_ATTR env_is_chip_wrapper(void)
static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio)
{
intr_matrix_set(cpu_no, intr_source, intr_num);
esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
}
static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num)

4
components/esp_wifi/esp32s3/esp_adapter.c
View File

@ -42,6 +42,8 @@
#include "esp_smartconfig.h"
#include "esp_coexist_internal.h"
#include "esp_coexist_adapter.h"
#include "esp_rom_sys.h"
#include "esp32s3/rom/ets_sys.h"
#define TAG "esp_adapter"
@ -171,7 +173,7 @@ static bool IRAM_ATTR env_is_chip_wrapper(void)
static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio)
{
intr_matrix_set(cpu_no, intr_source, intr_num);
esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
}
static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num)

8
components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/FreeRTOSConfig_arch.h
View File

@ -14,13 +14,7 @@
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#ifndef __ASSEMBLER__
#if CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/ets_sys.h"
#endif
#include "esp_rom_sys.h"
#endif // __ASSEMBLER__
/* The maximum interrupt priority from which FreeRTOS.org API functions can

7
components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/FreeRTOSConfig_arch.h
View File

@ -43,13 +43,6 @@ int xt_clock_freq(void) __attribute__((deprecated));
#ifndef __ASSEMBLER__
#include <assert.h>
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#endif
#endif // __ASSEMBLER__
#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION

3
components/hal/spi_hal.c
View File

@ -8,6 +8,7 @@
#include "hal/spi_hal.h"
#include "hal/log.h"
#include "hal/assert.h"
#include "soc/soc_caps.h"
//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
@ -78,7 +79,7 @@ esp_err_t spi_hal_cal_clock_conf(const spi_hal_timing_param_t *timing_param, int
spi_hal_timing_conf_t temp_conf;
int clk_src_freq_hz = timing_param->clk_src_hz;
assert((clk_src_freq_hz == 80 * 1000 * 1000) || (clk_src_freq_hz == 40 * 1000 * 1000));
HAL_ASSERT((clk_src_freq_hz == 80 * 1000 * 1000) || (clk_src_freq_hz == 40 * 1000 * 1000));
int eff_clk_n = spi_ll_master_cal_clock(clk_src_freq_hz, timing_param->expected_freq, timing_param->duty_cycle, &temp_conf.clock_reg);
//When the speed is too fast, we may need to use dummy cycles to compensate the reading.

7
components/heap/multi_heap_platform.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,11 +11,6 @@
#include "sdkconfig.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
#include <assert.h>
typedef portMUX_TYPE multi_heap_lock_t;

13
components/log/include/esp_log.h
View File

@ -11,19 +11,6 @@
#include <stdarg.h>
#include "sdkconfig.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/ets_sys.h"
#endif
#ifdef __cplusplus
extern "C" {

2
components/log/log_freertos.c
View File

@ -117,6 +117,6 @@ uint32_t esp_log_early_timestamp(void)
extern uint32_t g_ticks_per_us_pro;
return cpu_hal_get_cycle_count() / (g_ticks_per_us_pro * 1000);
#else
return cpu_hal_get_cycle_count() / (ets_get_cpu_frequency() * 1000);
return cpu_hal_get_cycle_count() / (esp_rom_get_cpu_ticks_per_us() * 1000);
#endif
}

6
components/log/log_noos.c
View File

@ -6,7 +6,8 @@
#include <assert.h>
#include "esp_log_private.h"
#include "hal/cpu_hal.h" // for cpu_hal_get_cycle_count()
#include "esp_rom_sys.h"
#include "hal/cpu_hal.h"
static int s_lock = 0;
@ -31,8 +32,7 @@ void esp_log_impl_unlock(void)
/* FIXME: define an API for getting the timestamp in soc/hal IDF-2351 */
uint32_t esp_log_early_timestamp(void)
{
extern uint32_t ets_get_cpu_frequency(void);
return cpu_hal_get_cycle_count() / (ets_get_cpu_frequency() * 1000);
return cpu_hal_get_cycle_count() / (esp_rom_get_cpu_ticks_per_us() * 1000);
}
uint32_t esp_log_timestamp(void) __attribute__((alias("esp_log_early_timestamp")));

19
components/pthread/include/esp_pthread.h
View File

@ -1,19 +1,12 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#include "freertos/FreeRTOSConfig.h"

1
components/spi_flash/sim/stubs/log/include/esp_log.h
View File

@ -9,6 +9,7 @@
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include "sdkconfig.h"

1
components/ulp/ulp_fsm/ulp_macro.c
View File

@ -7,6 +7,7 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_err.h"

2
components/wpa_supplicant/src/eap_peer/eap_mschapv2.c
View File

@ -10,8 +10,6 @@
#ifdef EAP_MSCHAPv2
#include "rsn_supp/wpa.h"
#include "utils/includes.h"
#include "utils/common.h"
#include "crypto/random.h"
#include "crypto/ms_funcs.h"
#include "tls/tls.h"

7
components/wpa_supplicant/src/rsn_supp/wpa.h
View File

@ -16,13 +16,8 @@
#define WPA_H
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
#include "utils/common.h"
#include "utils/includes.h"
#include "common/defs.h"
#include "common/wpa_common.h"
#include "esp_wifi_types.h"

11
components/wpa_supplicant/src/utils/includes.h
View File

@ -58,10 +58,19 @@
#endif /* CONFIG_NATIVE_WINDOWS */
#else
// for ETSTimer type
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/ets_sys.h"
#endif
#endif /* !__ets__ */

24
examples/peripherals/rmt/ir_protocols/components/infrared_tools/include/ir_tools.h
View File

@ -1,25 +1,19 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <stdint.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_err.h"
#define IR_TOOLS_FLAGS_PROTO_EXT (1 << 0) /*!< Enable Extended IR protocol */
#define IR_TOOLS_FLAGS_INVERSE (1 << 1) /*!< Inverse the IR signal, i.e. take high level as low, and vice versa */

8
tools/ci/check_copyright_ignore.txt
View File

@ -708,7 +708,6 @@ components/esp_rom/include/esp32s3/rom/usb/usb_persist.h
components/esp_rom/include/esp_rom_crc.h
components/esp_rom/include/esp_rom_efuse.h
components/esp_rom/include/esp_rom_gpio.h
components/esp_rom/include/esp_rom_sys.h
components/esp_rom/include/esp_rom_uart.h
components/esp_rom/include/linux/soc/reset_reasons.h
components/esp_rom/linux/esp_rom_crc.c
@ -750,19 +749,15 @@ components/esp_system/port/arch/xtensa/expression_with_stack.c
components/esp_system/port/public_compat/brownout.h
components/esp_system/port/public_compat/cache_err_int.h
components/esp_system/port/public_compat/trax.h
components/esp_system/port/soc/esp32/cache_err_int.c
components/esp_system/port/soc/esp32/cache_err_int.h
components/esp_system/port/soc/esp32/intr.c
components/esp_system/port/soc/esp32/reset_reason.c
components/esp_system/port/soc/esp32c3/apb_backup_dma.c
components/esp_system/port/soc/esp32c3/cache_err_int.c
components/esp_system/port/soc/esp32c3/cache_err_int.h
components/esp_system/port/soc/esp32c3/reset_reason.c
components/esp_system/port/soc/esp32h2/apb_backup_dma.c
components/esp_system/port/soc/esp32h2/cache_err_int.c
components/esp_system/port/soc/esp32h2/cache_err_int.h
components/esp_system/port/soc/esp32h2/reset_reason.c
components/esp_system/port/soc/esp32s2/cache_err_int.c
components/esp_system/port/soc/esp32s2/cache_err_int.h
components/esp_system/port/soc/esp32s2/reset_reason.c
components/esp_system/port/soc/esp32s2/usb_console.c
@ -780,7 +775,6 @@ components/esp_system/test_eh_frame_parser/linker.ld
components/esp_system/test_eh_frame_parser/main.c
components/esp_system/ubsan.c
components/esp_timer/include/esp_private/esp_timer_private.h
components/esp_timer/src/ets_timer_legacy.c
components/esp_timer/test/test_esp_timer.c
components/esp_timer/test/test_esp_timer_light_sleep.c
components/esp_timer/test/test_ets_timer.c
@ -1397,7 +1391,6 @@ components/protocomm/src/common/protocomm_priv.h
components/protocomm/src/security/security0.c
components/protocomm/src/transports/protocomm_console.c
components/protocomm/test/test_protocomm.c
components/pthread/include/esp_pthread.h
components/pthread/pthread_cond_var.c
components/pthread/pthread_internal.h
components/pthread/pthread_local_storage.c
@ -2441,7 +2434,6 @@ examples/peripherals/pcnt/rotary_encoder/components/rotary_encoder/include/rotar
examples/peripherals/pcnt/rotary_encoder/components/rotary_encoder/src/rotary_encoder_pcnt_ec11.c
examples/peripherals/pcnt/rotary_encoder/main/rotary_encoder_example_main.c
examples/peripherals/rmt/ir_protocols/components/infrared_tools/include/ir_timings.h
examples/peripherals/rmt/ir_protocols/components/infrared_tools/include/ir_tools.h
examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_nec.c
examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_rc5.c
examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_parser_rmt_nec.c

5
tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c
View File

@ -1,10 +1,11 @@
/* MEMPROT IramDram testing code */
#include <stdio.h>
#include <string.h>
#include "sdkconfig.h"
#include "esp_log.h"
#include "esp_spi_flash.h"
#include "esp32s2/memprot.h"
#include <string.h>
#include "esp_log.h"
#include "soc/soc.h"
/*
* ESP32S2 MEMORY PROTECTION MODULE TEST