Marius Vikhammer 9a6de4cb3e fix(panic): fixed cache error being reported as illegal instruction ... On riscv chips accessing cache mapped memory regions over the ibus would result in an illegal instructions exception triggering faster than the cache error interrupt/exception. Added a cache error check in the panic handler, if any cache errors are active the panic handler will now report a cache error, even if the trigger exception was a illegal instructions.		2023-12-04 10:49:00 +08:00
..
debug_helpers_asm.S	arch: move debug helpers	2021-02-26 13:34:29 +08:00
debug_helpers.c	Reverts Backtrace: format to what it used to be	2022-06-10 18:33:46 -10:00
debug_stubs.c	esp_system: fix and reenable no-format warning	2023-03-28 13:42:44 +02:00
esp_ipc_isr_handler.S	esp_system: Fix a race-condition in esp_ipc_isr (in QEMU env)	2023-05-24 19:08:29 +08:00
esp_ipc_isr_port.c	feat(esp_system): Support IPC_ISR for ESP32P4	2023-09-15 23:38:12 +08:00
esp_ipc_isr_routines.S	esp_system: Fix a race-condition in esp_ipc_isr (in QEMU env)	2023-05-24 19:08:29 +08:00
expression_with_stack_asm.S	arch: move shared stack implementation to esp_system	2021-02-26 13:34:29 +08:00
expression_with_stack.c	bugfix(esp_system): made watchpoint setting configuration-dependent	2023-03-13 14:24:15 +08:00
panic_arch.c	fix(panic): fixed cache error being reported as illegal instruction	2023-12-04 10:49:00 +08:00
panic_handler_asm.S	xtensa: Move saving of a0 register to match upstream	2022-02-03 17:08:14 +08:00
trax.c	move brownout trax cache_int_err to private folder	2021-11-26 18:27:53 +08:00