esp_intr_dump function can be used to print the list of allocated and
free interrupts. It can be used as a debugging aid when interrupt
allocation fails.
There's two GDMA groups on ESP32P4, one is connected to AHB bus,
and another one is connected AXI bus.
We now have two seperate APIs for allocating DMA channels,
depends on the bus type.
The changes only related to C6 and H2 chips where CONFIG_SOC_IEEE802154_SUPPORTED=y.
For this case these APIs return 8 bytes
esp_efuse_mac_get_default() -> 8 bytes
esp_efuse_mac_get_custom() -> 8 bytes
esp_read_mac(..., ESP_MAC_IEEE802154) -> 8 bytes
The rest cases len is 6 bytes
- Technical details covered in section "15.3.2 Anti-DPA Attack Security
Control" chapter of the ESP32-C6 TRM
- Default configuration sets the security level low for the DPA
protection
- This change applies to all the crypto peripherals where the clock
frequency is dynamically adjusted to create randomness in the power
consumption trajectory
- This configuration helps to make the SCA attacks difficult on the
crypto peripherals
Changed rv_utils_intr_edge_ack and esp_cpu_intr_edge_ack to
take uint32_t instead of int to avoid build errors.
The test is to test in particular that __builtin_ffsll, used in
xt_utils.h, which is included via esp_cpu.h, compiles fine
in C++20 with -Wsign-conversion enabled.
Closes https://github.com/espressif/esp-idf/pull/10895
- to acknowledge the unused DCACHE added to DRAM for ESP32-S3
- For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is added to
the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB (from 0x3C000000).
- But, if we try allocating memory from the 16 kB block and run an `esp_ptr_internal`
check on that memory pointer, it fails as the address block from 0x3C000000
corresponds to the external memory symbols SOC_DROM_LOW and SOC_EXTRAM_DATA_LOW.
(E.g. freertos - If the IDLE task stack buffer gets allocated from this region,
the firmware will abort due to this failure).
- Thus, the checks `esp_ptr_internal`, `esp_ptr_in_drom` and `esp_ptr_byte_accessible`
have been updated to acknowledge this memory as a part of the DRAM.
Co-authored-by: Mahavir Jain <mahavir@espressif.com>
bugfix: esp32c6 deep sleep minor fixes
Closes WIFI-5559, WIFI-5425, WIFI-3494, WIFI-3495, WIFI-4163, and WIFI-4164
See merge request espressif/esp-idf!22697
Memprot functions are no longer placed by default in IRAM,
selecting ESP_PANIC_HANDLER_IRAM will still force panic related memprot
functions to be placed in IRAM.
Update wifi lib with below -
1. Create NAN Discovery SM for beaconing & cluster formation
2. Create NAN interface for Tx/Rx of beacons & action frames
3. Add commands & events for NAN Services Publish/Subscribe/Followup
4. Add NAN Datapath definitions, Events, Peer structures
5. Support for forming and parsing of Datapath related attributes
6. Modules for NDP Req, Resp, Confirm, Term, Peer management
7. NAN Interface related additions in Datapath, Data Tx Q's
In addition include below changes -
1. Add netif and driver support for NAN Interface
2. Add simple examples for Publisher-Subscriber usecases
3. Add an advanced console example that supports commands
for NAN Discovery, Services & Datapath
4. Add wifi_apps for providing better NAN API's and Peer management
Co-authored-by: Shyamal Khachane <shyamal.khachane@espressif.com>
modem retention: Support esp32c6 wifi MAC and baseband sleep retention
sleep_modem: wifi MAC modem wakeup protect in modem state before PMU trigger sleep enable request
sleep modem: provide a interface to get whether the Modem power domain is allowed to power off during sleep
add i2c_ana master header file to project
auto beacon: release PMU's lock on root clock source (it is locked in the PLL)
wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL
clock, PMU will forcibly lock the root clock source as PLL, when the root
clock source of the software system is selected as PLL, we need to release
the root clock source locking.
When it is judged that the PLL is locked by PMU after wakeing up from the PMU
modem state, switch the root clock source to the PLL in the sleep process (a
critical section).
auto beacon: fix the failure to receive broadcast/multicast frames in modem state
When the multicast field in the beacon frame received in the PMU modem state is
True, the PMU switches to the PMU active state (the PMU waits for the HP LDO to
stabilize and then restores the MAC context) and starts to receive
broadcast/multicast frames (Broadcast/Multicast frames will be sent after a
minimum delay of 48 us after the beacon frame), because the PMU waits for the HP
LDO to stabilize too long (~154 us), which will cause broadcast/multicast frame
reception to be missed.
auto beacon: select the PLL clock source as the REGDMA backup clock source when the PMU switches to ACTIVE from MODEM state
update Digital Peripheral (M2A switch) REGDMA restore time parameter
auto beacon: fix the issue that only channel 1 can connect to AP in modem state
1. Remove RTC_CLOCK_BBPLL_POWER_ON_WITH_USB Kconfig option
During sleep, BBPLL clock always gets disabled
esp_restart does not disable BBPLL clock, so that first stage bootloader log can be printed
2. Add a new Kconfig option PM_NO_AUTO_LS_ON_USJ_CONNECTED
When this option is selected, IDF will constantly monitor USB CDC port connection status.
As long as it gets connected to a HOST, automatic light-sleep will not happen.
Closes https://github.com/espressif/esp-idf/issues/8507
cpu retention: add riscv core sleep critical and non-critical register layout structure definition
cpu retention: add assembly subroutine for cpu critical register backup and restore
cpu retention: add cpu core critical register context backup and restore support
cpu retention: add cpu core non-critical register context backup and restore support
cpu retention: add interrupt priority register context backup and restore support
cpu retention: add cache config register context backup and restore support
cpu retention: add plic interrupt register context backup and restore support
cpu retention: add clint interrupt register context backup and restore support
cpu retention: wait icache state idle before pmu enter sleep
Initialize the pmu sleep machine constant when pmu is initialized, and calculate
the pmu sleep time adjustment value and hardware configuration value according
to the machine constant during system sleep.
Calibrate fast OSC before each sleep and use the calibration value to calculate
PMU hardware wait cycles when use the fast OSC as the work clock.
1. add check in the gdma driver, to prevent multiple channels connecting
to the same peripheral
2. memory copy DMA ID will occupy the peripheral's DMA ID on some ESP
targets (e.g. esp32c3/s3). We should search for a free one when
install async memcpy driver.
Closes https://github.com/espressif/esp-idf/issues/10575
Since DRAM and IRAM are superposed on esp32c6 it is not necessary to convert a freshly allocated
DRAM addr to its IRAM equivalent when MALLOC_CAP_EXEC is passed to heap_caps_malloc(). Instead,
proceed with a default allocation since the address returned by multi_heap_malloc() already belongs
to the IRAM region.
Applies for esp32c6 and every boards with superposed DRAM and IRAM addresses.
esp_hw_support: Adds APIs to define user own MAC addresses without generation from the base MAC address
Closes IDFGH-5534 and IDFGH-8022
See merge request espressif/esp-idf!21036
1. Fix deep sleep wakeup IOs can not be unhold issue
2. Correct hold related APIs' description
3. Fix gpio_force_hold_all API
docs: Add GPIO wakeup source to sleep_modes doc for ESP32C3 and C2
API `esp_ds_encrypt_params` do not require aligned and DMA capable
output buffer for C3/S3/H2/C6. Implementation in ROM code has been
updated to remove usage of DMA mode.
This commit updates the API documentation.
esp_light_sleep_start() will stall the other CPU via esp_ipc_isr_stall_other_cpu(). After stalling the other CPU,
will call esp_clk_... API which themselves take locks. If the other stalled CPU is holding those locks, this will
result in a deadlock.
This commit adds a workaround calling esp_clk_private_lock() to take the lock before stalling the other CPU.
- Remove esp_cpu_in_ocd_mode() from esp_cpu.h. Users should call esp_cpu_dbgr_is_attached() instead.
- Remove esp_cpu_get_ccount() from esp_cpu.h. Users should call esp_cpu_get_cycle_count() instead.
- Remove esp_cpu_set_ccount() from esp_cpu.h. Users should call esp_cpu_set_cycle_count() instead.
- Other IDF components updated to call esp_cpu_dbgr_is_attached(), esp_cpu_get_cycle_count() and esp_cpu_set_cycle_count() as well.
This commit marks all functions in soc_hal.h and soc_ll.h as deprecated.
Users should use functions from esp_cpu.h instead.
Also added missing wrap funcions for esp_cpu_stall() in test_panic.c files.
This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
This function removes the following legacy atomic CAS functions:
From compare_set.h (file removed):
- compare_and_set_native()
- compare_and_set_extram()
From portmacro.h
- uxPortCompareSet()
- uxPortCompareSetExtram()
Users should call esp_cpu_compare_and_set() instead as this function hides the details
of atomic CAS on internal and external RAM addresses.
Due to the removal of compare_set.h, some missing header includes are also fixed in this commit.
esp_cpu_compare_and_set() abstracts the atomic compare-and-set instruction by
hiding the details of whether the target variable is in internal or external
RAM. This commit updates "spinlocks.h" as follows:
- esp_cpu_compare_and_set() is now called instead of "compare_set.h"
- Refactored spinlock logic to be more optimized and have more stringent sanity checks
This commit fixes esp_cpu_compare_and_set() in the following ways
- Removed call to esp_ptr_external_ram() as it incurred > 80 CPU cycles (due to multiple nested
function calls, and those functions not being in IRAM). We now check manually if the pointer
is in external RAM for increased speed.
- Fixed infinite wait when attempting to get the external_ram_cas_lock. The function should
return immediatley if any part of the compare and set call fails.
- The preprocessor conditions of esp_cpu_compare_and_set() to depend on CONFIG_SPIRAM instead
of SOC_SPIRAM_SUPPORTED. Even if the target supports SPIRAM, we only need the external RAM
compare and set feature if SPIRAM is enabled.
Also fixed incorrect inclusion of esp_intr_alloc.h in esp_cpu.h
