mirror of
https://github.com/espressif/esp-idf.git
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ESP32H2: Introduce new chip target esp32h2, hello_world example supported
This commit is contained in:
Cao Sen Miao
parent
4e67332b74
commit
4713a9a7f2
9
Kconfig
9
Kconfig
@ -13,6 +13,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
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config IDF_ENV_FPGA
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# This option is for internal use only
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bool
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default "y" if IDF_TARGET_ESP32H2 # TODO: IDF-5630
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option env="IDF_ENV_FPGA"
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config IDF_CI_BUILD
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@ -100,6 +101,13 @@ mainmenu "Espressif IoT Development Framework Configuration"
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select FREERTOS_UNICORE
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select IDF_TARGET_ARCH_RISCV
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config IDF_TARGET_ESP32H2
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bool
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default "y" if IDF_TARGET="esp32h2"
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select FREERTOS_UNICORE
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select IDF_TARGET_ARCH_RISCV
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select ESPTOOLPY_NO_STUB # // ESP32H2-TODO
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config IDF_TARGET_LINUX
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bool
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default "y" if IDF_TARGET="linux"
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@ -114,6 +122,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
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default 0x000C if IDF_TARGET_ESP32C2
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default 0x000D if IDF_TARGET_ESP32C6
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default 0x000E if IDF_TARGET_ESP32H4_BETA_VERSION_2 # ESP32-TODO: IDF-3475
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default 0x0010 if IDF_TARGET_ESP32H2
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default 0xFFFF
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238
components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
Normal file
238
components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
Normal file
@ -0,0 +1,238 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
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*
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* ESP32-H2 ROM static data usage is as follows:
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* - 0x4083ba78 - 0x4084d380: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x4084d380 - 0x4084f380: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x4084f380 - 0x4084fee0: ROM .bss and .data used in startup code or nonos/early boot (can be freed when IDF runs)
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* - 0x4084fee0 - 0x40850000: ROM .bss and .data used in startup code and when IDF runs (cannot be freed)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x4084d380).
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*/
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/* We consider 0x3fcdc710 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
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* and work out iram_seg and iram_loader_seg addresses from there, backwards.
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*/
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/* These lengths can be adjusted, if necessary: */
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bootloader_usable_dram_end = 0x4084cfd0;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x5000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x2000;
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/* Start of the lower region is determined by region size and the end of the higher region */
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bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
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bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
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bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
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bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
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MEMORY
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{
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iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
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iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
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dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
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}
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/* Default entry point: */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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.iram_loader.text :
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{
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. = ALIGN (16);
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_loader_text_start = ABSOLUTE(.);
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*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
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*liblog.a:(.literal .text .literal.* .text.*)
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*libgcc.a:(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
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*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
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*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
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*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
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*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
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*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
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*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
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*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
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*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
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*libefuse.a:*.*(.literal .text .literal.* .text.*)
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_loader_text_end = ABSOLUTE(.);
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} > iram_loader_seg
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.iram.text :
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{
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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} > iram_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_dram_start = ABSOLUTE(.);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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} > dram_seg
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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_data_end = ABSOLUTE(.);
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} > dram_seg
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.dram0.rodata :
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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*(.sdata2 .sdata2.* .srodata .srodata.*)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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*(.eh_frame)
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. = (. + 3) & ~ 3;
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/* C++ constructor and destructor tables, properly ordered: */
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__init_array_start = ABSOLUTE(.);
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KEEP (*crtbegin.*(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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__init_array_end = ABSOLUTE(.);
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KEEP (*crtbegin.*(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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_rodata_end = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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. = ALIGN(4);
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_dram_end = ABSOLUTE(.);
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} > dram_seg
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.iram.text :
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.iram .iram.*) /* catch stray IRAM_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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/** CPU will try to prefetch up to 16 bytes of
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* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += 16;
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_text_end = ABSOLUTE(.);
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_etext = .;
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} > iram_seg
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}
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/**
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* 0x4083b6cc ------------------> _dram0_0_start
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* | |
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* | |
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* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
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* | |
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* | |
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* 0x4084cfd0 ------------------> __stack_sentry
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* | |
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* | | 2. Startup pro cpu stack (freed when IDF app is running)
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* | |
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* 0x4084efd0 ------------------> __stack (pro cpu)
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* | |
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* | |
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* | | 3. Shared memory only used in startup code or nonos/early boot*
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* | | (can be freed when IDF runs)
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* | |
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* | |
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* 0x4084fb30 ------------------> _dram0_rtos_reserved_start
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* | |
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* | |
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* | | 4. Shared memory used in startup code and when IDF runs
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* | |
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* | |
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* 0x4084fc04 ------------------> _dram0_rtos_reserved_end
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* | |
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* 0x4084ffcc ------------------> _data_start_interface
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* | |
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* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
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* | |
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* 0x40850000 ------------------> _data_end_interface
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*/
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@ -0,0 +1,6 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* No definition for ESP32-H2 target */
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@ -3,3 +3,55 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <assert.h>
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#include "string.h"
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp32h2/rom/gpio.h"
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#include "esp32h2/rom/spi_flash.h"
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#include "esp32h2/rom/efuse.h"
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#include "soc/gpio_periph.h"
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#include "soc/efuse_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/soc_caps.h"
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#include "flash_qio_mode.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_common.h"
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void bootloader_flash_update_id()
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{
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esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
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chip->device_id = bootloader_read_flash_id();
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}
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void IRAM_ATTR bootloader_flash_cs_timing_config()
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{
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
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}
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void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
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{
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uint32_t spi_clk_div = 0;
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_DIV_1:
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spi_clk_div = 1;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_2:
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spi_clk_div = 2;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_3:
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spi_clk_div = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_4:
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spi_clk_div = 4;
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break;
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default:
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break;
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}
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esp_rom_spiflash_config_clk(spi_clk_div, 0);
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}
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@ -23,6 +23,8 @@
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#include "esp32c2/rom/secure_boot.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/secure_boot.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/secure_boot.h"
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#endif
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#if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300
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@ -9,7 +9,7 @@
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#include "soc/chip_revision.h"
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#include "hal/efuse_hal.h"
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#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
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#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
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#include "soc/rtc_cntl_reg.h"
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#else
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#include "soc/lp_wdt_reg.h"
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@ -102,6 +102,17 @@ __attribute__((weak)) void bootloader_clock_configure(void)
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SET_PERI_REG_MASK(LP_TIMER_LP_INT_CLR_REG, LP_TIMER_MAIN_TIMER_LP_INT_CLR); /* MAIN_TIMER */
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SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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#elif CONFIG_IDF_TARGET_ESP32H2
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// CLR ENA
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
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CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_ENA, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
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SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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// SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); // TODO: IDF-5348 /* SLP_REJECT */
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// SET_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_CLR, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */
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#else
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@ -33,6 +33,10 @@ int bootloader_clock_get_rated_freq_mhz(void)
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#elif CONFIG_IDF_TARGET_ESP32C6
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return 160;
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||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
//IDF-6570
|
||||
return 96;
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
return 240;
|
||||
|
||||
|
||||
@ -61,7 +61,7 @@ void bootloader_config_wdt(void)
|
||||
* protect the remainder of the bootloader process.
|
||||
*/
|
||||
//Disable RWDT flashboot protection.
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5653
|
||||
wdt_hal_context_t rwdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
|
||||
#else
|
||||
wdt_hal_context_t rwdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
|
||||
@ -3,3 +3,19 @@
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "sdkconfig.h"
|
||||
#include "bootloader_random.h"
|
||||
#include "esp_log.h"
|
||||
|
||||
static const char *TAG = "bootloader_random";
|
||||
void bootloader_random_enable(void)
|
||||
{
|
||||
// ESP32H2-TODO: IDF-6274
|
||||
ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
|
||||
}
|
||||
|
||||
void bootloader_random_disable(void)
|
||||
{
|
||||
// ESP32H2-TODO: IDF-6274
|
||||
ESP_EARLY_LOGW(TAG, "bootloader_random_disable() has not been implemented yet");
|
||||
}
|
||||
|
||||
@ -48,6 +48,13 @@
|
||||
#include "esp32c6/rom/uart.h"
|
||||
#include "esp32c6/rom/gpio.h"
|
||||
#include "esp32c6/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/efuse.h"
|
||||
#include "esp32h2/rom/crc.h"
|
||||
#include "esp32h2/rom/rtc.h"
|
||||
#include "esp32h2/rom/uart.h"
|
||||
#include "esp32h2/rom/gpio.h"
|
||||
#include "esp32h2/rom/secure_boot.h"
|
||||
|
||||
#else // CONFIG_IDF_TARGET_*
|
||||
#error "Unsupported IDF_TARGET"
|
||||
|
||||
321
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
Normal file
321
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
Normal file
@ -0,0 +1,321 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_image_format.h"
|
||||
#include "flash_qio_mode.h"
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "esp_rom_uart.h"
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp_rom_spiflash.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/assist_debug_reg.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
#include "esp32h2/rom/efuse.h"
|
||||
#include "esp32h2/rom/ets_sys.h"
|
||||
#include "bootloader_common.h"
|
||||
#include "bootloader_init.h"
|
||||
#include "bootloader_clock.h"
|
||||
#include "bootloader_flash_config.h"
|
||||
#include "bootloader_mem.h"
|
||||
#include "esp_private/regi2c_ctrl.h"
|
||||
#include "soc/regi2c_lp_bias.h"
|
||||
#include "soc/regi2c_bias.h"
|
||||
#include "bootloader_console.h"
|
||||
#include "bootloader_flash_priv.h"
|
||||
#include "bootloader_soc.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "hal/mmu_hal.h"
|
||||
#include "hal/cache_hal.h"
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
|
||||
static const char *TAG = "boot.esp32h2";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
|
||||
}
|
||||
|
||||
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
|
||||
{
|
||||
uint32_t size;
|
||||
switch (bootloader_hdr->spi_size) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
size = 1;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
size = 2;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
size = 4;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
size = 8;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
size = 16;
|
||||
break;
|
||||
default:
|
||||
size = 2;
|
||||
}
|
||||
cache_hal_disable(CACHE_TYPE_ALL);
|
||||
// Set flash chip size
|
||||
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
|
||||
cache_hal_enable(CACHE_TYPE_ALL);
|
||||
}
|
||||
|
||||
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
|
||||
{
|
||||
ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
|
||||
ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
|
||||
ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
|
||||
ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
|
||||
ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
|
||||
|
||||
const char *str;
|
||||
switch (bootloader_hdr->spi_speed) {
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_2:
|
||||
str = "40MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_3:
|
||||
str = "26.7MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_4:
|
||||
str = "20MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_1:
|
||||
str = "80MHz";
|
||||
break;
|
||||
default:
|
||||
str = "20MHz";
|
||||
break;
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Speed : %s", str);
|
||||
|
||||
/* SPI mode could have been set to QIO during boot already,
|
||||
so test the SPI registers not the flash header */
|
||||
uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
|
||||
if (spi_ctrl & SPI_MEM_FREAD_QIO) {
|
||||
str = "QIO";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
|
||||
str = "QOUT";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
|
||||
str = "DIO";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
|
||||
str = "DOUT";
|
||||
} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
|
||||
str = "FAST READ";
|
||||
} else {
|
||||
str = "SLOW READ";
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Mode : %s", str);
|
||||
|
||||
switch (bootloader_hdr->spi_size) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
str = "1MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
str = "2MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
str = "4MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
str = "8MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
str = "16MB";
|
||||
break;
|
||||
default:
|
||||
str = "2MB";
|
||||
break;
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Flash Size : %s", str);
|
||||
}
|
||||
|
||||
static void IRAM_ATTR bootloader_init_flash_configure(void)
|
||||
{
|
||||
bootloader_configure_spi_pins(1);
|
||||
bootloader_flash_cs_timing_config();
|
||||
}
|
||||
|
||||
static void bootloader_spi_flash_resume(void)
|
||||
{
|
||||
bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
|
||||
esp_rom_spiflash_wait_idle(&g_rom_flashchip);
|
||||
}
|
||||
|
||||
static esp_err_t bootloader_init_spi_flash(void)
|
||||
{
|
||||
bootloader_init_flash_configure();
|
||||
bootloader_spi_flash_resume();
|
||||
bootloader_flash_unlock();
|
||||
|
||||
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
|
||||
bootloader_enable_qio_mode();
|
||||
#endif
|
||||
|
||||
print_flash_info(&bootloader_image_hdr);
|
||||
update_flash_config(&bootloader_image_hdr);
|
||||
//ensure the flash is write-protected
|
||||
bootloader_enable_wp();
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static void wdt_reset_cpu0_info_enable(void)
|
||||
{
|
||||
REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
|
||||
REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
|
||||
REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
|
||||
}
|
||||
|
||||
static void wdt_reset_info_dump(int cpu)
|
||||
{
|
||||
(void) cpu;
|
||||
// saved PC was already printed by the ROM bootloader.
|
||||
// nothing to do here.
|
||||
}
|
||||
|
||||
static void bootloader_check_wdt_reset(void)
|
||||
{
|
||||
int wdt_rst = 0;
|
||||
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
|
||||
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
|
||||
rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
|
||||
ESP_EARLY_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
if (wdt_rst) {
|
||||
// if reset by WDT dump info from trace port
|
||||
wdt_reset_info_dump(0);
|
||||
}
|
||||
wdt_reset_cpu0_info_enable();
|
||||
}
|
||||
|
||||
static void bootloader_super_wdt_auto_feed(void)
|
||||
{
|
||||
REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
|
||||
REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
|
||||
REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
|
||||
}
|
||||
|
||||
static inline void bootloader_hardware_init(void)
|
||||
{
|
||||
// ESP32H2-TODO: IDF-5990
|
||||
}
|
||||
|
||||
static inline void bootloader_ana_reset_config(void)
|
||||
{
|
||||
// TODO: IDF-5990 copied from C6, need update
|
||||
// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
|
||||
/*
|
||||
For origin chip & ECO1: only support swt reset;
|
||||
For ECO2: fix brownout reset bug, support swt & brownout reset;
|
||||
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
|
||||
*/
|
||||
uint8_t chip_version = efuse_hal_get_minor_chip_version();
|
||||
switch (chip_version) {
|
||||
case 0:
|
||||
case 1:
|
||||
//Disable BOR and GLITCH reset
|
||||
bootloader_ana_bod_reset_config(false);
|
||||
bootloader_ana_clock_glitch_reset_config(false);
|
||||
break;
|
||||
case 2:
|
||||
//Enable BOR reset. Disable GLITCH reset
|
||||
bootloader_ana_bod_reset_config(true);
|
||||
bootloader_ana_clock_glitch_reset_config(false);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
//Enable BOR, and GLITCH reset
|
||||
bootloader_ana_bod_reset_config(true);
|
||||
bootloader_ana_clock_glitch_reset_config(true);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t bootloader_init(void)
|
||||
{
|
||||
esp_err_t ret = ESP_OK;
|
||||
|
||||
bootloader_hardware_init();
|
||||
bootloader_ana_reset_config();
|
||||
bootloader_super_wdt_auto_feed();
|
||||
// protect memory region
|
||||
bootloader_init_mem();
|
||||
/* check that static RAM is after the stack */
|
||||
assert(&_bss_start <= &_bss_end);
|
||||
assert(&_data_start <= &_data_end);
|
||||
// clear bss section
|
||||
bootloader_clear_bss_section();
|
||||
// init eFuse virtual mode (read eFuses to RAM)
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
|
||||
#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
|
||||
esp_efuse_init_virtual_mode_in_ram();
|
||||
#endif
|
||||
#endif
|
||||
//init cache hal
|
||||
cache_hal_init();
|
||||
//reset mmu
|
||||
mmu_hal_init();
|
||||
// config clock
|
||||
bootloader_clock_configure();
|
||||
// initialize console, from now on, we can use esp_log
|
||||
bootloader_console_init();
|
||||
/* print 2nd bootloader banner */
|
||||
bootloader_print_banner();
|
||||
// update flash ID
|
||||
bootloader_flash_update_id();
|
||||
// Check and run XMC startup flow
|
||||
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
|
||||
ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
|
||||
goto err;
|
||||
}
|
||||
// read bootloader header
|
||||
if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
|
||||
goto err;
|
||||
}
|
||||
// read chip revision and check if it's compatible to bootloader
|
||||
if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
|
||||
goto err;
|
||||
}
|
||||
// initialize spi flash
|
||||
if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
|
||||
goto err;
|
||||
}
|
||||
// check whether a WDT reset happend
|
||||
bootloader_check_wdt_reset();
|
||||
// config WDT
|
||||
bootloader_config_wdt();
|
||||
// enable RNG early entropy source
|
||||
bootloader_enable_random();
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
40
components/bootloader_support/src/esp32h2/bootloader_sha.c
Normal file
40
components/bootloader_support/src/esp32h2/bootloader_sha.c
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "bootloader_sha.h"
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <sys/param.h>
|
||||
|
||||
#include "esp32h2/rom/sha.h"
|
||||
|
||||
static SHA_CTX ctx;
|
||||
|
||||
bootloader_sha256_handle_t bootloader_sha256_start()
|
||||
{
|
||||
// Enable SHA hardware
|
||||
ets_sha_enable();
|
||||
ets_sha_init(&ctx, SHA2_256);
|
||||
return &ctx; // Meaningless non-NULL value
|
||||
}
|
||||
|
||||
void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
assert(data_len % 4 == 0);
|
||||
ets_sha_update(&ctx, data, data_len, false);
|
||||
}
|
||||
|
||||
void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
|
||||
if (digest == NULL) {
|
||||
bzero(&ctx, sizeof(ctx));
|
||||
return;
|
||||
}
|
||||
ets_sha_finish(&ctx, digest);
|
||||
}
|
||||
33
components/bootloader_support/src/esp32h2/bootloader_soc.c
Normal file
33
components/bootloader_support/src/esp32h2/bootloader_soc.c
Normal file
@ -0,0 +1,33 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_analog_peri_reg.h"
|
||||
|
||||
void bootloader_ana_super_wdt_reset_config(bool enable)
|
||||
{
|
||||
// ESP32H2 has removed the super wdt
|
||||
}
|
||||
|
||||
void bootloader_ana_bod_reset_config(bool enable)
|
||||
{
|
||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
|
||||
if (enable) {
|
||||
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
|
||||
} else {
|
||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
|
||||
}
|
||||
}
|
||||
|
||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||
{
|
||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
|
||||
if (enable) {
|
||||
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
|
||||
} else {
|
||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <strings.h>
|
||||
#include "esp_flash_encrypt.h"
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_log.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "flash_encrypt";
|
||||
|
||||
esp_err_t esp_flash_encryption_enable_secure_features(void)
|
||||
{
|
||||
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
|
||||
ESP_LOGI(TAG, "Disable UART bootloader encryption...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
|
||||
ESP_LOGI(TAG, "Disable UART bootloader cache...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
|
||||
ESP_LOGI(TAG, "Disable JTAG...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
|
||||
|
||||
#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)
|
||||
// This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot
|
||||
// otherwise the Flash Encryption key cannot be read protected
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
|
||||
#endif
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <strings.h>
|
||||
#include "esp_flash_encrypt.h"
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_log.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "secure_boot";
|
||||
|
||||
esp_err_t esp_secure_boot_enable_secure_features(void)
|
||||
{
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
|
||||
|
||||
#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
|
||||
ESP_LOGI(TAG, "Enabling Security download mode...");
|
||||
esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Could not enable Security download mode...");
|
||||
return err;
|
||||
}
|
||||
#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
|
||||
ESP_LOGI(TAG, "Disable ROM Download mode...");
|
||||
esp_err_t err = esp_efuse_disable_rom_download_mode();
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Could not disable ROM Download mode...");
|
||||
return err;
|
||||
}
|
||||
#else
|
||||
ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
|
||||
ESP_LOGI(TAG, "Disable hardware & software JTAG...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
|
||||
esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
|
||||
#endif
|
||||
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
||||
bool rd_dis_now = true;
|
||||
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
|
||||
/* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
|
||||
when Flash Encryption is being enabled */
|
||||
rd_dis_now = esp_flash_encryption_enabled();
|
||||
#endif
|
||||
if (rd_dis_now) {
|
||||
ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
|
||||
}
|
||||
#else
|
||||
ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -37,6 +37,9 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/rtc.h"
|
||||
#include "esp32c6/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/rtc.h"
|
||||
#include "esp32h2/rom/secure_boot.h"
|
||||
#endif
|
||||
|
||||
#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
|
||||
|
||||
@ -0,0 +1 @@
|
||||
# ESP32H2: Support BT
|
||||
@ -5,12 +5,6 @@ set(srcs
|
||||
"gpio/rtc_io.c"
|
||||
"gpio/gpio_glitch_filter_ops.c"
|
||||
"gptimer/gptimer.c"
|
||||
"sdspi_crc.c"
|
||||
"sdspi_host.c"
|
||||
"sdspi_transaction.c"
|
||||
"spi_common.c"
|
||||
"spi_master.c"
|
||||
"spi_slave.c"
|
||||
"spi_bus_lock.c"
|
||||
"uart.c")
|
||||
|
||||
@ -111,6 +105,16 @@ if(CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED)
|
||||
list(APPEND srcs "usb_serial_jtag.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_GPSPI_SUPPORTED)
|
||||
list(APPEND srcs
|
||||
"spi_common.c"
|
||||
"spi_master.c"
|
||||
"spi_slave.c"
|
||||
"sdspi_crc.c"
|
||||
"sdspi_host.c"
|
||||
"sdspi_transaction.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2)
|
||||
list(APPEND srcs "spi_slave_hd.c")
|
||||
endif()
|
||||
@ -138,6 +142,14 @@ if(${target} STREQUAL "esp32")
|
||||
list(APPEND srcs "deprecated/adc_i2s_deprecated.c")
|
||||
endif()
|
||||
|
||||
if(${target} STREQUAL "esp32h2")
|
||||
# TODO: IDF-5310
|
||||
list(REMOVE_ITEM srcs
|
||||
"deprecated/timer_legacy.c"
|
||||
"gptimer/gptimer.c"
|
||||
)
|
||||
endif()
|
||||
|
||||
if(BOOTLOADER_BUILD)
|
||||
# Bootloader shall NOT depend on the drivers
|
||||
idf_component_register()
|
||||
|
||||
@ -70,7 +70,7 @@ typedef enum {
|
||||
ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO4 */
|
||||
ADC1_CHANNEL_MAX,
|
||||
} adc1_channel_t;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
typedef enum {
|
||||
ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
|
||||
ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */
|
||||
|
||||
55
components/efuse/esp32h2/esp_efuse_fields.c
Normal file
55
components/efuse/esp32h2/esp_efuse_fields.c
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "stdlib.h"
|
||||
#include "esp_types.h"
|
||||
#include "esp32h2/rom/efuse.h"
|
||||
#include "assert.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "bootloader_random.h"
|
||||
#include "sys/param.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "efuse";
|
||||
|
||||
// Contains functions that provide access to efuse fields which are often used in IDF.
|
||||
|
||||
// Returns chip package from efuse
|
||||
uint32_t esp_efuse_get_pkg_ver(void)
|
||||
{
|
||||
uint32_t pkg_ver = 0;
|
||||
esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
|
||||
return pkg_ver;
|
||||
}
|
||||
|
||||
|
||||
esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme)
|
||||
{
|
||||
int cur_log_scheme = 0;
|
||||
esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2);
|
||||
if (!cur_log_scheme) { // not burned yet
|
||||
return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2);
|
||||
} else {
|
||||
return ESP_ERR_INVALID_STATE;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_disable_rom_download_mode(void)
|
||||
{
|
||||
return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
|
||||
{
|
||||
if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
|
||||
return ESP_ERR_INVALID_STATE;
|
||||
}
|
||||
return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
|
||||
}
|
||||
5
components/efuse/esp32h2/esp_efuse_rtc_calib.c
Normal file
5
components/efuse/esp32h2/esp_efuse_rtc_calib.c
Normal file
@ -0,0 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
1123
components/efuse/esp32h2/esp_efuse_table.c
Normal file
1123
components/efuse/esp32h2/esp_efuse_table.c
Normal file
File diff suppressed because it is too large
Load Diff
178
components/efuse/esp32h2/esp_efuse_table.csv
Normal file
178
components/efuse/esp32h2/esp_efuse_table.csv
Normal file
@ -0,0 +1,178 @@
|
||||
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1..-) | #
|
||||
# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
|
||||
# | ... | | | #
|
||||
# | EFUSE_BLK10)| | | #
|
||||
##########################################################################
|
||||
# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
|
||||
# !!!!!!!!!!! #
|
||||
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA BLOCK #
|
||||
##############################
|
||||
# EFUSE_RD_WR_DIS_REG #
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
|
||||
WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 1, 1, Write protection for SWAP_UART_SDIO_EN
|
||||
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
|
||||
WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
|
||||
WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
|
||||
WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
|
||||
WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
|
||||
WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
|
||||
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, Write protection for SEC_DPA_LEVEL
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
|
||||
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,EFUSE_BLK0, 19, 1, Write protection for SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
|
||||
WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
|
||||
WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
|
||||
WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
|
||||
WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
|
||||
WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
|
||||
WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
|
||||
WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
|
||||
WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA0_REG #
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, Read protection
|
||||
RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
|
||||
RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
|
||||
RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
|
||||
RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
|
||||
RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
|
||||
RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
|
||||
RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
SWAP_UART_SDIO_EN, EFUSE_BLK0, 39, 1, Swap pad of uart and sdio.
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode
|
||||
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, Disable USB_SERIAL_JTAG
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function
|
||||
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently.
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes.
|
||||
USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
|
||||
USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
|
||||
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio
|
||||
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA1_REG #
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA2_REG #
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
|
||||
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, Configures the clock random divide mode to determine the spa secure level
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA3_REG #
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode
|
||||
DIS_USB_PRINT, EFUSE_BLK0, 130, 1, Disable USB Print
|
||||
DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA4_REG #
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
|
||||
|
||||
# MAC_SPI_SYS BLOCK#
|
||||
#######################
|
||||
# RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2
|
||||
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
|
||||
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
|
||||
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
|
||||
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
|
||||
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
|
||||
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
|
||||
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
|
||||
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
|
||||
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
|
||||
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
|
||||
|
||||
# RD_MAC_SPI_SYS_3
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
|
||||
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
|
||||
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
|
||||
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
|
||||
|
||||
# RD_MAC_SPI_SYS_5
|
||||
# WAFER_VERSION_MINOR most significant bit
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
|
||||
|
||||
# SYS_DATA_PART1 BLOCK# - System configuration
|
||||
#######################
|
||||
# RD_SYS_PART1_DATA0 - rd_sys_part1_data3
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
|
||||
|
||||
# RD_SYS_PART1_DATA4
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2
|
||||
TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 140, 8, ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1
|
||||
|
||||
# RD_SYS_PART1_DATA5
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3
|
||||
|
||||
################
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
|
||||
|
||||
################
|
||||
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
|
||||
|
||||
# AUTO CONFIG DIG&RTC DBIAS#
|
||||
################
|
||||
K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO
|
||||
K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO
|
||||
V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20
|
||||
V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20
|
||||
DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt
|
||||
THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 87.
|
215
components/efuse/esp32h2/esp_efuse_utility.c
Normal file
215
components/efuse/esp32h2/esp_efuse_utility.c
Normal file
@ -0,0 +1,215 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "assert.h"
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
static const char *TAG = "efuse";
|
||||
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
/*Range addresses to read blocks*/
|
||||
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
|
||||
{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
|
||||
{EFUSE_RD_MAC_SYS_0_REG, EFUSE_RD_MAC_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_8M
|
||||
{EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
|
||||
{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
|
||||
{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
|
||||
{EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
|
||||
{EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
|
||||
{EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
|
||||
{EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
|
||||
{EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
|
||||
{EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
|
||||
};
|
||||
|
||||
static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
|
||||
|
||||
/*Range addresses to write blocks (it is not real regs, it is buffer) */
|
||||
const esp_efuse_range_addr_t range_write_addr_blocks[] = {
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
|
||||
};
|
||||
|
||||
#ifndef CONFIG_EFUSE_VIRTUAL
|
||||
// Update Efuse timing configuration
|
||||
static esp_err_t esp_efuse_set_timing(void)
|
||||
{
|
||||
// efuse clock is fixed.
|
||||
// An argument (0) is for compatibility and will be ignored.
|
||||
efuse_hal_set_timing(0);
|
||||
return ESP_OK;
|
||||
}
|
||||
#endif // ifndef CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
// Efuse read operation: copies data from physical efuses to efuse read registers.
|
||||
void esp_efuse_utility_clear_program_registers(void)
|
||||
{
|
||||
efuse_hal_read();
|
||||
efuse_hal_clear_program_registers();
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_utility_check_errors(void)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
// Burn values written to the efuse write registers
|
||||
esp_err_t esp_efuse_utility_burn_chip(void)
|
||||
{
|
||||
esp_err_t error = ESP_OK;
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
|
||||
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
int subblock = 0;
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
|
||||
esp_efuse_utility_write_efuses_to_flash();
|
||||
#endif
|
||||
#else // CONFIG_EFUSE_VIRTUAL
|
||||
if (esp_efuse_set_timing() != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Efuse fields are not burnt");
|
||||
} else {
|
||||
// Permanently update values written to the efuse write registers
|
||||
// It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
|
||||
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
bool need_burn_block = false;
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
if (REG_READ(addr_wr_block) != 0) {
|
||||
need_burn_block = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!need_burn_block) {
|
||||
continue;
|
||||
}
|
||||
if (error) {
|
||||
// It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
|
||||
// in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
|
||||
ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
|
||||
continue;
|
||||
}
|
||||
efuse_hal_clear_program_registers();
|
||||
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
uint8_t block_rs[12];
|
||||
efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstringop-overflow"
|
||||
#pragma GCC diagnostic ignored "-Warray-bounds"
|
||||
memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
|
||||
#pragma GCC diagnostic pop
|
||||
}
|
||||
unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
|
||||
unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
|
||||
memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
|
||||
|
||||
uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
|
||||
#pragma GCC diagnostic push
|
||||
#if __GNUC__ >= 11
|
||||
#pragma GCC diagnostic ignored "-Wstringop-overread"
|
||||
#endif
|
||||
#pragma GCC diagnostic ignored "-Warray-bounds"
|
||||
memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
|
||||
#pragma GCC diagnostic pop
|
||||
int repeat_burn_op = 1;
|
||||
bool correct_written_data;
|
||||
bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block);
|
||||
if (coding_error_before) {
|
||||
ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
|
||||
}
|
||||
bool coding_error_occurred;
|
||||
|
||||
do {
|
||||
ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
|
||||
efuse_hal_program(num_block); // BURN a block
|
||||
|
||||
bool coding_error_after;
|
||||
for (unsigned i = 0; i < 5; i++) {
|
||||
efuse_hal_read();
|
||||
coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
|
||||
if (coding_error_after == true) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false;
|
||||
if (coding_error_occurred) {
|
||||
ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
|
||||
}
|
||||
|
||||
correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len);
|
||||
if (!correct_written_data || coding_error_occurred) {
|
||||
ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstringop-overflow"
|
||||
#pragma GCC diagnostic ignored "-Warray-bounds"
|
||||
memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
|
||||
#pragma GCC diagnostic pop
|
||||
}
|
||||
|
||||
} while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
|
||||
|
||||
if (coding_error_occurred) {
|
||||
ESP_LOGW(TAG, "Coding error was not fixed");
|
||||
if (num_block == 0) {
|
||||
ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
|
||||
error = ESP_FAIL;
|
||||
}
|
||||
}
|
||||
if (!correct_written_data) {
|
||||
ESP_LOGE(TAG, "Written data are incorrect");
|
||||
error = ESP_FAIL;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
esp_efuse_utility_reset();
|
||||
return error;
|
||||
}
|
||||
|
||||
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
|
||||
// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
|
||||
// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
|
||||
// They will be filled during the burn operation.
|
||||
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
|
||||
{
|
||||
// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
|
||||
for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
|
||||
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
if (REG_READ(addr_wr_block)) {
|
||||
int num_reg = 0;
|
||||
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
|
||||
if (esp_efuse_utility_read_reg(num_block, num_reg)) {
|
||||
ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
|
||||
return ESP_ERR_CODING;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
79
components/efuse/esp32h2/include/esp_efuse_chip.h
Normal file
79
components/efuse/esp32h2/include/esp_efuse_chip.h
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of eFuse blocks ESP32H2
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
|
||||
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
|
||||
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
|
||||
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
|
||||
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
|
||||
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
|
||||
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
|
||||
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
|
||||
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
|
||||
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY_MAX = 10,
|
||||
|
||||
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
|
||||
EFUSE_BLK_MAX
|
||||
} esp_efuse_block_t;
|
||||
|
||||
/**
|
||||
* @brief Type of coding scheme
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_CODING_SCHEME_NONE = 0, /**< None */
|
||||
EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */
|
||||
} esp_efuse_coding_scheme_t;
|
||||
|
||||
/**
|
||||
* @brief Type of key purpose
|
||||
*/
|
||||
typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
|
||||
ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */
|
||||
} esp_efuse_purpose_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
59
components/efuse/esp32h2/include/esp_efuse_rtc_calib.h
Normal file
59
components/efuse/esp32h2/include/esp_efuse_rtc_calib.h
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <esp_types.h>
|
||||
#include <esp_err.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//This is the ADC calibration value version burnt in efuse
|
||||
#define ESP_EFUSE_ADC_CALIB_VER 1
|
||||
|
||||
/**
|
||||
* @brief Get the RTC calibration efuse version
|
||||
*
|
||||
* @return Version of the stored efuse
|
||||
*/
|
||||
int esp_efuse_rtc_calib_get_ver(void);
|
||||
|
||||
/**
|
||||
* @brief Get the init code in the efuse, for the corresponding attenuation.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param adc_unit ADC unit. Not used, for compatibility. On esp32h2, for calibration v1, both ADC units use the same init code (calibrated by ADC1)
|
||||
* @param atten Attenuation of the init code
|
||||
* @return The init code stored in efuse
|
||||
*/
|
||||
uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten);
|
||||
|
||||
/**
|
||||
* @brief Get the calibration digits stored in the efuse, and the corresponding voltage.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param atten Attenuation to use
|
||||
* @param out_digi Output buffer of the digits
|
||||
* @param out_vol_mv Output of the voltage, in mV
|
||||
* @return
|
||||
* - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid
|
||||
* - ESP_OK: if success
|
||||
*/
|
||||
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv);
|
||||
|
||||
/**
|
||||
* @brief Get the temperature sensor calibration number delta_T stored in the efuse.
|
||||
*
|
||||
* @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse.
|
||||
*
|
||||
* @return ESP_OK if get the calibration value successfully.
|
||||
* ESP_ERR_INVALID_ARG if can't get the calibration value.
|
||||
*/
|
||||
esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
145
components/efuse/esp32h2/include/esp_efuse_table.h
Normal file
145
components/efuse/esp32h2/include/esp_efuse_table.h
Normal file
@ -0,0 +1,145 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */
|
||||
|
||||
#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
|
||||
|
||||
#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
21
components/efuse/esp32h2/private_include/esp_efuse_utility.h
Normal file
21
components/efuse/esp32h2/private_include/esp_efuse_utility.h
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */
|
||||
|
||||
#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
|
||||
|
||||
#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
4
components/efuse/esp32h2/sources.cmake
Normal file
4
components/efuse/esp32h2/sources.cmake
Normal file
@ -0,0 +1,4 @@
|
||||
set(EFUSE_SOC_SRCS "esp_efuse_table.c"
|
||||
"esp_efuse_fields.c"
|
||||
"esp_efuse_rtc_calib.c"
|
||||
"esp_efuse_utility.c")
|
||||
@ -32,6 +32,16 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/deprecated/${target}/esp_adc_cal_legacy.c
|
||||
list(APPEND srcs "deprecated/${target}/esp_adc_cal_legacy.c")
|
||||
endif()
|
||||
|
||||
# ESP32H2-TODO
|
||||
if(CONFIG_IDF_TARGET_ESP32H2)
|
||||
# TODO: IDF-6214
|
||||
list(REMOVE_ITEM srcs
|
||||
"adc_cali_curve_fitting.c"
|
||||
"adc_oneshot.c"
|
||||
"adc_common.c"
|
||||
)
|
||||
endif()
|
||||
|
||||
idf_component_register(SRCS ${srcs}
|
||||
INCLUDE_DIRS ${includes}
|
||||
PRIV_REQUIRES driver efuse
|
||||
|
||||
140
components/esp_gdbstub/esp32h2/gdbstub_esp32h2.c
Normal file
140
components/esp_gdbstub/esp32h2/gdbstub_esp32h2.c
Normal file
@ -0,0 +1,140 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#include "soc/uart_periph.h"
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/usb_serial_jtag_struct.h"
|
||||
#include "hal/usb_serial_jtag_ll.h"
|
||||
#include "esp_gdbstub_common.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#define UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
|
||||
|
||||
#define GDBSTUB_MEM_REGION_COUNT 9
|
||||
|
||||
#define UART_REG_FIELD_LEN 0x84
|
||||
|
||||
typedef struct {
|
||||
intptr_t lower;
|
||||
intptr_t upper;
|
||||
} mem_bound_t;
|
||||
|
||||
static const mem_bound_t mem_region_table [GDBSTUB_MEM_REGION_COUNT] =
|
||||
{
|
||||
{SOC_DROM_LOW, SOC_DROM_HIGH},
|
||||
{SOC_IROM_LOW, SOC_IROM_HIGH},
|
||||
{SOC_IRAM_LOW, SOC_IRAM_HIGH},
|
||||
{SOC_DRAM_LOW, SOC_DRAM_HIGH},
|
||||
{SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH},
|
||||
{SOC_DROM_MASK_LOW, SOC_DROM_MASK_HIGH},
|
||||
{SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH},
|
||||
// RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them
|
||||
// We shouldn't read the uart registers since it will disturb the debugging via UART,
|
||||
// so skip UART part of the peripheral registers.
|
||||
{DR_REG_UART_BASE + UART_REG_FIELD_LEN, SOC_PERIPHERAL_HIGH},
|
||||
{SOC_DEBUG_LOW, SOC_DEBUG_HIGH},
|
||||
};
|
||||
|
||||
static inline bool check_inside_valid_region(intptr_t addr)
|
||||
{
|
||||
for (size_t i = 0; i < GDBSTUB_MEM_REGION_COUNT; i++) {
|
||||
if (addr >= mem_region_table[i].lower && addr < mem_region_table[i].upper) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void esp_gdbstub_target_init()
|
||||
{
|
||||
}
|
||||
|
||||
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
|
||||
|
||||
int esp_gdbstub_getchar()
|
||||
{
|
||||
uint8_t c;
|
||||
//retry the read until we succeed
|
||||
while (usb_serial_jtag_ll_read_rxfifo(&c, 1)==0) ;
|
||||
return c;
|
||||
}
|
||||
|
||||
void esp_gdbstub_putchar(int c)
|
||||
{
|
||||
uint8_t cc=c;
|
||||
//retry the write until we succeed
|
||||
while (usb_serial_jtag_ll_write_txfifo(&cc, 1)<1) ;
|
||||
}
|
||||
|
||||
void esp_gdbstub_flush()
|
||||
{
|
||||
usb_serial_jtag_ll_txfifo_flush();
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
//assume UART gdbstub channel
|
||||
|
||||
int esp_gdbstub_getchar()
|
||||
{
|
||||
while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) {
|
||||
;
|
||||
}
|
||||
return REG_READ(UART_FIFO_AHB_REG(UART_NUM));
|
||||
}
|
||||
|
||||
void esp_gdbstub_putchar(int c)
|
||||
{
|
||||
while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) {
|
||||
;
|
||||
}
|
||||
REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c);
|
||||
}
|
||||
|
||||
void esp_gdbstub_flush()
|
||||
{
|
||||
//not needed for uart
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
int esp_gdbstub_readmem(intptr_t addr)
|
||||
{
|
||||
if (!check_inside_valid_region(addr)) {
|
||||
/* see esp_cpu_configure_region_protection */
|
||||
return -1;
|
||||
}
|
||||
uint32_t val_aligned = *(uint32_t *)(addr & (~3));
|
||||
uint32_t shift = (addr & 3) * 8;
|
||||
return (val_aligned >> shift) & 0xff;
|
||||
}
|
||||
|
||||
int esp_gdbstub_writemem(unsigned int addr, unsigned char data)
|
||||
{
|
||||
if (!check_inside_valid_region(addr)) {
|
||||
/* see esp_cpu_configure_region_protection */
|
||||
return -1;
|
||||
}
|
||||
|
||||
int *i = (int *)(addr & (~3));
|
||||
if ((addr & 3) == 0) {
|
||||
*i = (*i & 0xffffff00) | (data << 0);
|
||||
}
|
||||
if ((addr & 3) == 1) {
|
||||
*i = (*i & 0xffff00ff) | (data << 8);
|
||||
}
|
||||
if ((addr & 3) == 2) {
|
||||
*i = (*i & 0xff00ffff) | (data << 16);
|
||||
}
|
||||
if ((addr & 3) == 3) {
|
||||
*i = (*i & 0x00ffffff) | (data << 24);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
7
components/esp_gdbstub/esp32h2/gdbstub_target_config.h
Normal file
7
components/esp_gdbstub/esp32h2/gdbstub_target_config.h
Normal file
@ -0,0 +1,7 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
@ -114,7 +114,7 @@ static uint32_t gdbstub_hton(uint32_t i)
|
||||
return __builtin_bswap32(i);
|
||||
}
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5653
|
||||
static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
#else
|
||||
static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
|
||||
|
||||
@ -73,6 +73,11 @@ if(NOT BOOTLOADER_BUILD)
|
||||
if(CONFIG_SOC_MODEM_CLOCK_IS_INDEPENDENT)
|
||||
list(APPEND srcs "modem_clock.c")
|
||||
endif()
|
||||
if(CONFIG_IDF_TARGET_ESP32H2)
|
||||
list(REMOVE_ITEM srcs
|
||||
"adc_share_hw_ctrl.c" # TODO: IDF-6215
|
||||
)
|
||||
endif()
|
||||
else()
|
||||
# Requires "_esp_error_check_failed()" function
|
||||
list(APPEND priv_requires "esp_system")
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
// TODO: IDF-5645
|
||||
#if CONFIG_IDF_TARGET_ESP32C6
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "soc/lp_aon_reg.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
#define SYSTEM_CPU_PER_CONF_REG PCR_CPU_WAITI_CONF_REG
|
||||
@ -91,7 +91,7 @@ void esp_cpu_unstall(int core_id)
|
||||
|
||||
void esp_cpu_reset(int core_id)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2// TODO: IDF-5645
|
||||
SET_PERI_REG_MASK(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET);
|
||||
#else
|
||||
assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM);
|
||||
@ -143,7 +143,7 @@ static bool is_intr_num_resv(int intr_num)
|
||||
uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8);
|
||||
|
||||
// int_num 0,3,4,7 are inavaliable for PULP cpu
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5728 replace with a better macro name
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2// TODO: IDF-5728 replace with a better macro name
|
||||
reserved |= BIT(0) | BIT(3) | BIT(4) | BIT(7);
|
||||
#endif
|
||||
|
||||
@ -693,6 +693,88 @@ void esp_cpu_configure_region_protection(void)
|
||||
PMP_ENTRY_SET(13, pmpaddr13, PMP_NAPOT | PMP_RW);
|
||||
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
// ESP32H2-TODO: IDF-6452
|
||||
void esp_cpu_configure_region_protection(void)
|
||||
{
|
||||
/* Notes on implementation:
|
||||
*
|
||||
* 1) Note: ESP32-H2 CPU doesn't support overlapping PMP regions
|
||||
*
|
||||
* 2) Therefore, we use TOR (top of range) entries to map the whole address
|
||||
* space, bottom to top.
|
||||
*
|
||||
* 3) There are not enough entries to describe all the memory regions 100% accurately.
|
||||
*
|
||||
* 4) This means some gaps (invalid memory) are accessible. Priority for extending regions
|
||||
* to cover gaps is to extend read-only or read-execute regions or read-only regions only
|
||||
* (executing unmapped addresses should always fault with invalid instruction, read-only means
|
||||
* stores will correctly fault even if reads may return some invalid value.)
|
||||
*
|
||||
* 5) Entries are grouped in order with some static asserts to try and verify everything is
|
||||
* correct.
|
||||
*/
|
||||
const unsigned NONE = PMP_L | PMP_TOR;
|
||||
const unsigned RW = PMP_L | PMP_TOR | PMP_R | PMP_W;
|
||||
const unsigned RX = PMP_L | PMP_TOR | PMP_R | PMP_X;
|
||||
const unsigned RWX = PMP_L | PMP_TOR | PMP_R | PMP_W | PMP_X;
|
||||
|
||||
// 1. Gap at bottom of address space
|
||||
PMP_ENTRY_SET(0, SOC_DEBUG_LOW, NONE);
|
||||
|
||||
// 2. Debug region
|
||||
PMP_ENTRY_SET(1, SOC_DEBUG_HIGH, RWX);
|
||||
_Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region");
|
||||
|
||||
// 3. Gap between debug region & IROM
|
||||
PMP_ENTRY_SET(2, SOC_IROM_MASK_LOW, NONE);
|
||||
_Static_assert(SOC_DEBUG_HIGH < SOC_IROM_MASK_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 4. ROM
|
||||
PMP_ENTRY_SET(3, SOC_DROM_MASK_HIGH, RX);
|
||||
_Static_assert(SOC_IROM_MASK_LOW < SOC_DROM_MASK_HIGH, "Invalid ROM region");
|
||||
|
||||
// 5. Gap between ROM & RAM
|
||||
PMP_ENTRY_SET(4, SOC_IRAM_LOW, NONE);
|
||||
_Static_assert(SOC_DROM_MASK_HIGH < SOC_IRAM_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 6. RAM
|
||||
PMP_ENTRY_SET(5, SOC_IRAM_HIGH, RWX);
|
||||
_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
|
||||
|
||||
// 7. Gap between DRAM and I_Cache
|
||||
PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE);
|
||||
_Static_assert(SOC_IRAM_HIGH < SOC_IROM_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 8. I_Cache (flash)
|
||||
PMP_ENTRY_SET(7, SOC_IROM_HIGH, RWX);
|
||||
_Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I_Cache region");
|
||||
|
||||
// 9. D_Cache (flash)
|
||||
PMP_ENTRY_SET(8, SOC_DROM_HIGH, RW);
|
||||
_Static_assert(SOC_DROM_LOW < SOC_DROM_HIGH, "Invalid D_Cache region");
|
||||
|
||||
// 10. Gap between D_Cache & LP_RAM
|
||||
PMP_ENTRY_SET(9, SOC_RTC_IRAM_LOW, NONE);
|
||||
_Static_assert(SOC_DROM_HIGH < SOC_RTC_IRAM_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 16. LP memory
|
||||
PMP_ENTRY_SET(10, SOC_RTC_IRAM_HIGH, RWX);
|
||||
_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
|
||||
|
||||
// 17. Gap between LP memory & peripheral addresses
|
||||
PMP_ENTRY_SET(11, SOC_PERIPHERAL_LOW, NONE);
|
||||
_Static_assert(SOC_RTC_IRAM_HIGH < SOC_PERIPHERAL_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 18. Peripheral addresses
|
||||
PMP_ENTRY_SET(12, SOC_PERIPHERAL_HIGH, RW);
|
||||
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
|
||||
|
||||
// 19. End of address space
|
||||
PMP_ENTRY_SET(13, UINT32_MAX, NONE); // all but last 4 bytes
|
||||
PMP_ENTRY_SET(14, UINT32_MAX, PMP_L | PMP_NA4); // last 4 bytes
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------------- Debugging ------------------------------------------------------
|
||||
|
||||
@ -27,6 +27,7 @@ typedef enum {
|
||||
CHIP_ESP32H4 = 6, //!< ESP32-H4
|
||||
CHIP_ESP32C2 = 12, //!< ESP32-C2
|
||||
CHIP_ESP32C6 = 13, //!< ESP32-C6
|
||||
CHIP_ESP32H2 = 16, //!< ESP32-H2
|
||||
CHIP_POSIX_LINUX = 999, //!< The code is running on POSIX/Linux simulator
|
||||
} esp_chip_model_t;
|
||||
|
||||
|
||||
@ -0,0 +1,68 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Acquire lock for HMAC cryptography peripheral
|
||||
*
|
||||
* Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral
|
||||
*/
|
||||
void esp_crypto_hmac_lock_acquire(void);
|
||||
|
||||
/**
|
||||
* @brief Release lock for HMAC cryptography peripheral
|
||||
*
|
||||
* Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral
|
||||
*/
|
||||
void esp_crypto_hmac_lock_release(void);
|
||||
|
||||
/**
|
||||
* @brief Acquire lock for DS cryptography peripheral
|
||||
*
|
||||
* Internally also locks the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals
|
||||
*/
|
||||
void esp_crypto_ds_lock_acquire(void);
|
||||
|
||||
/**
|
||||
* @brief Release lock for DS cryptography peripheral
|
||||
*
|
||||
* Internally also releases the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals
|
||||
*/
|
||||
void esp_crypto_ds_lock_release(void);
|
||||
|
||||
/**
|
||||
* @brief Acquire lock for the SHA and AES cryptography peripheral.
|
||||
*
|
||||
*/
|
||||
void esp_crypto_sha_aes_lock_acquire(void);
|
||||
|
||||
/**
|
||||
* @brief Release lock for the SHA and AES cryptography peripheral.
|
||||
*
|
||||
*/
|
||||
void esp_crypto_sha_aes_lock_release(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Acquire lock for the mpi cryptography peripheral.
|
||||
*
|
||||
*/
|
||||
void esp_crypto_mpi_lock_acquire(void);
|
||||
|
||||
/**
|
||||
* @brief Release lock for the mpi/rsa cryptography peripheral.
|
||||
*
|
||||
*/
|
||||
void esp_crypto_mpi_lock_release(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
32
components/esp_hw_support/include/soc/esp32h2/rtc.h
Normal file
32
components/esp_hw_support/include/soc/esp32h2/rtc.h
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @file esp32h2/rtc.h
|
||||
*
|
||||
* This file contains declarations of rtc related functions.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get current value of RTC counter in microseconds
|
||||
*
|
||||
* Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
|
||||
*
|
||||
* @return current value of RTC counter in microseconds
|
||||
*/
|
||||
uint64_t esp_rtc_get_time_us(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
//////////////////////////////////////////////////////////
|
||||
// ESP32-H2 PMS memory protection types
|
||||
//
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// ESP32H2-TODO: IDF-6332
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -13,7 +13,7 @@ entries:
|
||||
cpu: esp_cpu_compare_and_set (noflash)
|
||||
esp_memory_utils (noflash)
|
||||
rtc_clk (noflash)
|
||||
if IDF_TARGET_ESP32C6 = n: # TODO: IDF-5645
|
||||
if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n: # TODO: IDF-5645
|
||||
rtc_init:rtc_vddsdio_set_config (noflash)
|
||||
rtc_pm (noflash_text)
|
||||
rtc_sleep (noflash_text)
|
||||
|
||||
@ -0,0 +1,14 @@
|
||||
set(srcs "rtc_clk_init.c"
|
||||
"rtc_clk.c"
|
||||
# "rtc_init.c" // ESP32H2-TODO
|
||||
# "rtc_pm.c" // ESP32H2-TODO
|
||||
# "rtc_sleep.c" // ESP32H2-TODO
|
||||
"rtc_time.c"
|
||||
"chip_info.c"
|
||||
)
|
||||
|
||||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . private_include)
|
||||
target_include_directories(${COMPONENT_LIB} PRIVATE ../hal)
|
||||
41
components/esp_hw_support/port/esp32h2/Kconfig.hw_support
Normal file
41
components/esp_hw_support/port/esp32h2/Kconfig.hw_support
Normal file
@ -0,0 +1,41 @@
|
||||
choice ESP32H2_REV_MIN
|
||||
prompt "Minimum Supported ESP32-C6 Revision"
|
||||
default ESP32H2_REV_MIN_0
|
||||
help
|
||||
Required minimum chip revision. ESP-IDF will check for it and
|
||||
reject to boot if the chip revision fails the check.
|
||||
This ensures the chip used will have some modifications (features, or bugfixes).
|
||||
|
||||
The complied binary will only support chips above this revision,
|
||||
this will also help to reduce binary size.
|
||||
|
||||
config ESP32H2_REV_MIN_0
|
||||
bool "Rev v0.0"
|
||||
endchoice
|
||||
|
||||
config ESP32H2_REV_MIN_FULL
|
||||
int
|
||||
default 0 if ESP32H2_REV_MIN_0
|
||||
|
||||
config ESP_REV_MIN_FULL
|
||||
int
|
||||
default ESP32H2_REV_MIN_FULL
|
||||
|
||||
#
|
||||
# MAX Revision
|
||||
#
|
||||
|
||||
comment "Maximum Supported ESP32-H2 Revision (Rev v0.99)"
|
||||
# Maximum revision that IDF supports.
|
||||
# It can not be changed by user.
|
||||
# Only Espressif can change it when a new version will be supported in IDF.
|
||||
# Supports all chips starting from ESP32H2_REV_MIN_FULL to ESP32H2_REV_MAX_FULL
|
||||
|
||||
config ESP32H2_REV_MAX_FULL
|
||||
int
|
||||
default 99
|
||||
# keep in sync the "Maximum Supported Revision" description with this value
|
||||
|
||||
config ESP_REV_MAX_FULL
|
||||
int
|
||||
default ESP32H2_REV_MAX_FULL
|
||||
@ -0,0 +1 @@
|
||||
# ESP32H2-TODO: MAC support
|
||||
39
components/esp_hw_support/port/esp32h2/Kconfig.rtc
Normal file
39
components/esp_hw_support/port/esp32h2/Kconfig.rtc
Normal file
@ -0,0 +1,39 @@
|
||||
choice RTC_CLK_SRC
|
||||
prompt "RTC clock source"
|
||||
default RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
Choose which clock is used as RTC clock source.
|
||||
|
||||
config RTC_CLK_SRC_INT_RC
|
||||
bool "Internal 136kHz RC oscillator"
|
||||
config RTC_CLK_SRC_EXT_CRYS
|
||||
bool "External 32kHz crystal"
|
||||
select ESP_SYSTEM_RTC_EXT_XTAL
|
||||
config RTC_CLK_SRC_EXT_OSC
|
||||
bool "External 32kHz oscillator at 32K_XP pin"
|
||||
select ESP_SYSTEM_RTC_EXT_OSC
|
||||
config RTC_CLK_SRC_INT_RC32K
|
||||
bool "Internal 32kHz RC oscillator"
|
||||
endchoice
|
||||
|
||||
config RTC_CLK_CAL_CYCLES
|
||||
int "Number of cycles for RTC_SLOW_CLK calibration"
|
||||
default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
|
||||
default 1024 if RTC_CLK_SRC_INT_RC
|
||||
range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
|
||||
range 0 32766 if RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
When the startup code initializes RTC_SLOW_CLK, it can perform
|
||||
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
|
||||
frequency. This option sets the number of RTC_SLOW_CLK cycles measured
|
||||
by the calibration routine. Higher numbers increase calibration
|
||||
precision, which may be important for applications which spend a lot of
|
||||
time in deep sleep. Lower numbers reduce startup time.
|
||||
|
||||
When this option is set to 0, clock calibration will not be performed at
|
||||
startup, and approximate clock frequencies will be assumed:
|
||||
|
||||
- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
|
||||
- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
|
||||
In case more value will help improve the definition of the launch of the crystal.
|
||||
If the crystal could not start, it will be switched to internal RC.
|
||||
18
components/esp_hw_support/port/esp32h2/chip_info.c
Normal file
18
components/esp_hw_support/port/esp32h2/chip_info.c
Normal file
@ -0,0 +1,18 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include "esp_chip_info.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
void esp_chip_info(esp_chip_info_t *out_info)
|
||||
{
|
||||
memset(out_info, 0, sizeof(*out_info));
|
||||
out_info->model = CHIP_ESP32H2;
|
||||
out_info->revision = efuse_hal_chip_revision();
|
||||
out_info->cores = 1;
|
||||
out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE;
|
||||
}
|
||||
22
components/esp_hw_support/port/esp32h2/i2c_brownout.h
Normal file
22
components/esp_hw_support/port/esp32h2/i2c_brownout.h
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file i2c_brownout.h
|
||||
* @brief Register definitions for brownout detector
|
||||
*
|
||||
* This file lists register fields of the brownout detector, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in i2c_rtc_clk.h.
|
||||
*/
|
||||
|
||||
#define I2C_BOD 0x61
|
||||
#define I2C_BOD_HOSTID 1
|
||||
|
||||
#define I2C_BOD_THRESHOLD 0x5
|
||||
#define I2C_BOD_THRESHOLD_MSB 2
|
||||
#define I2C_BOD_THRESHOLD_LSB 0
|
||||
71
components/esp_hw_support/port/esp32h2/rtc_clk.c
Normal file
71
components/esp_hw_support/port/esp32h2/rtc_clk.c
Normal file
@ -0,0 +1,71 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <assert.h>
|
||||
#include <stdlib.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp32h2/rom/ets_sys.h"
|
||||
#include "esp32h2/rom/rtc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "esp_hw_log.h"
|
||||
#include "esp_rom_sys.h"
|
||||
#include "hal/usb_serial_jtag_ll.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
#include "soc/lp_clkrst_reg.h"
|
||||
|
||||
|
||||
static const char *TAG = "rtc_clk";
|
||||
|
||||
soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
|
||||
{
|
||||
// ESP32H2-TODO: IDF-6254
|
||||
return REG_GET_FIELD(LP_CLKRST_LP_CLK_CONF_REG, LP_CLKRST_SLOW_CLK_SEL);
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_slow_freq_get_hz(void)
|
||||
{
|
||||
// ESP32H2-TODO: IDF-6254
|
||||
switch (rtc_clk_slow_freq_get()) {
|
||||
case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
|
||||
case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
|
||||
case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
|
||||
default: return 0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rtc_clk_cpu_freq_set_xtal(void)
|
||||
{
|
||||
// ESP32H2-TODO: IDF-6254
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
ESP_EARLY_LOGW(TAG, "rtc_clk_xtal_freq_get() has not benn implemented yet");
|
||||
// ESP32H2-TODO: IDF-6254
|
||||
return 32;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
// ESP32H2-TODO: IDF-6254
|
||||
}
|
||||
|
||||
void rtc_clk_apb_freq_update(uint32_t apb_freq)
|
||||
{
|
||||
// ESP32H2-TODO: IDF-6254
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_apb_freq_get(void)
|
||||
{
|
||||
ESP_EARLY_LOGW(TAG, "rtc_clk_apb_freq_get() has not benn implemented yet");
|
||||
// ESP32H2-TODO: IDF-6254
|
||||
return 0;
|
||||
}
|
||||
84
components/esp_hw_support/port/esp32h2/rtc_clk_init.c
Normal file
84
components/esp_hw_support/port/esp32h2/rtc_clk_init.c
Normal file
@ -0,0 +1,84 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include "esp32h2/rom/ets_sys.h"
|
||||
#include "esp32h2/rom/rtc.h"
|
||||
#include "esp32h2/rom/uart.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
#include "esp_hw_log.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_rom_uart.h"
|
||||
|
||||
static const char *TAG = "rtc_clk_init";
|
||||
|
||||
void rtc_clk_init(rtc_clk_config_t cfg)
|
||||
{
|
||||
ESP_HW_LOGW(TAG, "rtc_clk_init() has not been implemented yet");
|
||||
#if 0 // ESP32H2-TODO
|
||||
rtc_cpu_freq_config_t old_config, new_config;
|
||||
|
||||
/* Set tuning parameters for 8M and 150k clocks.
|
||||
* Note: this doesn't attempt to set the clocks to precise frequencies.
|
||||
* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
|
||||
* - SCK_DCAP value controls tuning of 150k clock.
|
||||
* The higher the value of DCAP is, the lower is the frequency.
|
||||
* - CK8M_DFREQ value controls tuning of 8M clock.
|
||||
* CLK_8M_DFREQ constant gives the best temperature characteristics.
|
||||
*/
|
||||
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
|
||||
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
|
||||
|
||||
/* Configure 150k clock division */
|
||||
rtc_clk_divider_set(cfg.clk_rtc_clk_div);
|
||||
|
||||
/* Configure 8M clock division */
|
||||
rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
|
||||
|
||||
/* Reset (disable) i2c internal bus for all regi2c registers */
|
||||
regi2c_ctrl_ll_i2c_reset(); // TODO: This should be move out from rtc_clk_init
|
||||
/* Enable the internal bus used to configure BBPLL */
|
||||
regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
rtc_clk_apb_freq_update(xtal_freq * MHZ);
|
||||
|
||||
/* Set CPU frequency */
|
||||
rtc_clk_cpu_freq_get_config(&old_config);
|
||||
uint32_t freq_before = old_config.freq_mhz;
|
||||
bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
|
||||
if (!res) {
|
||||
ESP_HW_LOGE(TAG, "invalid CPU frequency value");
|
||||
abort();
|
||||
}
|
||||
rtc_clk_cpu_freq_set_config(&new_config);
|
||||
|
||||
/* Re-calculate the ccount to make time calculation correct. */
|
||||
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
|
||||
|
||||
/* Slow & fast clocks setup */
|
||||
// We will not power off RC_FAST in bootloader stage even if it is not being used as any
|
||||
// cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
|
||||
bool need_rc_fast_en = true;
|
||||
bool need_rc_fast_d256_en = false;
|
||||
if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
rtc_clk_32k_enable(true);
|
||||
} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
|
||||
need_rc_fast_d256_en = true;
|
||||
}
|
||||
rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en);
|
||||
rtc_clk_fast_src_set(cfg.fast_clk_src);
|
||||
rtc_clk_slow_src_set(cfg.slow_clk_src);
|
||||
#endif
|
||||
}
|
||||
102
components/esp_hw_support/port/esp32h2/rtc_time.c
Normal file
102
components/esp_hw_support/port/esp32h2/rtc_time.c
Normal file
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp32h2/rom/ets_sys.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/timer_group_reg.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
|
||||
* This feature counts the number of XTAL clock cycles within a given number of
|
||||
* RTC_SLOW_CLK cycles.
|
||||
*
|
||||
* Slow clock calibration feature has two modes of operation: one-off and cycling.
|
||||
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
|
||||
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
|
||||
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
|
||||
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
|
||||
* enabled using TIMG_RTC_CALI_START bit.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
|
||||
* @param cal_clk which clock to calibrate
|
||||
* @param slowclk_cycles number of slow clock cycles to count
|
||||
* @return number of XTAL clock cycles within the given number of slow clock cycles
|
||||
*/
|
||||
// ESP32H2-TODO
|
||||
static const char *TAG = "rtc_time";
|
||||
|
||||
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_clk_cal_internal() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_clk_cal_ratio() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_clk_cal() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_time_us_to_slowclk() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_time_slowclk_to_us() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint64_t rtc_time_get(void)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_time_get() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint64_t rtc_light_slp_time_get(void)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_light_slp_time_get() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint64_t rtc_deep_slp_time_get(void)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_deep_slp_time_get() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
|
||||
{
|
||||
// ESP32H2-TODO
|
||||
ESP_EARLY_LOGW(TAG, "rtc_clk_freq_cal() has not been implemented yet");
|
||||
return 0;
|
||||
}
|
||||
21
components/esp_hw_support/port/esp32h2/systimer.c
Normal file
21
components/esp_hw_support/port/esp32h2/systimer.c
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "esp_private/systimer.h"
|
||||
|
||||
/**
|
||||
* @brief systimer's clock source is fixed to XTAL (32MHz), and has a fixed fractional divider (2).
|
||||
* So the resolution of the systimer is 32MHz/2 = 16MHz. Please check again: IDF-6484
|
||||
*/
|
||||
uint64_t systimer_ticks_to_us(uint64_t ticks)
|
||||
{
|
||||
return ticks / 16;
|
||||
}
|
||||
|
||||
uint64_t systimer_us_to_ticks(uint64_t us)
|
||||
{
|
||||
return us * 16;
|
||||
}
|
||||
@ -27,11 +27,11 @@
|
||||
#endif
|
||||
#include "sys/queue.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
|
||||
static const char *TAG = "rtc_module";
|
||||
#endif
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
|
||||
|
||||
#define NOT_REGISTERED (-1)
|
||||
|
||||
@ -100,7 +100,7 @@ out:
|
||||
|
||||
esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t rtc_intr_mask, uint32_t flags)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
|
||||
ESP_EARLY_LOGW(TAG, "rtc_isr_register() has not been implemented yet");
|
||||
return ESP_OK;
|
||||
#else
|
||||
@ -131,7 +131,7 @@ esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t r
|
||||
|
||||
esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
|
||||
ESP_EARLY_LOGW(TAG, "rtc_isr_deregister() has not been implemented yet");
|
||||
return ESP_OK;
|
||||
#else
|
||||
@ -160,7 +160,7 @@ esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
|
||||
#endif
|
||||
}
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
|
||||
/**
|
||||
* @brief This helper function can be used to avoid the interrupt to be triggered with cache disabled.
|
||||
* There are lots of different signals on RTC module (i.e. sleep_wakeup, wdt, brownout_detect, etc.)
|
||||
@ -183,7 +183,7 @@ static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask)
|
||||
|
||||
IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)
|
||||
{
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
|
||||
if (rtc_isr_cpu == cpu) {
|
||||
rtc_intr_enabled |= RTCCNTL.int_ena.val;
|
||||
RTCCNTL.int_ena.val &= rtc_intr_cache;
|
||||
@ -193,7 +193,7 @@ IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)
|
||||
|
||||
IRAM_ATTR void rtc_isr_noniram_enable(uint32_t cpu)
|
||||
{
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
|
||||
if (rtc_isr_cpu == cpu) {
|
||||
RTCCNTL.int_ena.val = rtc_intr_enabled;
|
||||
rtc_intr_enabled = 0;
|
||||
|
||||
@ -107,7 +107,7 @@ void esp_sleep_enable_gpio_switch(bool enable)
|
||||
#endif // SOC_GPIO_SUPPORT_SLP_SWITCH
|
||||
|
||||
// TODO: IDF-6051, IDF-6052
|
||||
#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6
|
||||
#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
|
||||
IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
|
||||
{
|
||||
gpio_hal_context_t gpio_hal = {
|
||||
|
||||
@ -57,31 +57,25 @@
|
||||
#include "esp_private/gpio.h"
|
||||
#include "esp_private/sleep_gpio.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/cache.h"
|
||||
#include "esp32s2/rom/rtc.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "esp_private/gpio.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/cache.h"
|
||||
#include "esp32s3/rom/rtc.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "esp_private/sleep_mac_bb.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#include "esp32c3/rom/cache.h"
|
||||
#include "esp32c3/rom/rtc.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "esp_private/sleep_mac_bb.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/cache.h"
|
||||
#include "esp32h4/rom/rtc.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/cache.h"
|
||||
#include "esp32c2/rom/rtc.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/cache.h"
|
||||
#include "esp32c6/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/rtc.h"
|
||||
#include "esp32h2/rom/cache.h"
|
||||
#include "esp32h2/rom/rtc.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#endif
|
||||
|
||||
@ -115,6 +109,9 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)// TODO: IDF-5348
|
||||
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)// TODO: IDF-6267
|
||||
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
|
||||
#endif
|
||||
|
||||
#define LIGHT_SLEEP_TIME_OVERHEAD_US DEFAULT_HARDWARE_OUT_OVERHEAD_US
|
||||
@ -495,7 +492,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
|
||||
uint32_t result;
|
||||
if (deep_sleep) {
|
||||
// TODO: IDF-6051, IDF-6052
|
||||
#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6
|
||||
#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
|
||||
esp_sleep_isolate_digital_gpio();
|
||||
#endif
|
||||
|
||||
@ -778,7 +775,7 @@ esp_err_t esp_light_sleep_start(void)
|
||||
rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
|
||||
|
||||
// Safety net: enable WDT in case exit from light sleep fails
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5653
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
|
||||
#else
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
@ -986,7 +983,7 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
|
||||
|
||||
bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
|
||||
{
|
||||
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
||||
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-6027 C6 IO0-7 meet both conditions here
|
||||
return RTC_GPIO_IS_VALID_GPIO(gpio_num);
|
||||
#else
|
||||
return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);
|
||||
@ -1236,7 +1233,7 @@ esp_err_t esp_sleep_disable_bt_wakeup(void)
|
||||
|
||||
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
|
||||
return ESP_SLEEP_WAKEUP_UNDEFINED;
|
||||
#else
|
||||
if (esp_rom_get_reset_reason(0) != RESET_REASON_CORE_DEEP_SLEEP && !s_light_sleep_wakeup) {
|
||||
|
||||
@ -1,3 +1,7 @@
|
||||
if(IDF_TARGET STREQUAL "esp32h2")
|
||||
return() #ESP32H2-TODO: IDF-6213
|
||||
endif()
|
||||
|
||||
set(srcs "src/esp_lcd_common.c"
|
||||
"src/esp_lcd_panel_io.c"
|
||||
"src/esp_lcd_panel_io_i2c.c"
|
||||
|
||||
30
components/esp_pm/include/esp32h2/pm.h
Normal file
30
components/esp_pm/include/esp32h2/pm.h
Normal file
@ -0,0 +1,30 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Power management config for ESP32H2
|
||||
*
|
||||
* Pass a pointer to this structure as an argument to esp_pm_configure function.
|
||||
*/
|
||||
typedef struct {
|
||||
int max_freq_mhz; /*!< Maximum CPU frequency, in MHz */
|
||||
int min_freq_mhz; /*!< Minimum CPU frequency to use when no locks are taken, in MHz */
|
||||
bool light_sleep_enable; /*!< Enter light sleep when no locks are taken */
|
||||
} esp_pm_config_esp32h2_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -60,6 +60,9 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/pm.h"
|
||||
#include "driver/gpio.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/pm.h"
|
||||
#include "driver/gpio.h"
|
||||
#endif
|
||||
|
||||
#define MHZ (1000000)
|
||||
@ -98,6 +101,8 @@
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_PROFILING
|
||||
@ -236,6 +241,8 @@ esp_err_t esp_pm_configure(const void* vconfig)
|
||||
const esp_pm_config_esp32c2_t* config = (const esp_pm_config_esp32c2_t*) vconfig;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
const esp_pm_config_esp32c6_t* config = (const esp_pm_config_esp32c6_t*) vconfig;
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
const esp_pm_config_esp32h2_t* config = (const esp_pm_config_esp32h2_t*) vconfig;
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
@ -348,6 +355,8 @@ esp_err_t esp_pm_get_configuration(void* vconfig)
|
||||
esp_pm_config_esp32c2_t* config = (esp_pm_config_esp32c2_t*) vconfig;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
esp_pm_config_esp32c6_t* config = (esp_pm_config_esp32c6_t*) vconfig;
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
esp_pm_config_esp32h2_t* config = (esp_pm_config_esp32h2_t*) vconfig;
|
||||
#endif
|
||||
|
||||
portENTER_CRITICAL(&s_switch_lock);
|
||||
@ -794,6 +803,8 @@ void esp_pm_impl_init(void)
|
||||
esp_pm_config_esp32c2_t cfg = {
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
esp_pm_config_esp32c6_t cfg = {
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
esp_pm_config_esp32h2_t cfg = {
|
||||
#endif
|
||||
.max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
|
||||
.min_freq_mhz = xtal_freq_mhz,
|
||||
|
||||
@ -27,10 +27,6 @@ config ESP_ROM_GET_CLK_FREQ
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_RVFPLIB
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_HAL_WDT
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -12,7 +12,6 @@
|
||||
#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM.
|
||||
#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking
|
||||
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
|
||||
#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib
|
||||
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
|
||||
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
|
||||
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
|
||||
|
||||
@ -62,3 +62,20 @@ multi_heap_minimum_free_size_impl = 0x40000494;
|
||||
multi_heap_get_info_impl = 0x40000498;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
heap_tlsf_table_ptr = 0x4084ffd8;
|
||||
|
||||
PROVIDE (multi_heap_malloc = multi_heap_malloc_impl);
|
||||
PROVIDE (multi_heap_free = multi_heap_free_impl);
|
||||
PROVIDE (multi_heap_realloc = multi_heap_realloc_impl);
|
||||
PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl);
|
||||
PROVIDE (multi_heap_register = multi_heap_register_impl);
|
||||
PROVIDE (multi_heap_get_info = multi_heap_get_info_impl);
|
||||
PROVIDE (multi_heap_free_size = multi_heap_free_size_impl);
|
||||
PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl);
|
||||
PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl);
|
||||
PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
|
||||
PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
|
||||
PROVIDE (multi_heap_check = multi_heap_check);
|
||||
PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
|
||||
PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init);
|
||||
PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
|
||||
PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);
|
||||
|
||||
@ -32,10 +32,6 @@ endif()
|
||||
if(NOT BOOTLOADER_BUILD)
|
||||
list(APPEND srcs
|
||||
"rtc_io_hal.c"
|
||||
"spi_hal.c"
|
||||
"spi_hal_iram.c"
|
||||
"spi_slave_hal.c"
|
||||
"spi_slave_hal_iram.c"
|
||||
"timer_hal.c"
|
||||
"timer_hal_iram.c"
|
||||
"gpio_hal.c"
|
||||
@ -115,6 +111,19 @@ if(NOT BOOTLOADER_BUILD)
|
||||
list(APPEND srcs "${target}/modem_clock_hal.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_GPSPI_SUPPORTED)
|
||||
list(APPEND srcs
|
||||
"spi_hal.c"
|
||||
"spi_hal_iram.c"
|
||||
"spi_slave_hal.c"
|
||||
"spi_slave_hal_iram.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2)
|
||||
list(APPEND srcs "spi_slave_hd_hal.c")
|
||||
endif()
|
||||
|
||||
|
||||
if(${target} STREQUAL "esp32")
|
||||
list(APPEND srcs
|
||||
"sdio_slave_hal.c"
|
||||
@ -128,7 +137,6 @@ if(NOT BOOTLOADER_BUILD)
|
||||
if(${target} STREQUAL "esp32s2")
|
||||
list(APPEND srcs
|
||||
"spi_flash_hal_gpspi.c"
|
||||
"spi_slave_hd_hal.c"
|
||||
"touch_sensor_hal.c"
|
||||
"usb_hal.c"
|
||||
"usb_phy_hal.c"
|
||||
@ -144,7 +152,6 @@ if(NOT BOOTLOADER_BUILD)
|
||||
list(APPEND srcs
|
||||
"ds_hal.c"
|
||||
"spi_flash_hal_gpspi.c"
|
||||
"spi_slave_hd_hal.c"
|
||||
"touch_sensor_hal.c"
|
||||
"usb_hal.c"
|
||||
"usb_phy_hal.c"
|
||||
@ -161,7 +168,6 @@ if(NOT BOOTLOADER_BUILD)
|
||||
list(APPEND srcs
|
||||
"ds_hal.c"
|
||||
"spi_flash_hal_gpspi.c"
|
||||
"spi_slave_hd_hal.c"
|
||||
"xt_wdt_hal.c"
|
||||
"aes_hal.c"
|
||||
"esp32c3/brownout_hal.c"
|
||||
@ -173,7 +179,6 @@ if(NOT BOOTLOADER_BUILD)
|
||||
list(APPEND srcs
|
||||
"ds_hal.c"
|
||||
"spi_flash_hal_gpspi.c"
|
||||
"spi_slave_hd_hal.c"
|
||||
"aes_hal.c"
|
||||
"esp32h4/brownout_hal.c"
|
||||
"hmac_hal.c"
|
||||
@ -183,7 +188,6 @@ if(NOT BOOTLOADER_BUILD)
|
||||
if(${target} STREQUAL "esp32c2")
|
||||
list(APPEND srcs
|
||||
"spi_flash_hal_gpspi.c"
|
||||
"spi_slave_hd_hal.c"
|
||||
"esp32c2/brownout_hal.c"
|
||||
"esp32c2/rtc_cntl_hal.c")
|
||||
endif()
|
||||
@ -191,7 +195,6 @@ if(NOT BOOTLOADER_BUILD)
|
||||
if(${target} STREQUAL "esp32c6")
|
||||
list(APPEND srcs
|
||||
"spi_flash_hal_gpspi.c"
|
||||
"spi_slave_hd_hal.c"
|
||||
"esp32c6/brownout_hal.c"
|
||||
"esp32c6/rtc_cntl_hal.c")
|
||||
|
||||
@ -202,15 +205,9 @@ if(NOT BOOTLOADER_BUILD)
|
||||
"spi_flash_hal_gpspi.c"
|
||||
)
|
||||
|
||||
# TODO: IDF-5310
|
||||
list(REMOVE_ITEM srcs
|
||||
"adc_oneshot_hal.c"
|
||||
"adc_hal_common.c"
|
||||
"spi_slave_hd_hal.c"
|
||||
"spi_hal.c"
|
||||
"spi_hal_iram.c"
|
||||
"spi_slave_hal.c"
|
||||
"spi_slave_hal_iram.c"
|
||||
"adc_oneshot_hal.c" # TODO: IDF-6214
|
||||
"adc_hal_common.c" # TODO: IDF-6215
|
||||
"esp32h2/brownout_hal.c"
|
||||
"esp32h2/rtc_cntl_hal.c"
|
||||
"timer_hal.c"
|
||||
|
||||
@ -8,6 +8,8 @@
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/systimer_struct.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/pcr_struct.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time
|
||||
@ -29,6 +31,24 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systi
|
||||
dev->conf.clk_en = en;
|
||||
}
|
||||
|
||||
// Set clock source: XTAL(default) or RC_FAST
|
||||
static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src)
|
||||
{
|
||||
PCR.systimer_func_clk_conf.systimer_func_clk_sel = (clk_src == SYSTIMER_CLK_SRC_RC_FAST) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void)
|
||||
{
|
||||
return (PCR.systimer_func_clk_conf.systimer_func_clk_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL;
|
||||
}
|
||||
|
||||
/********************** ETM *****************************/
|
||||
|
||||
__attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en)
|
||||
{
|
||||
dev->conf.etm_en = en;
|
||||
}
|
||||
|
||||
/******************* Counter *************************/
|
||||
|
||||
__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
|
||||
|
||||
@ -4,8 +4,9 @@ entries:
|
||||
mmu_hal (noflash)
|
||||
if IDF_TARGET_ESP32 = n:
|
||||
cache_hal (noflash)
|
||||
spi_hal_iram (noflash)
|
||||
spi_slave_hal_iram (noflash)
|
||||
if SOC_GPSPI_SUPPORTED = y:
|
||||
spi_hal_iram (noflash)
|
||||
spi_slave_hal_iram (noflash)
|
||||
if UART_ISR_IN_IRAM = y || ESP_PANIC_HANDLER_IRAM = y:
|
||||
uart_hal_iram (noflash)
|
||||
else:
|
||||
|
||||
@ -3,3 +3,93 @@
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "esp_attr.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "heap_memory_layout.h"
|
||||
#include "esp_heap_caps.h"
|
||||
|
||||
/**
|
||||
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
|
||||
* Each type of memory map consists of one or more regions in the address space.
|
||||
* Each type contains an array of prioritized capabilities.
|
||||
* Types with later entries are only taken if earlier ones can't fulfill the memory request.
|
||||
*
|
||||
* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
|
||||
* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
/* Index of memory in `soc_memory_types[]` */
|
||||
enum {
|
||||
SOC_MEMORY_TYPE_DRAM = 0,
|
||||
SOC_MEMORY_TYPE_STACK_DRAM = 1,
|
||||
SOC_MEMORY_TYPE_DIRAM = 2,
|
||||
SOC_MEMORY_TYPE_RTCRAM = 3,
|
||||
SOC_MEMORY_TYPE_NUM,
|
||||
};
|
||||
|
||||
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
|
||||
// Type 0: DRAM
|
||||
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM
|
||||
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
|
||||
#else
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
|
||||
#endif
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
|
||||
/**
|
||||
* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
|
||||
*
|
||||
* @note Because of requirements in the coalescing code which merges adjacent regions,
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* Register the shared buffer area of the last memory block into the heap during heap initialization
|
||||
*/
|
||||
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
|
||||
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x40800000, 0x30000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //Block 4, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x40830000, 0x20000, SOC_MEMORY_TYPE_STACK_DRAM, 0x40830000}, //Block 9, can be used as trace memory
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
|
||||
#endif
|
||||
};
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
|
||||
|
||||
|
||||
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
|
||||
|
||||
/**
|
||||
* Reserved memory regions.
|
||||
* These are removed from the soc_memory_regions array when heaps are created.
|
||||
*
|
||||
*/
|
||||
|
||||
// Static data region. DRAM used by data+bss and possibly rodata
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
|
||||
|
||||
// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
// TODO: IDF-6019 check reserved lp mem region
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
|
||||
#endif
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
#include "esp32c2/rom/rom_layout.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/rom_layout.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/rom_layout.h"
|
||||
#endif
|
||||
#endif // ESP_ROM_HAS_LAYOUT_TABLE
|
||||
|
||||
|
||||
28
components/idf_test/include/esp32h2/idf_performance_target.h
Normal file
28
components/idf_test/include/esp32h2/idf_performance_target.h
Normal file
@ -0,0 +1,28 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 43
|
||||
|
||||
// SHA256 hardware throughput at 160 MHz, threshold set lower than worst case
|
||||
#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90
|
||||
// esp_sha() time to process 32KB of input data from RAM
|
||||
#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 560
|
||||
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 210000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 45000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 670000
|
||||
|
||||
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
|
||||
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
|
||||
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
|
||||
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
|
||||
|
||||
// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
|
||||
#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70
|
||||
#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140
|
||||
@ -35,6 +35,8 @@
|
||||
#include "esp32c2/rom/libc_stubs.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/libc_stubs.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/libc_stubs.h"
|
||||
#endif
|
||||
|
||||
static struct _reent s_reent;
|
||||
@ -112,7 +114,7 @@ static struct syscall_stub_table s_stub_table = {
|
||||
._scanf_float = NULL,
|
||||
#endif
|
||||
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 \
|
||||
|| CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
|
||||
|| CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
/* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM
|
||||
assertion failures (as function names & source file names will be similar)
|
||||
*/
|
||||
@ -136,7 +138,7 @@ void esp_newlib_init(void)
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
syscall_table_ptr_pro = &s_stub_table;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 \
|
||||
|| CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
|
||||
|| CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
syscall_table_ptr = &s_stub_table;
|
||||
#endif
|
||||
|
||||
|
||||
@ -42,6 +42,9 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/rtc.h"
|
||||
#include "esp32c6/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/rtc.h"
|
||||
#include "esp32h2/rtc.h"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
@ -91,6 +91,10 @@ config SOC_SDM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPSPI_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -82,6 +82,7 @@
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
#define SOC_RMT_SUPPORTED 1
|
||||
#define SOC_SDM_SUPPORTED 1
|
||||
#define SOC_GPSPI_SUPPORTED 1
|
||||
#define SOC_LEDC_SUPPORTED 1
|
||||
#define SOC_I2C_SUPPORTED 1
|
||||
#define SOC_SUPPORT_COEXISTENCE 1
|
||||
|
||||
@ -51,6 +51,10 @@ config SOC_I2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPSPI_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SHA_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -37,6 +37,7 @@
|
||||
#define SOC_TEMP_SENSOR_SUPPORTED 1
|
||||
#define SOC_LEDC_SUPPORTED 1
|
||||
#define SOC_I2C_SUPPORTED 1
|
||||
#define SOC_GPSPI_SUPPORTED 1
|
||||
#define SOC_SHA_SUPPORTED 1
|
||||
#define SOC_ECC_SUPPORTED 1
|
||||
#define SOC_FLASH_ENC_SUPPORTED 1
|
||||
|
||||
@ -75,6 +75,10 @@ config SOC_SDM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPSPI_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -43,6 +43,7 @@
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
#define SOC_RMT_SUPPORTED 1
|
||||
#define SOC_SDM_SUPPORTED 1
|
||||
#define SOC_GPSPI_SUPPORTED 1
|
||||
#define SOC_LEDC_SUPPORTED 1
|
||||
#define SOC_I2C_SUPPORTED 1
|
||||
#define SOC_SYSTIMER_SUPPORTED 1
|
||||
|
||||
@ -79,6 +79,10 @@ config SOC_SDM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPSPI_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -46,6 +46,7 @@
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
#define SOC_RMT_SUPPORTED 1
|
||||
#define SOC_SDM_SUPPORTED 1
|
||||
#define SOC_GPSPI_SUPPORTED 1
|
||||
#define SOC_LEDC_SUPPORTED 1
|
||||
#define SOC_I2C_SUPPORTED 1
|
||||
#define SOC_SYSTIMER_SUPPORTED 1
|
||||
|
||||
@ -3,10 +3,6 @@
|
||||
# using gen_soc_caps_kconfig.py, do not edit manually
|
||||
#####################################################
|
||||
|
||||
config SOC_IEEE802154_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_IEEE802154_BLE_ONLY
|
||||
bool
|
||||
default y
|
||||
@ -69,7 +65,7 @@ config SOC_ADC_MONITOR_SUPPORTED
|
||||
|
||||
config SOC_ADC_PERIPH_NUM
|
||||
int
|
||||
default 2
|
||||
default 1
|
||||
|
||||
config SOC_ADC_MAX_CHANNEL_NUM
|
||||
int
|
||||
@ -539,10 +535,6 @@ config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MEMSPI_IS_INDEPENDENT
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -377,7 +377,7 @@ typedef union {
|
||||
/** continue : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to continue GCM operation.
|
||||
*/
|
||||
uint32_t continue:1;
|
||||
uint32_t conti:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -478,7 +478,7 @@ typedef struct {
|
||||
volatile aes_inc_sel_reg_t inc_sel;
|
||||
volatile aes_aad_block_num_reg_t aad_block_num;
|
||||
volatile aes_remainder_bit_num_reg_t remainder_bit_num;
|
||||
volatile aes_continue_reg_t continue;
|
||||
volatile aes_continue_reg_t conti;
|
||||
volatile aes_int_clear_reg_t int_clear;
|
||||
volatile aes_int_ena_reg_t int_ena;
|
||||
volatile aes_date_reg_t date;
|
||||
|
||||
@ -744,12 +744,12 @@ typedef struct {
|
||||
volatile apb_tsens_sample_reg_t tsens_sample;
|
||||
uint32_t reserved_06c[228];
|
||||
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
|
||||
} apb_dev_t;
|
||||
} apb_saradc_dev_t;
|
||||
|
||||
extern apb_saradc_dev_t APB_SARADC;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
|
||||
_Static_assert(sizeof(apb_saradc_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
#define _CACHE_MEMORY_H_
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
||||
@ -989,7 +989,7 @@ typedef union {
|
||||
} intmtx_core0_interrupt_reg_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
typedef struct interrupt_matrix_dev_t {
|
||||
volatile intmtx_core0_pmu_intr_map_reg_t pmu_intr_map;
|
||||
volatile intmtx_core0_efuse_intr_map_reg_t efuse_intr_map;
|
||||
volatile intmtx_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
|
||||
@ -1061,12 +1061,12 @@ typedef struct {
|
||||
volatile intmtx_core0_clock_gate_reg_t clock_gate;
|
||||
uint32_t reserved_114[442];
|
||||
volatile intmtx_core0_interrupt_reg_date_reg_t interrupt_reg_date;
|
||||
} intmtx_core0_dev_t;
|
||||
} interrupt_matrix_dev_t;
|
||||
|
||||
extern interrupt_matrix_dev_t INTMTX;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(intmtx_core0_dev_t) == 0x800, "Invalid size of intmtx_core0_dev_t structure");
|
||||
_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -64,4 +64,3 @@
|
||||
#define PMU_ICG_FUNC_ENA_UHCI 5
|
||||
#define PMU_ICG_FUNC_ENA_HPCORE 17
|
||||
#define PMU_ICG_FUNC_ENA_HPBUS 15
|
||||
#endif /* _SOC_ICG_MAP_H_ */
|
||||
|
||||
@ -89,7 +89,7 @@ typedef union {
|
||||
/** continue : RO; bitpos: [31:1]; default: 0;
|
||||
* Reserved.
|
||||
*/
|
||||
uint32_t continue:31;
|
||||
uint32_t conti:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_continue_reg_t;
|
||||
@ -193,7 +193,7 @@ typedef struct {
|
||||
volatile sha_t_length_reg_t t_length;
|
||||
volatile sha_dma_block_num_reg_t dma_block_num;
|
||||
volatile sha_start_reg_t start;
|
||||
volatile sha_continue_reg_t continue;
|
||||
volatile sha_continue_reg_t conti;
|
||||
volatile sha_busy_reg_t busy;
|
||||
volatile sha_dma_start_reg_t dma_start;
|
||||
volatile sha_dma_continue_reg_t dma_continue;
|
||||
|
||||
@ -163,10 +163,10 @@
|
||||
#define SOC_IROM_LOW 0x42000000
|
||||
#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<7))
|
||||
#define SOC_DROM_LOW SOC_IROM_HIGH
|
||||
#define SOC_DROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
|
||||
#define SOC_DROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8)) // ESP32H2 MMU-TODO: IDF-6251
|
||||
#define SOC_IROM_MASK_LOW 0x40000000
|
||||
#define SOC_IROM_MASK_HIGH 0x4004A000
|
||||
#define SOC_DROM_MASK_LOW 0x4004A000
|
||||
#define SOC_IROM_MASK_HIGH 0x4001C400
|
||||
#define SOC_DROM_MASK_LOW 0x4001C400
|
||||
#define SOC_DROM_MASK_HIGH 0x40020000
|
||||
#define SOC_IRAM_LOW 0x40800000
|
||||
#define SOC_IRAM_HIGH 0x40850000
|
||||
@ -212,7 +212,7 @@
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x4087c770
|
||||
|
||||
#define SOC_ROM_STACK_SIZE 0x2000
|
||||
|
||||
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
|
||||
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
// #define SOC_MCPWM_SUPPORTED 1 // TODO: IDF-6237
|
||||
// #define SOC_TWAI_SUPPORTED 1 // TODO: IDF-6217
|
||||
// #define SOC_BT_SUPPORTED 1 // TODO: IDF-6416
|
||||
#define SOC_IEEE802154_SUPPORTED 1
|
||||
// #define SOC_IEEE802154_SUPPORTED 1 // TODO: IDF-6577
|
||||
#define SOC_IEEE802154_BLE_ONLY 1
|
||||
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: IDF-6238
|
||||
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: IDF-6239
|
||||
@ -46,6 +46,7 @@
|
||||
// #define SOC_I2S_SUPPORTED 1 // TODO: IDF-6219
|
||||
// #define SOC_RMT_SUPPORTED 1 // TODO: IDF-6224
|
||||
// #define SOC_SDM_SUPPORTED 1 // TODO: IDF-6220
|
||||
// #define SOC_GPSPI_SUPPORTED 1 // TODO: IDF-6264
|
||||
#define SOC_SYSTIMER_SUPPORTED 1
|
||||
// #define SOC_SUPPORT_COEXISTENCE 1 // TODO: IDF-6416
|
||||
// #define SOC_AES_SUPPORTED 1 // TODO: IDF-6280
|
||||
@ -76,7 +77,7 @@
|
||||
#define SOC_ADC_ARBITER_SUPPORTED 1
|
||||
#define SOC_ADC_FILTER_SUPPORTED 1
|
||||
#define SOC_ADC_MONITOR_SUPPORTED 1
|
||||
#define SOC_ADC_PERIPH_NUM (2)
|
||||
#define SOC_ADC_PERIPH_NUM (1U)
|
||||
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
|
||||
#define SOC_ADC_MAX_CHANNEL_NUM (5)
|
||||
#define SOC_ADC_ATTEN_NUM (4)
|
||||
@ -307,7 +308,7 @@
|
||||
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
|
||||
#define SOC_SPI_SUPPORT_CD_SIG 1
|
||||
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
|
||||
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
|
||||
//#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 //TODO: IDF-6247
|
||||
|
||||
// Peripheral supports DIO, DOUT, QIO, or QOUT
|
||||
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
|
||||
|
||||
@ -99,6 +99,10 @@ config SOC_SDM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPSPI_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -63,6 +63,7 @@
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
#define SOC_RMT_SUPPORTED 1
|
||||
#define SOC_SDM_SUPPORTED 1
|
||||
#define SOC_GPSPI_SUPPORTED 1
|
||||
#define SOC_LEDC_SUPPORTED 1
|
||||
#define SOC_I2C_SUPPORTED 1
|
||||
#define SOC_SYSTIMER_SUPPORTED 1
|
||||
|
||||
@ -131,6 +131,10 @@ config SOC_SDM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPSPI_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -52,6 +52,7 @@
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
#define SOC_RMT_SUPPORTED 1
|
||||
#define SOC_SDM_SUPPORTED 1
|
||||
#define SOC_GPSPI_SUPPORTED 1
|
||||
#define SOC_LEDC_SUPPORTED 1
|
||||
#define SOC_I2C_SUPPORTED 1
|
||||
#define SOC_SYSTIMER_SUPPORTED 1
|
||||
|
||||
@ -40,6 +40,10 @@
|
||||
#include "esp32c6/rom/cache.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/cache.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#endif
|
||||
#include "esp_rom_spiflash.h"
|
||||
#include <soc/soc.h>
|
||||
@ -74,7 +78,7 @@ static void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
|
||||
|
||||
static uint32_t s_flash_op_cache_state[2];
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C6
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
/* esp32c6 does not has a register indicating if cache is enabled
|
||||
* so we use s static data to store to state of cache, every time
|
||||
* disable/restore api is called, the state will be updated
|
||||
@ -384,7 +388,7 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_st
|
||||
uint32_t icache_state;
|
||||
icache_state = Cache_Suspend_ICache() << 16;
|
||||
*saved_state = icache_state;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
uint32_t icache_state;
|
||||
icache_state = Cache_Suspend_ICache();
|
||||
*saved_state = icache_state;
|
||||
@ -413,7 +417,7 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta
|
||||
Cache_Resume_ICache(saved_state >> 16);
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2
|
||||
Cache_Resume_ICache(saved_state >> 16);
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
Cache_Resume_ICache(saved_state);
|
||||
s_cache_enabled = 1;
|
||||
#endif
|
||||
@ -430,7 +434,7 @@ IRAM_ATTR bool spi_flash_cache_enabled(void)
|
||||
bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2
|
||||
bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0);
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
bool result = s_cache_enabled;
|
||||
#endif
|
||||
return result;
|
||||
|
||||
@ -3,3 +3,6 @@
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
// TODO: IDF-6020
|
||||
|
||||
@ -112,7 +112,7 @@ esp_flash_t *esp_flash_default_chip = NULL;
|
||||
.input_delay_ns = 0,\
|
||||
.cs_setup = 1,\
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
#if !CONFIG_SPI_FLASH_AUTO_SUSPEND
|
||||
#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
|
||||
.host_id = SPI1_HOST,\
|
||||
@ -363,8 +363,8 @@ esp_err_t esp_flash_init_default_chip(void)
|
||||
const esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip;
|
||||
memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT();
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6
|
||||
// For esp32s2 spi IOs are configured as from IO MUX by default
|
||||
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
|
||||
// Only these chips have efuses for spi pin configuration.
|
||||
cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false;
|
||||
#endif
|
||||
|
||||
|
||||
@ -40,6 +40,8 @@
|
||||
#include "esp32c2/rom/cache.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/cache.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/cache.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_SPIRAM
|
||||
|
||||
@ -29,6 +29,9 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/ets_sys.h"
|
||||
#include "esp32c6/rom/cache.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/ets_sys.h"
|
||||
#include "esp32h2/rom/cache.h"
|
||||
#endif
|
||||
|
||||
#include "esp_attr.h"
|
||||
@ -40,7 +43,7 @@ typedef struct {
|
||||
} spi_noos_arg_t;
|
||||
|
||||
static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
typedef struct {
|
||||
uint32_t icache_autoload;
|
||||
} spi_noos_arg_t;
|
||||
@ -57,7 +60,7 @@ static IRAM_ATTR esp_err_t start(void *arg)
|
||||
spi_noos_arg_t *spi_arg = arg;
|
||||
spi_arg->icache_autoload = Cache_Suspend_ICache();
|
||||
spi_arg->dcache_autoload = Cache_Suspend_DCache();
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
spi_noos_arg_t *spi_arg = arg;
|
||||
spi_arg->icache_autoload = Cache_Suspend_ICache();
|
||||
#endif
|
||||
@ -74,7 +77,7 @@ static IRAM_ATTR esp_err_t end(void *arg)
|
||||
Cache_Invalidate_ICache_All();
|
||||
Cache_Resume_ICache(spi_arg->icache_autoload);
|
||||
Cache_Resume_DCache(spi_arg->dcache_autoload);
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
|
||||
spi_noos_arg_t *spi_arg = arg;
|
||||
Cache_Invalidate_ICache_All();
|
||||
Cache_Resume_ICache(spi_arg->icache_autoload);
|
||||
|
||||
@ -73,6 +73,8 @@
|
||||
#include "esp32h4/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/ets_sys.h"
|
||||
#endif
|
||||
|
||||
#endif /* !__ets__ */
|
||||
|
||||
16
examples/common_components/env_caps/esp32h2/Kconfig.env_caps
Normal file
16
examples/common_components/env_caps/esp32h2/Kconfig.env_caps
Normal file
@ -0,0 +1,16 @@
|
||||
config ENV_GPIO_RANGE_MIN
|
||||
int
|
||||
default 0
|
||||
|
||||
config ENV_GPIO_RANGE_MAX
|
||||
int
|
||||
default 27
|
||||
# GPIOs 23/24 are always used by UART in examples
|
||||
|
||||
config ENV_GPIO_IN_RANGE_MAX
|
||||
int
|
||||
default ENV_GPIO_RANGE_MAX
|
||||
|
||||
config ENV_GPIO_OUT_RANGE_MAX
|
||||
int
|
||||
default ENV_GPIO_RANGE_MAX
|
||||
Loading…
Reference in New Issue
Block a user