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feat(brc_predictor): p4 base support for branch predictor
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -550,6 +550,16 @@ FORCE_INLINE_ATTR intptr_t esp_cpu_get_call_addr(intptr_t return_address)
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*/
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bool esp_cpu_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, uint32_t new_value);
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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/**
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* @brief Enable branch prediction
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*/
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FORCE_INLINE_ATTR void esp_cpu_branch_prediction_enable(void)
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{
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rv_utils_en_branch_predictor();
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}
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#endif //#if SOC_BRANCH_PREDICTOR_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -152,6 +152,10 @@ void startup_resume_other_cores(void)
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void IRAM_ATTR call_start_cpu1(void)
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{
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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esp_cpu_branch_prediction_enable();
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#endif //#if SOC_BRANCH_PREDICTOR_SUPPORTED
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esp_cpu_intr_set_ivt_addr(&_vector_table);
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ets_set_appcpu_boot_addr(0);
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@ -317,6 +321,9 @@ void IRAM_ATTR call_start_cpu0(void)
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);
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#endif
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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esp_cpu_branch_prediction_enable();
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#endif
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// Move exception vectors to IRAM
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esp_cpu_intr_set_ivt_addr(&_vector_table);
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -229,6 +229,17 @@ FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_
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return (old_value == compare_value);
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}
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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FORCE_INLINE_ATTR void rv_utils_en_branch_predictor(void)
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{
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#define MHCR 0x7c1
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#define MHCR_RS (1<<4) /* R/W, address return stack set bit */
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#define MHCR_BFE (1<<5) /* R/W, allow predictive jump set bit */
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#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
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RV_SET_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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