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393 Commits

Author SHA1 Message Date
Ivan Grokhotkov
ea7d020f20 Merge branch 'feature/ubsan' into 'master' 
system: add option to enable undefined behavior sanitizer (UBSAN)

Closes IDF-166 and IDF-1824

See merge request espressif/esp-idf!11318
 2021-04-23 09:27:42 +00:00
Ivan Grokhotkov
da90775d98 hal: mpu: fix signed overflow error 2021-04-22 23:33:47 +02:00
Darian Leung
54eb152a96 TWAI: Simply caps and remove unused caps 2021-04-16 18:36:18 +08:00
Angus Gratton
268b23db96 bootloader: Fix selection of Quad I/O modes on ESP32-U4WDH chip 
Closes https://github.com/espressif/esp-idf/issues/6191
 2021-04-12 18:49:17 +10:00
morris
75dfd970b4 dac: added DAC support macro 
Remove DAC support on ESP32-S3
 2021-04-12 12:04:46 +08:00
Armando
9b9ea71ff9 spi: remove HSPI macro on esp32c3 and esp32s3 2021-04-06 13:42:49 +08:00
Michael (XIAO Xufeng)
3a90d51831 Merge branch 'refactor/using_isr_callback_in_timer_example' into 'master' 
TIMG: clean up timer example and add example test

Closes IDF-2722, IDF-2766, and IDF-2347

See merge request espressif/esp-idf!12218
 2021-03-22 06:36:32 +00:00
morris
f5ca47c0fc mcpwm: rename macros related to soc capbility 2021-03-16 21:53:59 +08:00
morris
5a520cacf1 timer_group: correct timer_ll_set_divider 2021-03-16 17:56:37 +08:00
Angus Gratton
fd164b82b6 Merge branch 'refactor/move_from_xtensa' into 'master' 
Movements from xtensa

Closes IDF-2164

See merge request espressif/esp-idf!10556
 2021-03-11 00:24:25 +00:00
Renz Bagaporo
1efdcd69d9 xtensa: move out trax 2021-02-26 19:45:48 +08:00
Xia Xiaotian
f53c0c5b87 esp_wifi: store PHY digital registers before disabling PHY and load 
them after enabling PHY
 2021-02-26 11:29:50 +08:00
morris
7b37158ede rmt: distinguish group and channel in HAL layer 2021-02-25 12:42:23 +08:00
morris
6dc7f95342 mcpwm: fix wrong meta information 2021-02-22 20:23:35 +08:00
Angus Gratton
2ec04b57de soc esp32: Removes parentheses from RTC_MEM_xyz macros that expand directly to single numbers 
Not necessary in these cases, and prevents parens from expanding into the
assembly code such as added in 562ab01046  -
a pattern which is accepted by GCC assembler but illegal syntax for LLVM assembler.

As reported https://github.com/espressif/llvm-project/issues/35#issuecomment-726853574
 2021-02-08 10:08:01 +11:00
Michael (XIAO Xufeng)
d7d1dee208 system: reset dma when soft reset 2021-01-25 04:51:40 +00:00
Angus Gratton
fe8a891de9 Merge branch 'feature/support_esp32c3_master_cmake_secure_boot' into 'master' 
bootloader/esp32c3: Support secure boot

Closes IDF-2115

See merge request espressif/esp-idf!11797
 2021-01-21 08:42:49 +08:00
KonstantinKondrashov
88c5fe49b8 soc: Adds a soc_caps define for all chips to define the number of boot key digests 2021-01-19 20:51:13 +08:00
Li Shuai
aa7fd175b9 light sleep: light sleep support for esp32c3 2021-01-19 14:50:58 +08:00
ninh
27aa6c289f components/pm: Add slp gpio configure workaround 2021-01-15 15:34:45 +08:00
morris
e6d23a35ec gdma: dynamic alloc DMA channels 2021-01-13 10:52:27 +08:00
ninh
dc7bdb9857 adjust lightsleep overhead time and cali slowclk 2021-01-06 03:40:28 +00:00
Marius Vikhammer
eb788deb03 esp_hw_support: merge C3 changes to master 
Merge RTC related C3 changes to master
 2020-12-30 12:20:41 +08:00
Angus Gratton
c3ba995f2c Merge branch 'ci/ccomp_performance_tests' into 'master' 
unit_test: Refactor all performance tests that rely on cache compensated timer

See merge request espressif/esp-idf!11709
 2020-12-24 13:44:52 +08:00
Angus Gratton
fa892eb017 soc: Explain units for rtc_clk_cal() function, fix typo 2020-12-23 09:53:24 +11:00
Cao Sen Miao
e338a2e3df rtc: add function to en/disable the rtc clock 2020-12-23 09:53:24 +11:00
Marius Vikhammer
0a95151a75 unit_test: Refactor all performance tests that rely on cache compensated timer 
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.

This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
 2020-12-22 18:56:24 +11:00
Cao Sen Miao
0736c91d68 soc: Remove cache constants from soc.h 2020-12-17 15:34:13 +11:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer 
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
 2020-12-10 09:04:47 +00:00
Angus Gratton
c29d93986d soc: Add initial ESP32-C3 support 
From internal commit 7761d6e8
 2020-11-30 11:12:56 +11:00
Armando
fb8b905539 uart: add uart support on esp32s3 2020-11-24 19:12:51 +08:00
morris
c5fe158929 doc: fix wrong register description regarding to ethernet SMI 2020-11-16 13:30:49 +08:00
Michael (XIAO Xufeng)
14944b181e Merge branch 'fix/soc_caps_spi_dummy_output_esp32' into 'master' 
soc_caps.h: remove spi cap that is defined to 0

See merge request espressif/esp-idf!11203
 2020-11-16 10:39:27 +08:00
Michael (XIAO Xufeng)
099fca515d Merge branch 'bugfix/move_crypto_caps' into 'master' 
SHA/RSA: moved all caps to soc_caps.h

Closes IDF-2300

See merge request espressif/esp-idf!11032
 2020-11-13 11:06:44 +08:00
Angus Gratton
935e4b4d62 Merge branch 'feature/riscv_arch' into 'master' 
Add RISC-V support

Closes IDF-2359

See merge request espressif/esp-idf!11140
 2020-11-13 07:50:31 +08:00
Angus Gratton
420aef1ffe Updates for riscv support 
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
 2020-11-13 07:49:11 +11:00
Cao Sen Miao
6eee601cf6 i2c: Add supports on esp32s3 2020-11-12 11:32:45 +08:00
Michael (XIAO Xufeng)
5b6c965e99 soc_caps.h: remove spi cap that is defined to 0 
According to the caps rule, for unsupported feature we don't define anything. 

Remove the define 0 that violates this rule.
 2020-11-12 10:29:42 +08:00
Marius Vikhammer
488f46acf5 SHA/RSA: moved all caps to soc_caps.h 2020-11-12 02:15:46 +00:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit) 
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
 2020-11-11 07:36:35 +00:00
morris
ff976867b3 rmt: split TX and RX in LL driver 
Split TX and RX function in LL driver.
Channel number is encoded in driver layer.
Added channel signal list in periph.c
 2020-11-05 19:00:55 +08:00
chenjianqiang
9465af0066 rmt: support esp32s3 2020-11-05 19:00:55 +08:00
morris
e4c8ec6174 timergroup: move interrupt index into peripheral description file 
1. Added timer_group_periph.c file, describing module global signals
   (e.g. interrupt index)
2. Added more caps in soc_caps.h
 2020-11-03 18:16:50 +08:00
Michael (XIAO Xufeng)
35faecea1d Merge branch 'feature/support_sigma_delta_on_s3' into 'master' 
sigma_delta: add periph signal list and support esp32-s3

See merge request espressif/esp-idf!10945
 2020-10-30 17:22:02 +08:00
Michael (XIAO Xufeng)
3bacf35310 esp_flash: support high capacity flash chips (32-bit address) 2020-10-29 18:20:11 +08:00
morris
17808b3ff8 sigma_delta: add periph signal list and support esp32-s3 2020-10-29 11:06:28 +08:00
Renz Bagaporo
79887fdc6c soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
Renz Christian Bagaporo
1f2e2fe8af soc: separate abstraction, description and implementation 2020-02-11 14:30:42 +05:00
Wangjialin
aaf119e930 flash(esp32s2): fix setting address field in spi user mode. 2020-02-07 16:10:51 +01:00
Ivan Grokhotkov
70752baba4 esp32s2: add brownout detector support 
1. add brownout detector HAL for esp32 and esp32s2
2. enable brownout reset for esp32 rev. 1 and above
3. add approximate brownout detector levels for esp32s2
 2020-01-23 13:44:19 +01:00
Angus Gratton
c7738f24fc Merge branch 'bugfix/ledc_driver_enums' into 'master' 
driver: Avoid possible accidental mismatch between ledc_clk_src_t & ledc_clk_cfg_t enum

See merge request espressif/esp-idf!7021
 2020-01-10 15:34:43 +08:00
Darian Leung
a049e02d96 can: Refactor CAN to use HAL and LowLevel layers 
The following commit refactors the CAN driver such that
it is split into HAL and Lowlevel layers. The following
changes have also been made:

- Added bit field members to can_message_t as alternative
  to message flags. Updated examples and docs accordingly
- Register field names and fields of can_dev_t updated
 2020-01-09 16:13:51 +08:00
michael
f676a3b190 driver, soc: update multichip support headers 2020-01-06 17:13:54 +08:00
Ivan Grokhotkov
52f8aa2adb Merge branch 'feature/heap_non_os_build' into 'master' 
heap: make compatible with non-OS builds, remove target dependence

Closes IDF-1236

See merge request espressif/esp-idf!7051
 2020-01-03 17:12:51 +08:00
Ivan Grokhotkov
d9534b3d6a soc: fix backtraces containing ROM functions 
esp_ptr_executable would return false for pointers to ROM, which would
interrupt the backtrace. This makes ROM ranges recognized as
executable.
 2020-01-02 18:42:46 +01:00
Ivan Grokhotkov
4bbfa6e494 Merge branch 'feature/soc_ledc_caps' into 'master' 
soc: add ledc_caps.h, replace target-based ifdefs with caps-based

See merge request espressif/esp-idf!6858
 2019-12-30 18:47:11 +08:00
Ivan Grokhotkov
e4d45608d3 soc: add ledc_caps.h, replace target-based ifdefs with caps-based 2019-12-28 20:33:21 +00:00
Ivan Grokhotkov
3285ed116d heap: make compatible with non-OS builds, remove target dependence 2019-12-27 12:40:06 +01:00
morris
7baf7ce273 ethernet: optimise tx and rx 2019-12-24 11:18:31 +08:00
michael
11fa11000f spi: re-enable the unit tests for esp32s2beta 2019-12-23 10:22:59 +08:00
Mahavir Jain
e8db1c4da0 Merge branch 'feature/enable_i2s_tests_on_esp32s2beta' into 'master' 
Enable i2s and freertos test/s on esp32s2beta

See merge request espressif/esp-idf!6790
 2019-12-18 17:51:54 +08:00
kewal shah
eec8212237 add simplified API to set UART threshold values for RX FIFO full and TX FIFO empty 2019-12-16 20:26:04 +00:00
Angus Gratton
435dd546cc driver: Avoid possible accidental mismatch between ledc_clk_src_t & ledc_clk_cfg_t enum 
ledc_types.h includes two similar enums, ledc_clk_src_t & ledc_clk_cfg_t. Latter was added in
ESP-IDF v4.0.

The two enums do different things but there are two similar names: LEDC_REF_TICK / LEDC_USE_REF_TICK
and LEDC_APB_CLK / LEDC_USE_APB_CLK.

Because C will accept any enum or integer value for an enum argument, there's no easy way to check
the correct enum is passed without using static analysis.

To avoid accidental errors, make the numeric values for the two similarly named enums the same.,

Noticed when looking into https://github.com/espressif/esp-idf/issues/4476
 2019-12-16 19:43:11 +11:00
Mahavir Jain
8b05cf41ad i2s: enable tests for esp32s2beta 2019-12-16 11:53:33 +05:30
Wang Jia Lin
f5e60524ac Merge branch 'bugfix/fix_i2c_driver_breakingchange_issue' into 'master' 
bugfix(i2c): fix I2C driver breaking change issue

See merge request espressif/esp-idf!6809
 2019-12-06 16:50:16 +08:00
houwenxiang
aac935ec81 bugfix(i2c): fix I2C driver breaking change issue. 
1. Fixed I2C driver breaking change issue.
    2. Add I2C UT test case.
 2019-12-04 15:51:36 +08:00
houwenxiang
e4230d11ca bugfix(UART): fix uart driver spinlock misused bug 
1. fix uart driver spinlock misused bug
    2. add uart driver ut test case
    3. undo the change in light_sleep_example_main.c
 2019-12-03 16:06:31 +08:00
Wang Jia Lin
1ffcb54444 Merge branch 'bugfix/fix_esp32-s2_rtc_io_issue' into 'master' 
bugfix(gpio): fix esp32 s2 rtc io issue and gpio testcase issues

See merge request espressif/esp-idf!6832
 2019-12-03 11:17:41 +08:00
Renz Christian Bagaporo
e6ad330018 ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation 
Otherwise IRAM usage is too high in this example.
 2019-11-28 09:20:00 +08:00
Fu Zhi Bo
3a468a1ffd Refactor the touch sensor driver 2019-11-27 20:08:44 +08:00
xiongyu
af4c455417 bugfix(gpio):fix esp32 s2 rtc io issue 
* Modify the function implementation of ESP32-S2 RTC GPIO
  On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
  On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
* Add ESP32-S2 support of unit test
* Modify the pull-up test of unit test
* Modify the interrupt test of unit test
* Modify input and output mode test of unit test
 2019-11-27 17:18:20 +08:00
Angus Gratton
91b7a7beaf Merge branch 'bugfix/timer_intr_status_get' into 'master' 
bugfix(timer): fix get intr status function

See merge request espressif/esp-idf!6807
 2019-11-27 09:13:16 +08:00
Angus Gratton
64c8b640a1 Merge branch 'feature/log_component_noos' into 'master' 
log: make compatible with non-OS builds

See merge request espressif/esp-idf!6787
 2019-11-27 08:34:22 +08:00
chenjianqiang
bcfe684951 bugfix(timer): add a macro to control making the XTAL related functions 2019-11-26 12:39:46 +00:00
chenjianqiang
856d9f7d89 bugfix(timer): recover get raw interrupt status function 2019-11-26 12:39:46 +00:00
houwenxiang
f27ae9b0e2 feature: Add uart hal support. 2019-11-26 20:01:50 +08:00
Angus Gratton
f2a1a6105a Merge branch 'feat/mcpwm_hal' 
Manual merge of !6626
 2019-11-25 17:18:48 +11:00
Angus Gratton
6dd36fd571 Merge branch 'refactor/hal_gpio_driver' 
Manual merge of !5597
 2019-11-25 10:49:40 +11:00
Angus Gratton
f34edba8f3 Merge branch 'feature/adc_driver_hal_support' 
Manual merge of !6044
 2019-11-25 10:22:06 +11:00
michael
538540ce21 mcpwm: add HAL layer support 
Also improved the unit tests a bit.
 2019-11-25 00:36:30 +08:00
xiongyu
a3b79e9202 refactor(gpio): add hal gpio driver 2019-11-22 17:24:53 +08:00
fuzhibo
f49b192a5e refactor the adc driver 2019-11-22 15:42:16 +08:00
Mahavir Jain
25c0752682 i2s: fix regression in retrieval of chip revision causing apll test to fail 2019-11-22 11:46:38 +05:30
fuzhibo
03ac1aaafd dac: refactor driver add hal 2019-11-22 11:44:46 +08:00
Ivan Grokhotkov
951ed739f7 soc/cpu: add non-xtensa-specific replacement of xthal_get_ccount 2019-11-21 19:22:35 +01:00
houwenxiang
28286183d1 feature(I2C): Add i2c hal support. 2019-11-21 20:34:07 +08:00
chenjianqiang
857dec108d feat(ledc): refactor ledc driver 
1. add hal and low-level layer for ledc driver
2. support esp32s2beta ledc
 2019-11-21 16:25:22 +08:00
chenjianqiang
9f9da9ec96 feat(timer): refator timer group driver 
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
 2019-11-21 14:14:19 +08:00
xiongyu
e62b831867 refactor(sigmadelta): add hal sigmadelta driver 2019-11-21 11:53:07 +08:00
fuzhibo
0c2bf7c8bc rtcio: add hal for driver 2019-11-21 10:40:49 +08:00
Angus Gratton
b30b0e59fa Merge branch 'feature/add_rmt_hal' into 'master' 
rmt: add hal layer and new examples

Closes IDF-841, IDF-844, and IDF-857

See merge request espressif/esp-idf!5649
 2019-11-21 09:53:54 +08:00
morris
8fd8695ea1 rmt: add HAL layer 2019-11-20 10:54:21 +08:00
xiongyu
8c76a3c10d refactor(i2s): add hal i2s driver 2019-11-19 22:19:19 +08:00
xiongyu
b1a72866ca refactor(pcnt): add hal pcnt driver 2019-11-18 14:35:46 +08:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Ivan Grokhotkov
c7d8ef52ca Merge branch 'fix/esp_flash_no_qe' into 'master' 
esp_flash: fix the QE write issue in high freq, and support UT for external chips

Closes IDF-888

See merge request espressif/esp-idf!5736
 2019-10-20 13:59:30 +08:00
Angus Gratton
ae21d669b9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-17 18:22:08 +11:00
Darian
820fd6447d can: Add support for lower bit rates 
This commit adds support for lower bit rates in the CAN Driver for
ESP32 Rev 2 or later chips.
 2019-10-17 12:33:17 +08:00
Angus Gratton
496ede9bcd Merge branch 'master' into feature/esp32s2beta_merge 2019-10-15 14:59:27 +11:00
Michael (XIAO Xufeng)
571864e8ae esp_flash: fix set qe bit and write command issues 
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
 2019-10-14 17:25:58 +08:00
suda-morris
13c128fd31 Ethernet: optimize and bugfix 
1. simplify deallocate in esp_eth_mac_new_esp32, esp_eth_mac_new_dm9051
2. remove blocking operation in os timer callback
3. check buffer size in ethernet receive function
 2019-10-11 12:15:17 +08:00
Angus Gratton
adfc06a530 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-20 10:28:37 +10:00
Jack
95ec36afd4 dport: remove clock_en and reset bitname which is not suitable 2019-09-13 09:44:07 +10:00
Angus Gratton
33a186f630 soc: Remove deprecated LEDC struct register names (bit_num, div_num) 
Deprecated since ESP-IDF V3.0
 2019-09-13 09:44:07 +10:00
Angus Gratton
6195c69701 soc: remove deprecated io_mux PIN_PULLxxx_yyy macros 
Deprecated before ESP-IDF V1.0!
 2019-09-13 09:44:07 +10:00
Angus Gratton
11c1da5276 soc/pm: Remove deprecated use of rtc_cpu_freq_t enum 
Removes deprecated ways of setting/getting CPU freq, light sleep freqs.

Deprecated since ESP-IDF V3.2
 2019-09-13 09:44:07 +10:00
Angus Gratton
35147119f1 Merge branch 'feature/support_ut_esp32s2beta' into 'feature/esp32s2beta' 
ci: support build and run UT for esp32s2beta

See merge request espressif/esp-idf!5702
 2019-09-09 08:34:16 +08:00
Li Shuai
bd29202520 1. Fix backtrace is incomplete 
2. Optimization code style
 2019-09-05 18:40:33 +08:00
Michael (XIAO Xufeng)
43135dc348 spi: convenient LL macro 2019-09-04 10:53:25 +10:00
Michael (XIAO Xufeng)
05739798c3 soc: s2beta support 2019-09-04 10:53:25 +10:00
Angus Gratton
6990a7cd54 Merge branch 'master' into feature/esp32s2beta_update 2019-08-19 15:03:43 +10:00
Angus Gratton
367ecc2d60 Merge branch 'refactor/timerg_in_test' into 'master' 
timer_group: refactoring to avoid direct register access in the ISR

See merge request espressif/esp-idf!5656
 2019-08-14 15:32:16 +08:00
suda-morris
f86e82cb63 efuse: update the scheme of getting chip revision 2019-08-13 10:59:02 +08:00
Michael (XIAO Xufeng)
feea477023 timer_group: add LL functions for WDT 2019-08-09 13:46:30 +08:00
Michael (XIAO Xufeng)
c02981a99b timer_group: support interrupt LL and some utility functions in ISR 2019-08-09 13:46:30 +08:00
chenjianqiang
a97fe5615f feat(timer): refator timer group driver (partly pick) 2019-08-09 13:46:29 +08:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
kooho
2139ca668d Update I2S driver for esp32s2beta. 2019-08-05 16:05:16 +08:00
Anton Maklakov
afbaf74007 tools: Mass fixing of empty prototypes (for -Wstrict-prototypes) 2019-08-01 16:28:56 +07:00
chenjianqiang
91ae40e2ff uart: multichip support 2019-07-18 15:57:00 +08:00
chenjianqiang
4cc962353c feat(uart): update uart driver for esp32s2beta 2019-07-18 15:57:00 +08:00
boarchuz
b0168310db Typo correction 
Merges https://github.com/espressif/esp-idf/pull/3604
 2019-07-02 17:49:49 +08:00
Ivan Grokhotkov
d7d91225d3 Merge branch 'feature/refactor_etherent_driver' into 'master' 
add esp_eth component

Closes IDF-324, IDF-637, and IDFGH-1139

See merge request idf/esp-idf!5111
 2019-06-28 03:44:44 +08:00
Michael (XIAO Xufeng)
d6bd24ca67 esp_flash: add initialization interface for SPI devices 2019-06-27 13:27:27 +08:00
suda-morris
90c4827bd2 add esp_eth component 2019-06-26 10:19:23 +08:00
Michael (XIAO Xufeng)
17378fd4c2 spi: support new chip esp32s2beta 2019-06-23 12:17:27 +08:00
Michael (XIAO Xufeng)
9b13a04abf spi: multichip support 
move hardcoded numbers, etc. into soc files.
create headers for shared types which needs to be documented.

(MINOR CHANGE)
 2019-06-22 19:08:47 +08:00
Angus Gratton
bd9590502c Merge branch 'bugfix/spi_flash_remove_include_chain_in_host_drv' into 'master' 
esp_flash: support C++ and improve the document

See merge request idf/esp-idf!5287
 2019-06-21 13:12:09 +08:00
Angus Gratton
126b687c75 Merge branch 'refactor/vfs_uart_multichip_support' into 'master' 
vfs_uart & uart: add multichip support

See merge request idf/esp-idf!5298
 2019-06-20 18:31:24 +08:00
chenjianqiang
cf2ba210ef uart: multichip support 2019-06-20 11:32:22 +08:00
Michael (XIAO Xufeng)
caf121e4b6 esp_flash: break the inappropriate include chain in spi_flash_host_drv.h 2019-06-20 10:55:12 +08:00
Michael (XIAO Xufeng)
5c9dc44c49 spi: multichip support 
move hardcoded numbers, etc. into soc files.
create headers for shared types which needs to be documented.

(MINOR CHANGE)
 2019-06-20 10:38:52 +08:00
Darian Leung
037c079e9a esp32: Refactor backtrace and add esp_backtrace_print() 
This commit refactors backtracing within the panic handler so that a common
function esp_backtrace_get_next_frame() is used iteratively to traverse a
callstack.

A esp_backtrace_print() function has also be added that allows the printing
of a backtrace at runtime. The esp_backtrace_print() function allows unity to
print the backtrace of failed test cases and jump back to the main test menu
without the need reset the chip. esp_backtrace_print() can also be used as a
debugging function by users.

- esp_stack_ptr_is_sane() moved to soc_memory_layout.h
- removed uncessary includes of "esp_debug_helpers.h"
 2019-06-19 18:30:18 +08:00
suda-morris
3f7a571c90 fix errors when ci testing for esp32 2019-06-19 15:31:47 +08:00
Michael (XIAO Xufeng)
1036a091fe spi_flash: support working on differnt buses and frequency 2019-06-18 06:32:52 +00:00
suda-morris
91508ca27f add esp32s2beta in soc component 2019-06-11 13:06:32 +08:00
Konstantin Kondrashov
399d2d2605 all: Using xxx_periph.h 
Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... .

Cleaned up header files from unnecessary headers (releated to soc/... headers).
 2019-06-03 14:15:08 +08:00
Michael (XIAO Xufeng)
9a00b7706e fix the dram low addr defined in the soc.h header 2019-04-25 17:29:48 +08:00
Michael (XIAO Xufeng)
562af8f65e global: move the soc component out of the common list 
This MR removes the common dependency from every IDF components to the SOC component.

Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components.
But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components.

In CMAKE, we have two kinds of header visibilities (set by include path visibility):

(Assume component A --(depends on)--> B, B is the current component)

1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B)
2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only)

and we have two kinds of depending ways:

(Assume component A --(depends on)--> B --(depends on)--> C, B is the current component)

1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B)
2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B)

1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default.
2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it.
3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers
4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link)

This is a breaking change. Previous code may depends on the long include chain.
You may need to include the following headers for some files after this commit:

- soc/soc.h
- soc/soc_memory_layout.h
- driver/gpio.h
- esp_sleep.h

The major broken include chain includes:

1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h.
2. ets_sys.h no longer includes soc/soc.h
3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h

some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h

BREAKING CHANGE
 2019-04-16 13:21:15 +08:00
Angus Gratton
f871cc5ffa Merge branch 'feat/spi_hal_support' into 'master' 
spi_master: refactor and add HAL support

See merge request idf/esp-idf!4159
 2019-04-15 07:57:11 +08:00
Angus Gratton
8e91677701 Merge branch 'bugfix/bootloader_flash_crypt_cnt_ff' into 'master' 
flash encryption: reduce FLASH_CRYPT_CNT bit width to 7 bits

See merge request idf/esp-idf!4642
 2019-04-09 08:10:06 +08:00
huub
4aac441e46 soc:Added names to anonymous register structs 
For typedef volatile struct in components/soc/esp32/include/soc

Merges https://github.com/espressif/esp-idf/pull/3199
 2019-04-03 03:09:44 +00:00
Angus Gratton
4b4cd7fb51 efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field 
8th bit is not used by hardware.

As reported https://esp32.com/viewtopic.php?f=2&t=7800&p=40895#p40894
 2019-04-03 14:07:20 +11:00
Michael (XIAO Xufeng)
af2fc96ee1 spi_master: refactor and add HAL support 2019-03-28 17:14:50 +08:00
Ivan Grokhotkov
106dc05903 Merge branch 'feature/specify_includes_belonging_esp32' into 'master' 
move esp32 chip specific includes to esp32/xxx.h

See merge request idf/esp-idf!4534
 2019-03-21 18:34:08 +08:00
morris
956c25dedd move esp32 chip specific includes to esp32/xxx.h 2019-03-18 17:14:05 +08:00
Angus Gratton
2dd3344342 heap: Add integer overflow checks on MALLOC_CAP_32BIT & MALLOC_CAP_EXEC 2019-03-18 01:41:58 +00:00
Konstantin Kondrashov
d82023bf06 soc: Add support efuse 2019-02-28 07:31:29 +00:00
Ivan Grokhotkov
8cc6226051 soc: define named constants for DPORT_CPUPERIOD_SEL values 2019-02-26 17:07:59 +08:00