alex/esp-idf
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449 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
a58362a429 Merge branch 'feature/efuse_rev_major_minor' into 'master' 
efuse: Adds major and minor versions

See merge request espressif/esp-idf!18255
 2022-07-07 11:48:54 +08:00
Song Ruo Jing
b662f4b74f Merge branch 'feature/support_26M_32M_xtal_bbpll_c2' into 'master' 
support c2 26M/32M xtal for bbpll

Closes IDF-5485

See merge request espressif/esp-idf!18769
 2022-07-06 21:17:52 +08:00
cje
e16165f263 support c2 26M/32M xtal for bbpll 2022-07-05 17:45:03 +08:00
KonstantinKondrashov
0f8ff5aa15 efuse: Adds major and minor versions and others 2022-07-05 14:38:27 +08:00
Martin Vychodil
29c0703d7e Merge branch 'bugfix/esp32s3_memprot_wrong_check_unicore' into 'master' 
System/Security: fix missing checks for CPU-count sensitive Memprot APIs (ESP32S3)

Closes IDF-5401

See merge request espressif/esp-idf!18834
 2022-07-04 16:41:45 +08:00
Omar Chebib
7e42038c86 Merge branch 'refactor/move_regi2c_headers' into 'master' 
Refactor: move regi2c_*.h header files from esp_hw_support to soc component

See merge request espressif/esp-idf!18676
 2022-07-04 11:32:30 +08:00
Martin Vychodil
ee9aa9a302 System/Security: fix missing checks for CPU-count sensitive Memprot APIs (ESP32S3) 
Some of the Memory Protection (internal) API functions dealing with per-CPU operations were missing appropriate handling of the CPU count actually configured by CONFIG_FREERTOS_UNICORE. The flaw was fixed across all the places found in the code as the issue was of general type
 2022-07-02 20:12:56 +00:00
Cao Sen Miao
a690a87829 spi_flash: Remove legacy spi_flash drivers 2022-07-01 11:01:34 +08:00
Omar Chebib
cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component 
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
 2022-06-30 09:40:44 +00:00
morris
7fd9a91034 dma: move from driver to hw_support 2022-06-28 14:17:12 +08:00
Omar Chebib
8fae0f0753 G0: Support Xtensa targets for G0-only compilation 
G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
 2022-06-20 11:34:20 +00:00
Martin Vychodil
339fcbf14d System/Security: Memprot API unified (ESP32S3) 
Unified Memory protection API for all PMS-aware chips - ESP32S3 port
 2022-06-20 02:36:44 +00:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' 
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
 2022-06-16 11:53:39 +08:00
Armando (Dou Yiwen)
0b80546f8e Merge branch 'feature/new_esp_psram_component' into 'master' 
esp_psram: new esp psram component

Closes IDF-4318, IDF-4382, IDF-4841, and IDFGH-7192

See merge request espressif/esp-idf!18050
 2022-06-15 19:16:56 +08:00
Darian
e213e66ba3 Merge branch 'refactor/esp_hw_support_cpu' into 'master' 
esp_hw_support: Add new esp_cpu.h abstraction

Closes IDF-4769

See merge request espressif/esp-idf!17091
 2022-06-14 21:11:30 +08:00
Armando
cdad8a02fe esp_psram: remove g_spiram_ok 2022-06-14 15:44:27 +08:00
Armando
38e5043ae8 esp_psram: new psram component 2022-06-14 15:44:27 +08:00
Omar Chebib
2fd784c97a G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h" 2022-06-14 15:00:53 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer 
G0 doesn't depend on any G1+ layer for RISC-V based targets
 2022-06-14 15:00:53 +08:00
Darian Leung
61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API 
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
 2022-06-14 14:30:58 +08:00
Darian Leung
556ec30457 esp_hw_support: Rename cpu_util.c to cpu.c 2022-06-14 14:30:57 +08:00
songruojing
03477a59db rtc_clk: Fix rtc8m calibration failure after cpu/core reset 
1. make sure 8md256 clk is enabled before calibration
2. improve bootloader and application startup 8m, 8md256 enable logic
 2022-06-13 17:47:51 +08:00
songruojing
c8752cee6a clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem 2022-06-13 17:47:50 +08:00
Armando
44f771c713 psram: support s3 copy flash to psram 2022-06-10 10:39:29 +08:00
Cao Sen Miao
6589daabb9 MMU: Add configurable mmu page size support on ESP32C2 2022-06-08 19:34:31 +08:00
Michael (XIAO Xufeng)
773715d900 Merge branch 'feature/support_refresh_brownout_v1' into 'master' 
spi_flash: send reset when brownout detected on XMC flash

Closes IDF-3882

See merge request espressif/esp-idf!16873
 2022-06-06 16:27:58 +08:00
Michael (XIAO Xufeng)
d798662421 Merge branch 'bugfix/s3_sleep_voltage' into 'master' 
esp32s3: fixed dangerous power parameters in sleep modes

See merge request espressif/esp-idf!18168
 2022-06-04 00:47:32 +08:00
Cao Sen Miao
6a2d3509dc spi_flash: Making XMC flash works more stable when brownout detected 2022-06-02 10:38:55 +08:00
chaijie
e624206ca6 modify voltage param to fit all mode of S3 2022-06-01 21:03:54 +08:00
Michael (XIAO Xufeng)
ab69df3ea7 esp32s3: fixed dangerous power parameters in sleep modes 2022-06-01 21:03:54 +08:00
KonstantinKondrashov
ac4c7d99fe dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
Anton Maklakov
3c8a1390a0 Merge branch 'bugfix/esp-system-warnings' into 'master' 
system: minor fixes of warnings

See merge request espressif/esp-idf!18310
 2022-05-30 19:33:01 +08:00
Anton Maklakov
afde2434e8 memprot: fix type casting to avoid suspesious address arithmetic 2022-05-30 14:48:12 +07:00
jingli
9eec740a16 enable external 32k osc for esp32c2 2022-05-27 19:29:29 +08:00
Song Ruo Jing
cf32e49aeb Merge branch 'refactor/cleanup_rtc_h' into 'master' 
clk_tree: Prework2 of introducing clock subsystem control

Closes IDF-4934

See merge request espressif/esp-idf!17861
 2022-05-26 09:16:47 +08:00
Sachin Parekh
9a763f4ff2 esp32c2: Enable IRAM/DRAM split using PMP 2022-05-24 21:36:06 +05:30
songruojing
74c99a8a07 rtc_clk: Add alias for the clock tree related enum and macros for backwards compatibility 2022-05-24 22:59:51 +08:00
songruojing
729d70129a clk_tree: add initial docs for clock tree 2022-05-24 22:59:51 +08:00
songruojing
a5b09cf015 rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in 
soc/clk_tree_defs.h
 2022-05-24 22:59:41 +08:00
Marius Vikhammer
0687daf2c8 kconfig: move remaining kconfig options out of target component 
The kconfig options are moved to the component where they are used,
mostly esp_hw_support and esp_system.
 2022-05-23 17:57:45 +08:00
songruojing
436085de51 rtc_clk: fix potential "division by zero" in rtc_clk_cpu_freq_mhz_to_config (found by coverity scan) 2022-05-23 13:38:41 +08:00
songruojing
87b917c04a rtc_clk: Remove the ck8m fpu logic when setting rtc slow clock source, ck8m fpu in sleep logic is now completely handled in sleep_modes.c 2022-05-21 13:13:52 +00:00
Konstantin Kondrashov
8429ec2553 Merge branch 'feature/adds_check_32k_xtal_stopped' into 'master' 
esp_hw_support: Adds a msg when 32k xtal was stopped

See merge request espressif/esp-idf!17581
 2022-05-19 16:48:20 +08:00
Michael (XIAO Xufeng)
0adb814af3 Merge branch 'bugfix/fix_memory_miss_bug_esp32c3_esp32s3' into 'master' 
ESP32C3/ESP32S3: Fix cpu crash bug  when wakeup from lightsleep for memory data miss

Closes IDF-162 and IDF-4923

See merge request espressif/esp-idf!17823
 2022-05-18 12:05:08 +08:00
Michael (XIAO Xufeng)
adcdcbaa0e Merge branch 'feat/pm_dbias_refactoring' into 'master' 
pm: refactoring dbias related code

See merge request espressif/esp-idf!17994
 2022-05-17 14:42:16 +08:00
chaijie
cc0a5a4edb solve memory error bug when in lightsleep mode 2022-05-16 11:43:00 +08:00
Michael (XIAO Xufeng)
6f507d527c rtc: fixed 8MD256 can't be used as RTC slow src on ESP32 
Sync configuration from other chips

Closes: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089
 2022-05-14 22:35:41 +08:00
Michael (XIAO Xufeng)
234628b3ea pm: putting dbias and pd_cur code into same function 2022-05-14 02:35:11 +08:00
Jing Li
ac0d16cdc8 Merge branch 'bugfix/fix_cannot_lslp_again_after_ulp_wakeup' into 'master' 
sleep: fix cannot lightsleep again after a wakeup from ULP

Closes IDFGH-4396

See merge request espressif/esp-idf!17970
 2022-05-13 22:25:23 +08:00
jingli
abb6bb1181 esp_hw_support/sleep: fix cannot enable sleep reject in some cases 
When enable sleep reject before this fix, we have two limitations:
1. it must be light sleep
2. RTC GPIO wakeup source must be set

We require light sleep because `esp_deep_sleep_start` function has
been declared with "noreturn" attribute, So developers don't expect
that this function may return (due to an error or a sleep reject).
But the requirement for RTC GPIO wakeup source is not reasonable for
all chips. This requirement exists because ESP32 only supports RTC GPIO
and SDIO sleep reject sources. But later chips support all sleep reject
sources.

This fix brings the following changes:
for ESP32: RTC GPIO and SDIO sleep reject sources can be enabled
           when corresponding wakeup source is set.

for later chips: all sleep reject sources can be enabled when
                 corresponding wakeup source is set.
 2022-05-12 19:09:57 +08:00