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Merge branch 'feature/support_26M_32M_xtal_bbpll_c2' into 'master'
support c2 26M/32M xtal for bbpll Closes IDF-5485 See merge request espressif/esp-idf!18769
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commit
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@ -139,6 +139,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
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clk_ll_cpu_set_divider(1);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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rtc_clk_apb_freq_update(40 * MHZ);
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ets_update_cpu_frequency(cpu_freq_mhz);
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}
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@ -224,16 +224,45 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint
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static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
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{
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(void)pll_freq_mhz;
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(void)xtal_freq_mhz;
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// ESP32C2 only support 40M XTAL, all the parameters are given as 40M XTAL directly
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uint8_t div_ref = 0;
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uint8_t div7_0 = 8;
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uint8_t dr1 = 0;
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uint8_t dr3 = 0;
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uint8_t dchgp = 5;
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uint8_t dcur = 3;
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uint8_t dbias = 2;
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uint8_t div_ref;
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uint8_t div7_0;
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uint8_t dr1;
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uint8_t dr3;
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uint8_t dchgp;
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uint8_t dcur;
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uint8_t dbias;
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/* Configure 480M PLL */
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switch (xtal_freq_mhz) {
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case RTC_XTAL_FREQ_26M:
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div_ref = 12;
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div7_0 = 236;
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dr1 = 4;
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dr3 = 4;
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dchgp = 0;
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dcur = 0;
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dbias = 2;
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break;
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case RTC_XTAL_FREQ_32M:
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div_ref = 0;
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div7_0 = 11;
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dr1 = 0;
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dr3 = 0;
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dchgp = 5;
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dcur = 3;
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dbias = 2;
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break;
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case RTC_XTAL_FREQ_40M:
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default:
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div_ref = 0;
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div7_0 = 8;
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dr1 = 0;
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dr3 = 0;
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dchgp = 5;
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dcur = 3;
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dbias = 2;
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break;
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}
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
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uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
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uint8_t i2c_bbpll_div_7_0 = div7_0;
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@ -492,12 +521,14 @@ static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void)
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{
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// ESP32C2 has a fixed crystal frequency (40MHz), but we will still read from the RTC storage register
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// Read from RTC storage register
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uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
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if ((xtal_freq_reg & UINT16_MAX) != RTC_XTAL_FREQ_40M) {
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return 0;
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if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) &&
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xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) {
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return xtal_freq_reg & UINT16_MAX;
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}
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return (uint32_t)RTC_XTAL_FREQ_40M;
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// If the format in reg is invalid
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return 0;
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}
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/**
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@ -127,6 +127,8 @@ storing in efuse (based on ATE 5k ECO3 chips)
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* Enum values should be equal to frequency in MHz.
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*/
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typedef enum {
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RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL
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RTC_XTAL_FREQ_32M = 32, //!< 32 MHz XTAL
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RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
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} rtc_xtal_freq_t;
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