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kconfig: move remaining kconfig options out of target component

Browse Source 
The kconfig options are moved to the component where they are used,
mostly esp_hw_support and esp_system.
This commit is contained in:
Marius Vikhammer 2022-05-10 12:27:36 +08:00
parent 179ea878c7
commit 0687daf2c8
137 changed files with 1356 additions and 1416 deletions
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42
Kconfig
View File

@ -200,6 +200,48 @@ mainmenu "Espressif IoT Development Framework Configuration"
If enabled, this disables the linking of binary libraries in the application build. Note
that after enabling this Wi-Fi/Bluetooth will not work.
config APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS
bool "App compatible with bootloaders before ESP-IDF v2.1"
select APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS
depends on IDF_TARGET_ESP32
default n
help
Bootloaders before ESP-IDF v2.1 did less initialisation of the
system clock. This setting needs to be enabled to build an app
which can be booted by these older bootloaders.
If this setting is enabled, the app can be booted by any bootloader
from IDF v1.0 up to the current version.
If this setting is disabled, the app can only be booted by bootloaders
from IDF v2.1 or newer.
Enabling this setting adds approximately 1KB to the app's IRAM usage.
config APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS
bool "App compatible with bootloader and partition table before ESP-IDF v3.1"
depends on IDF_TARGET_ESP32
default n
help
Partition tables before ESP-IDF V3.1 do not contain an MD5 checksum
field, and the bootloader before ESP-IDF v3.1 cannot read a partition
table that contains an MD5 checksum field.
Enable this option only if your app needs to boot on a bootloader and/or
partition table that was generated from a version *before* ESP-IDF v3.1.
If this option and Flash Encryption are enabled at the same time, and any
data partitions in the partition table are marked Encrypted, then the
partition encrypted flag should be manually verified in the app before accessing
the partition (see CVE-2021-27926).
config APP_INIT_CLK
bool
depends on IDF_TARGET_ESP32
default y if APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS
default y if APP_BUILD_TYPE_ELF_RAM
endmenu # Build type
source "$COMPONENT_KCONFIGS_PROJBUILD_SOURCE_FILE"

2
components/bootloader/Kconfig.projbuild
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@ -805,7 +805,7 @@ menu "Security features"
config SECURE_FLASH_ENCRYPTION_MODE_RELEASE
bool "Release"
select PARTITION_TABLE_MD5 if !ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS
select PARTITION_TABLE_MD5 if !APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS
endchoice

4
components/bt/esp_ble_mesh/Kconfig.in
View File

@ -68,7 +68,7 @@ if BLE_MESH
config BLE_MESH_FREERTOS_STATIC_ALLOC
bool "Enable FreeRTOS static allocation"
depends on FREERTOS_SUPPORT_STATIC_ALLOCATION && (ESP32_SPIRAM_SUPPORT || ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)
depends on FREERTOS_SUPPORT_STATIC_ALLOCATION && ((IDF_TARGET_ESP32 && SPIRAM) || ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY) # NOERROR
default n
help
Enable this option to use FreeRTOS static allocation APIs for BLE Mesh,
@ -85,7 +85,7 @@ if BLE_MESH
config BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL
bool "External SPIRAM"
depends on ESP32_SPIRAM_SUPPORT
depends on IDF_TARGET_ESP32 && SPIRAM
help
If enabled, BLE Mesh allocates dynamic memory from external SPIRAM for
FreeRTOS objects, i.e. mutex, queue, and task stack. External SPIRAM

4
components/driver/test/test_spi_bus_lock.c
View File

@ -43,7 +43,7 @@ typedef struct {
bool finished;
} task_context_t;
#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
#if !(CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32)
const static char TAG[] = "test_spi";
@ -347,4 +347,4 @@ TEST_CASE("spi master can be used on SPI1", "[spi]")
//TODO: add a case when a non-polling transaction happened in the bus-acquiring time and then release the bus then queue a new trans
#endif //!CONFIG_ESP32_SPIRAM_SUPPORT
#endif //!(CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32)

603
components/esp32/Kconfig
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@ -1,603 +0,0 @@
menu "ESP32-specific"
# TODO: this component simply shouldn't be included
# in the build at the CMake level, but this is currently
# not working so we just hide all items here
visible if IDF_TARGET_ESP32
config ESP32_ECO3_CACHE_LOCK_FIX
bool
default y
depends on !FREERTOS_UNICORE && ESP32_SPIRAM_SUPPORT
config ESP32_DPORT_WORKAROUND
bool
default "y" if !FREERTOS_UNICORE && ESP32_REV_MIN < 2
# Note: to support SPIRAM across multiple chips, check CONFIG_SPIRAM
# instead
config ESP32_SPIRAM_SUPPORT
bool "Support for external, SPI-connected RAM"
default "n"
select SPIRAM
help
This enables support for an external SPI RAM chip, connected in parallel with the
main SPI flash chip.
menu "SPI RAM config"
depends on ESP32_SPIRAM_SUPPORT
config SPIRAM_MODE_QUAD
bool
default "y"
choice SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
default SPIRAM_TYPE_AUTO
config SPIRAM_TYPE_AUTO
bool "Auto-detect"
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32"
config SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 or LY68L6400"
endchoice
config SPIRAM_SIZE
int
default -1 if SPIRAM_TYPE_AUTO
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0
choice SPIRAM_SPEED
prompt "Set RAM clock speed"
default SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz
Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
will be occupied by the system. Which SPI host to use can be selected by the config item
SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
(ESPTOOLPY_FLASHFREQ_80M is true)
config SPIRAM_SPEED_40M
bool "40MHz clock speed"
config SPIRAM_SPEED_80M
depends on ESPTOOLPY_FLASHFREQ_80M
bool "80MHz clock speed"
endchoice
# insert non-chip-specific items here
source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common"
config SPIRAM_CACHE_WORKAROUND
bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
default "y"
help
Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a
fix in the compiler (-mfix-esp32-psram-cache-issue) that makes sure the specific code that is
vulnerable to this will not be emitted.
This will also not use any bits of newlib that are located in ROM, opting for a version that is
compiled with the workaround and located in flash instead.
The workaround is not required for ESP32 revision 3 and above.
menu "SPIRAM cache workaround debugging"
choice SPIRAM_CACHE_WORKAROUND_STRATEGY
prompt "Workaround strategy"
depends on SPIRAM_CACHE_WORKAROUND
default SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
help
Select the workaround strategy. Note that the strategy for precompiled
libraries (libgcc, newlib, bt, wifi) is not affected by this selection.
Unless you know you need a different strategy, it's suggested you stay
with the default MEMW strategy. Note that DUPLDST can interfere with hardware
encryption and this will be automatically disabled if this workaround is selected.
'Insert nops' is the workaround that was used in older esp-idf versions. This workaround
still can cause faulty data transfers from/to SPI RAM in some situation.
config SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
bool "Insert memw after vulnerable instructions (default)"
config SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
bool "Duplicate LD/ST for 32-bit, memw for 8/16 bit"
config SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS
bool "Insert nops between vulnerable loads/stores (old strategy, obsolete)"
endchoice
#This needs to be Y only for the dupldst workaround
config SPIRAM_WORKAROUND_NEED_VOLATILE_SPINLOCK
bool
default "y" if SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
endmenu
menu "SPIRAM workaround libraries placement"
visible if SPIRAM_CACHE_WORKAROUND
config SPIRAM_CACHE_LIBJMP_IN_IRAM
bool "Put libc's jump related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: longjmp and setjmp.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBMATH_IN_IRAM
bool "Put libc's math related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: abs, div, labs, ldiv, quorem, fpclassify,
and nan.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM
bool "Put libc's number parsing related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: utoa, itoa, atoi, atol, strtol, and strtoul.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBIO_IN_IRAM
bool "Put libc's I/O related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: wcrtomb, fvwrite, wbuf, wsetup, fputwc, wctomb_r,
ungetc, makebuf, fflush, refill, and sccl.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBTIME_IN_IRAM
bool "Put libc's time related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: asctime, asctime_r, ctime, ctime_r, lcltime, lcltime_r,
gmtime, gmtime_r, strftime, mktime, tzset_r, tzset, time, gettzinfo, systimes, month_lengths,
timelocal, tzvars, tzlock, tzcalc_limits, and strptime.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBCHAR_IN_IRAM
bool "Put libc's characters related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: ctype_, toupper, tolower, toascii, strupr, bzero,
isalnum, isalpha, isascii, isblank, iscntrl, isdigit, isgraph, islower, isprint, ispunct,
isspace, and isupper.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBMEM_IN_IRAM
bool "Put libc's memory related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: memccpy, memchr memmove, and memrchr.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBSTR_IN_IRAM
bool "Put libc's string related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: strcasecmp, strcasestr, strchr, strcoll,
strcpy, strcspn, strdup, strdup_r, strlcat, strlcpy, strlen, strlwr, strncasecmp,
strncat, strncmp, strncpy, strndup, strndup_r, strrchr, strsep, strspn, strstr,
strtok_r, and strupr.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBRAND_IN_IRAM
bool "Put libc's random related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: srand, rand, and rand_r.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBENV_IN_IRAM
bool "Put libc's environment related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: environ, envlock, and getenv_r.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBFILE_IN_IRAM
bool "Put libc's file related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: lock, isatty, fclose, open, close, creat, read,
rshift, sbrk, stdio, syssbrk, sysclose, sysopen, creat, sysread, syswrite, impure, fwalk,
and findfp.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBMISC_IN_IRAM
bool "Put libc's miscellaneous functions in IRAM, see help"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: raise and system
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
endmenu
config SPIRAM_BANKSWITCH_ENABLE
bool "Enable bank switching for >4MiB external RAM"
default y
depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
help
The ESP32 only supports 4MiB of external RAM in its address space. The hardware does support larger
memories, but these have to be bank-switched in and out of this address space. Enabling this allows you
to reserve some MMU pages for this, which allows the use of the esp_himem api to manage these banks.
#Note that this is limited to 62 banks, as esp_spiram_writeback_cache needs some kind of mapping of
#some banks below that mark to work. We cannot at this moment guarantee this to exist when himem is
#enabled.
If spiram 2T mode is enabled, the size of 64Mbit psram will be changed as 32Mbit, so himem will be
unusable.
config SPIRAM_BANKSWITCH_RESERVE
int "Amount of 32K pages to reserve for bank switching"
depends on SPIRAM_BANKSWITCH_ENABLE
default 8
range 1 62
help
Select the amount of banks reserved for bank switching. Note that the amount of RAM allocatable with
malloc/esp_heap_alloc_caps will decrease by 32K for each page reserved here.
Note that this reservation is only actually done if your program actually uses the himem API. Without
any himem calls, the reservation is not done and the original amount of memory will be available
to malloc/esp_heap_alloc_caps.
config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
bool "Allow external memory as an argument to xTaskCreateStatic"
default n
depends on SPIRAM_USE_MALLOC
help
Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround,
normally tasks cannot be safely run with their stack residing in external memory; for this reason
xTaskCreate (and related task creaton functions) always allocate stack in internal memory and
xTaskCreateStatic will check if the memory passed to it is in internal memory. If you have a task that
needs a large amount of stack and does not call on ROM code in any way (no direct calls, but also no
Bluetooth/WiFi), you can try enable this to cause xTaskCreateStatic to allow tasks stack in external
memory.
choice SPIRAM_OCCUPY_SPI_HOST
prompt "SPI host to use for 32MBit PSRAM"
default SPIRAM_OCCUPY_VSPI_HOST
depends on SPIRAM_SPEED_80M
help
When both flash and PSRAM is working under 80MHz, and the PSRAM is of type 32MBit, one of the HSPI/VSPI
host will be used to output the clock. Select which one to use here.
config SPIRAM_OCCUPY_HSPI_HOST
bool "HSPI host (SPI2)"
config SPIRAM_OCCUPY_VSPI_HOST
bool "VSPI host (SPI3)"
config SPIRAM_OCCUPY_NO_HOST
bool "Will not try to use any host, will abort if not able to use the PSRAM"
endchoice
menu "PSRAM clock and cs IO for ESP32-DOWD"
config D0WD_PSRAM_CLK_IO
int "PSRAM CLK IO number"
depends on ESP32_SPIRAM_SUPPORT
range 0 33
default 17
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
config D0WD_PSRAM_CS_IO
int "PSRAM CS IO number"
depends on ESP32_SPIRAM_SUPPORT
range 0 33
default 16
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu
menu "PSRAM clock and cs IO for ESP32-D2WD"
config D2WD_PSRAM_CLK_IO
int "PSRAM CLK IO number"
depends on ESP32_SPIRAM_SUPPORT
range 0 33
default 9
help
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
config D2WD_PSRAM_CS_IO
int "PSRAM CS IO number"
depends on ESP32_SPIRAM_SUPPORT
range 0 33
default 10
help
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu
menu "PSRAM clock and cs IO for ESP32-PICO"
config PICO_PSRAM_CS_IO
int "PSRAM CS IO number"
depends on ESP32_SPIRAM_SUPPORT
range 0 33
default 10
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
IO.
For the reference hardware design, please refer to
https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
endmenu
config SPIRAM_CUSTOM_SPIWP_SD3_PIN
bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
default n
help
This setting is only used if the SPI flash pins have been overridden by setting the eFuses
SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
mode, so a WP pin setting is necessary.
If this config item is set to N (default), the correct WP pin will be automatically used for any
Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
to Y and specify the GPIO number connected to the WP pin.
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
configured in the bootloader.
config SPIRAM_SPIWP_SD3_PIN
int "Custom SPI PSRAM WP(SD3) Pin"
depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
#depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN # backwards compatibility, can uncomment in IDF 5
range 0 33
default 7
help
The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
value to the GPIO number of the SPIRAM WP pin.
config SPIRAM_2T_MODE
bool "Enable SPI PSRAM 2T mode"
depends on ESP32_SPIRAM_SUPPORT
default "n"
help
Enable this option to fix single bit errors inside 64Mbit PSRAM.
Some 64Mbit PSRAM chips have a hardware issue in the RAM which causes bit errors at multiple
fixed bit positions.
Note: If this option is enabled, the 64Mbit PSRAM chip will appear to be 32Mbit in size.
Applications will not be affected unless the use the esp_himem APIs, which are not supported
in 2T mode.
endmenu # "SPI RAM config"
config ESP32_MEMMAP_TRACEMEM
bool
default "n"
config ESP32_MEMMAP_TRACEMEM_TWOBANKS
bool
default "n"
config ESP32_TRAX
bool "Use TRAX tracing feature"
default "n"
select ESP32_MEMMAP_TRACEMEM
help
The ESP32 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config ESP32_TRAX_TWOBANKS
bool "Reserve memory for tracing both pro as well as app cpu execution"
default "n"
depends on ESP32_TRAX && !FREERTOS_UNICORE
select ESP32_MEMMAP_TRACEMEM_TWOBANKS
help
The ESP32 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
# Memory to reverse for trace, used in linker script
config ESP32_TRACEMEM_RESERVE_DRAM
hex
default 0x8000 if ESP32_MEMMAP_TRACEMEM && ESP32_MEMMAP_TRACEMEM_TWOBANKS
default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS
default 0x0
config ESP32_DEEP_SLEEP_WAKEUP_DELAY
int "Extra delay in deep sleep wake stub (in us)"
default 2000
range 0 5000
help
When ESP32 exits deep sleep, the CPU and the flash chip are powered on
at the same time. CPU will run deep sleep stub first, and then
proceed to load code from flash. Some flash chips need sufficient
time to pass between power on and first read operation. By default,
without any extra delay, this time is approximately 900us, although
some flash chip types need more than that.
By default extra delay is set to 2000us. When optimizing startup time
for applications which require it, this value may be reduced.
If you are seeing "flash read err, 1000" message printed to the
console after deep sleep reset, try increasing this value.
choice ESP32_XTAL_FREQ_SEL
prompt "Main XTAL frequency"
default ESP32_XTAL_FREQ_40
help
ESP32 currently supports the following XTAL frequencies:
- 26 MHz
- 40 MHz
Startup code can automatically estimate XTAL frequency. This feature
uses the internal 8MHz oscillator as a reference. Because the internal
oscillator frequency is temperature dependent, it is not recommended
to use automatic XTAL frequency detection in applications which need
to work at high ambient temperatures and use high-temperature
qualified chips and modules.
config ESP32_XTAL_FREQ_40
bool "40 MHz"
config ESP32_XTAL_FREQ_26
bool "26 MHz"
config ESP32_XTAL_FREQ_AUTO
bool "Autodetect"
endchoice
# Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h
config ESP32_XTAL_FREQ
int
default 0 if ESP32_XTAL_FREQ_AUTO
default 40 if ESP32_XTAL_FREQ_40
default 26 if ESP32_XTAL_FREQ_26
config ESP32_DISABLE_BASIC_ROM_CONSOLE
bool "Permanently disable BASIC ROM Console"
default n
help
If set, the first time the app boots it will disable the BASIC ROM Console
permanently (by burning an eFuse).
Otherwise, the BASIC ROM Console starts on reset if no valid bootloader is
read from the flash.
(Enabling secure boot also disables the BASIC ROM Console by default.)
config ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
bool "App compatible with bootloaders before ESP-IDF v2.1"
select ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS
default n
help
Bootloaders before ESP-IDF v2.1 did less initialisation of the
system clock. This setting needs to be enabled to build an app
which can be booted by these older bootloaders.
If this setting is enabled, the app can be booted by any bootloader
from IDF v1.0 up to the current version.
If this setting is disabled, the app can only be booted by bootloaders
from IDF v2.1 or newer.
Enabling this setting adds approximately 1KB to the app's IRAM usage.
config ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS
bool "App compatible with bootloader and partition table before ESP-IDF v3.1"
default n
help
Partition tables before ESP-IDF V3.1 do not contain an MD5 checksum
field, and the bootloader before ESP-IDF v3.1 cannot read a partition
table that contains an MD5 checksum field.
Enable this option only if your app needs to boot on a bootloader and/or
partition table that was generated from a version *before* ESP-IDF v3.1.
If this option and Flash Encryption are enabled at the same time, and any
data partitions in the partition table are marked Encrypted, then the
partition encrypted flag should be manually verified in the app before accessing
the partition (see CVE-2021-27926).
config ESP32_APP_INIT_CLK
bool
default y if ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
default y if APP_BUILD_TYPE_ELF_RAM
config ESP32_RTCDATA_IN_FAST_MEM
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
default n
depends on FREERTOS_UNICORE
help
This option allows to place .rtc_data and .rtc_rodata sections into
RTC fast memory segment to free the slow memory region for ULP programs.
This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory
can be accessed only by PRO_CPU core.
config ESP32_USE_FIXED_STATIC_RAM_SIZE
bool "Use fixed static RAM size"
default n
help
If this option is disabled, the DRAM part of the heap starts right after the .bss section,
within the dram0_0 region. As a result, adding or removing some static variables
will change the available heap size.
If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
where its length is set with ESP32_FIXED_STATIC_RAM_SIZE
config ESP32_FIXED_STATIC_RAM_SIZE
hex "Fixed Static RAM size"
default 0x1E000
range 0 0x2c200
depends on ESP32_USE_FIXED_STATIC_RAM_SIZE
help
RAM size dedicated for static variables (.data & .bss sections).
Please note that the actual length will be reduced by BTDM_RESERVE_DRAM if Bluetooth
controller is enabled.
config ESP32_DPORT_DIS_INTERRUPT_LVL
int "Disable the interrupt level for the DPORT workarounds"
default 5
help
To prevent interrupting DPORT workarounds,
need to disable interrupt with a maximum used level in the system.
config ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
bool "Enable IRAM as 8 bit accessible memory"
depends on FREERTOS_UNICORE
help
If enabled, application can use IRAM as byte accessible region for storing data
(Note: IRAM region cannot be used as task stack)
This is possible due to handling of exceptions `LoadStoreError (3)` and `LoadStoreAlignmentError (9)`
Each unaligned read/write access will incur a penalty of maximum of 167 CPU cycles.
endmenu # ESP32-Specific

13
components/esp32/sdkconfig.rename
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@ -1,13 +0,0 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
# ESP32-specific
CONFIG_SPIRAM_SUPPORT CONFIG_ESP32_SPIRAM_SUPPORT
CONFIG_MEMMAP_TRACEMEM CONFIG_ESP32_MEMMAP_TRACEMEM
CONFIG_MEMMAP_TRACEMEM_TWOBANKS CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS
CONFIG_TRACEMEM_RESERVE_DRAM CONFIG_ESP32_TRACEMEM_RESERVE_DRAM
CONFIG_DISABLE_BASIC_ROM_CONSOLE CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
# SPI RAM config
CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP

37
components/esp32c2/Kconfig
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@ -1,37 +0,0 @@
menu "ESP32C2-Specific"
visible if IDF_TARGET_ESP32C2
menu "Cache config"
choice ESP32C2_MMU_PAGE_SIZE
# TODO: IDF-3821
prompt "Cache page size"
default ESP32C2_MMU_PAGE_SIZE_64KB
help
Cache page size to be set on application startup
config ESP32C2_MMU_PAGE_SIZE_16KB
bool "16KB"
config ESP32C2_MMU_PAGE_SIZE_32KB
bool "32KB"
config ESP32C2_MMU_PAGE_SIZE_64KB
bool "64KB"
endchoice
config ESP32C2_INSTRUCTION_CACHE_WRAP
bool
prompt "Instruction cache wrap"
help
If enabled, instruction cache will use wrap mode to read spi flash.
The wrap length is fixed to 32B
config ESP32C2_MMU_PAGE_MODE
int
default 0 if ESP32C2_MMU_PAGE_SIZE_16KB
default 1 if ESP32C2_MMU_PAGE_SIZE_32KB
default 2 if ESP32C2_MMU_PAGE_SIZE_64KB
endmenu
endmenu # ESP32C2-Specific

246
components/esp32s2/Kconfig
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@ -1,246 +0,0 @@
menu "ESP32S2-specific"
# TODO: this component simply shouldn't be included
# in the build at the CMake level, but this is currently
# not working so we just hide all items here
visible if IDF_TARGET_ESP32S2
menu "Cache config"
choice ESP32S2_INSTRUCTION_CACHE_SIZE
prompt "Instruction cache size"
default ESP32S2_INSTRUCTION_CACHE_8KB
help
Instruction cache size to be set on application startup.
If you use 8KB instruction cache rather than 16KB instruction cache,
then the other 8KB will be added to the heap.
config ESP32S2_INSTRUCTION_CACHE_8KB
bool "8KB"
config ESP32S2_INSTRUCTION_CACHE_16KB
bool "16KB"
endchoice
choice ESP32S2_INSTRUCTION_CACHE_LINE_SIZE
prompt "Instruction cache line size"
default ESP32S2_INSTRUCTION_CACHE_LINE_32B
help
Instruction cache line size to be set on application startup.
config ESP32S2_INSTRUCTION_CACHE_LINE_16B
bool "16 Bytes"
config ESP32S2_INSTRUCTION_CACHE_LINE_32B
bool "32 Bytes"
endchoice
choice ESP32S2_DATA_CACHE_SIZE
prompt "Data cache size"
default ESP32S2_DATA_CACHE_0KB if !ESP32S2_SPIRAM_SUPPORT
default ESP32S2_DATA_CACHE_8KB if ESP32S2_SPIRAM_SUPPORT
help
Data cache size to be set on application startup.
If you use 0KB data cache, the other 16KB will be added to the heap
If you use 8KB data cache rather than 16KB data cache, the other 8KB will be added to the heap
config ESP32S2_DATA_CACHE_0KB
depends on !ESP32S2_SPIRAM_SUPPORT
bool "0KB"
config ESP32S2_DATA_CACHE_8KB
bool "8KB"
config ESP32S2_DATA_CACHE_16KB
bool "16KB"
endchoice
choice ESP32S2_DATA_CACHE_LINE_SIZE
prompt "Data cache line size"
default ESP32S2_DATA_CACHE_LINE_32B
help
Data cache line size to be set on application startup.
config ESP32S2_DATA_CACHE_LINE_16B
bool "16 Bytes"
config ESP32S2_DATA_CACHE_LINE_32B
bool "32 Bytes"
endchoice
config ESP32S2_INSTRUCTION_CACHE_WRAP
bool "Enable instruction cache wrap"
default "n"
help
If enabled, instruction cache will use wrap mode to read spi flash (maybe spiram).
The wrap length equals to INSTRUCTION_CACHE_LINE_SIZE.
However, it depends on complex conditions.
config ESP32S2_DATA_CACHE_WRAP
bool "Enable data cache wrap"
default "n"
help
If enabled, data cache will use wrap mode to read spiram (maybe spi flash).
The wrap length equals to DATA_CACHE_LINE_SIZE.
However, it depends on complex conditions.
endmenu # Cache config
# Note: to support SPIRAM across multiple chips, check CONFIG_SPIRAM
# instead
config ESP32S2_SPIRAM_SUPPORT
bool "Support for external, SPI-connected RAM"
default "n"
select SPIRAM
help
This enables support for an external SPI RAM chip, connected in parallel with the
main SPI flash chip.
menu "SPI RAM config"
depends on ESP32S2_SPIRAM_SUPPORT
config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
bool
default "y"
config SPIRAM_MODE_QUAD
bool
default "y"
choice SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
default SPIRAM_TYPE_AUTO
config SPIRAM_TYPE_AUTO
bool "Auto-detect"
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32"
config SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 or LY68L6400"
endchoice
config SPIRAM_SIZE
int
default -1 if SPIRAM_TYPE_AUTO
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0
menu "PSRAM clock and cs IO for ESP32S2"
depends on ESP32S2_SPIRAM_SUPPORT
config DEFAULT_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 30
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design.
config DEFAULT_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 26
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM"
default n
help
If enabled, instruction in flash will be copied into SPIRAM.
If SPIRAM_RODATA also enabled,
you can run the instruction when erasing or programming the flash.
config SPIRAM_RODATA
bool "Cache load read only data from SPI RAM"
default n
help
If enabled, radata in flash will be copied into SPIRAM.
If SPIRAM_FETCH_INSTRUCTIONS also enabled,
you can run the instruction when erasing or programming the flash.
choice SPIRAM_SPEED
prompt "Set RAM clock speed"
default SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
config SPIRAM_SPEED_80M
bool "80MHz clock speed"
config SPIRAM_SPEED_40M
bool "40Mhz clock speed"
config SPIRAM_SPEED_26M
bool "26Mhz clock speed"
config SPIRAM_SPEED_20M
bool "20Mhz clock speed"
endchoice
config SPIRAM_SPEED
int
default 80 if SPIRAM_SPEED_80M
default 40 if SPIRAM_SPEED_40M
default 40 if SPIRAM_SPEED_26M
default 40 if SPIRAM_SPEED_20M
source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common" #insert non-chip-specific items here
endmenu
config ESP32S2_MEMMAP_TRACEMEM
bool
default "n"
config ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
bool
default "n"
config ESP32S2_TRAX
bool "Use TRAX tracing feature"
default "n"
select ESP32S2_MEMMAP_TRACEMEM
help
The ESP32S2 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config ESP32S2_TRACEMEM_RESERVE_DRAM
hex
default 0x8000 if ESP32S2_MEMMAP_TRACEMEM && ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
default 0x4000 if ESP32S2_MEMMAP_TRACEMEM && !ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
default 0x0
config ESP32S2_KEEP_USB_ALIVE
bool "Keep USB peripheral enabled at start up" if !ESP_CONSOLE_USB_CDC
default y if ESP_CONSOLE_USB_CDC
help
During the application initialization process, all the peripherals except UARTs and timers
are reset. Enable this option to keep USB peripheral enabled.
This option is automatically enabled if "USB CDC" console is selected.
config ESP32S2_RTCDATA_IN_FAST_MEM
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
default n
help
This option allows to place .rtc_data and .rtc_rodata sections into
RTC fast memory segment to free the slow memory region for ULP programs.
config ESP32S2_USE_FIXED_STATIC_RAM_SIZE
bool "Use fixed static RAM size"
default n
help
If this option is disabled, the DRAM part of the heap starts right after the .bss section,
within the dram0_0 region. As a result, adding or removing some static variables
will change the available heap size.
If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
where its length is set with ESP32S2_FIXED_STATIC_RAM_SIZE
config ESP32S2_FIXED_STATIC_RAM_SIZE
hex "Fixed Static RAM size"
default 0x10000
range 0 0x34000
depends on ESP32S2_USE_FIXED_STATIC_RAM_SIZE
help
RAM size dedicated for static variables (.data & .bss sections).
endmenu # ESP32S2-Specific

333
components/esp32s3/Kconfig
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@ -1,333 +0,0 @@
menu "ESP32S3-Specific"
visible if IDF_TARGET_ESP32S3
menu "Cache config"
choice ESP32S3_INSTRUCTION_CACHE_SIZE
prompt "Instruction cache size"
default ESP32S3_INSTRUCTION_CACHE_16KB
help
Instruction cache size to be set on application startup.
If you use 16KB instruction cache rather than 32KB instruction cache,
then the other 16KB will be managed by heap allocator.
config ESP32S3_INSTRUCTION_CACHE_16KB
bool "16KB"
config ESP32S3_INSTRUCTION_CACHE_32KB
bool "32KB"
endchoice
config ESP32S3_INSTRUCTION_CACHE_SIZE
hex
default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB
default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB
choice ESP32S3_ICACHE_ASSOCIATED_WAYS
prompt "Instruction cache associated ways"
default ESP32S3_INSTRUCTION_CACHE_8WAYS
help
Instruction cache associated ways to be set on application startup.
config ESP32S3_INSTRUCTION_CACHE_4WAYS
bool "4 ways"
config ESP32S3_INSTRUCTION_CACHE_8WAYS
bool "8 ways"
endchoice
config ESP32S3_ICACHE_ASSOCIATED_WAYS
int
default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS
default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS
choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
prompt "Instruction cache line size"
default ESP32S3_INSTRUCTION_CACHE_LINE_32B
help
Instruction cache line size to be set on application startup.
config ESP32S3_INSTRUCTION_CACHE_LINE_16B
bool "16 Bytes"
depends on ESP32S3_INSTRUCTION_CACHE_16KB
config ESP32S3_INSTRUCTION_CACHE_LINE_32B
bool "32 Bytes"
endchoice
config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
int
default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B
default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B
config ESP32S3_INSTRUCTION_CACHE_WRAP
bool ## TODO IDF-4307
default "n"
depends on !SPIRAM_ECC_ENABLE
help
If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE.
However, it depends on complex conditions.
choice ESP32S3_DATA_CACHE_SIZE
prompt "Data cache size"
default ESP32S3_DATA_CACHE_32KB
help
Data cache size to be set on application startup.
If you use 32KB data cache rather than 64KB data cache,
the other 32KB will be added to the heap.
config ESP32S3_DATA_CACHE_16KB
bool "16KB"
config ESP32S3_DATA_CACHE_32KB
bool "32KB"
config ESP32S3_DATA_CACHE_64KB
bool "64KB"
endchoice
config ESP32S3_DATA_CACHE_SIZE
hex
# For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
default 0x8000 if ESP32S3_DATA_CACHE_16KB
default 0x8000 if ESP32S3_DATA_CACHE_32KB
default 0x10000 if ESP32S3_DATA_CACHE_64KB
choice ESP32S3_DCACHE_ASSOCIATED_WAYS
prompt "Data cache associated ways"
default ESP32S3_DATA_CACHE_8WAYS
help
Data cache associated ways to be set on application startup.
config ESP32S3_DATA_CACHE_4WAYS
bool "4 ways"
config ESP32S3_DATA_CACHE_8WAYS
bool "8 ways"
endchoice
config ESP32S3_DCACHE_ASSOCIATED_WAYS
int
default 4 if ESP32S3_DATA_CACHE_4WAYS
default 8 if ESP32S3_DATA_CACHE_8WAYS
choice ESP32S3_DATA_CACHE_LINE_SIZE
prompt "Data cache line size"
default ESP32S3_DATA_CACHE_LINE_32B
help
Data cache line size to be set on application startup.
config ESP32S3_DATA_CACHE_LINE_16B
bool "16 Bytes"
depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB
config ESP32S3_DATA_CACHE_LINE_32B
bool "32 Bytes"
config ESP32S3_DATA_CACHE_LINE_64B
bool "64 Bytes"
endchoice
config ESP32S3_DATA_CACHE_LINE_SIZE
int
default 16 if ESP32S3_DATA_CACHE_LINE_16B
default 32 if ESP32S3_DATA_CACHE_LINE_32B
default 64 if ESP32S3_DATA_CACHE_LINE_64B
config ESP32S3_DATA_CACHE_WRAP
bool ## TODO IDF-4307
default "n"
depends on !SPIRAM_ECC_ENABLE
help
If enabled, data cache will use wrap mode to read spi flash or spi ram.
The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE.
However, it depends on complex conditions.
endmenu # Cache config
# Hint: to support SPIRAM across multiple chips, check CONFIG_SPIRAM instead
config ESP32S3_SPIRAM_SUPPORT
bool "Support for external, SPI-connected RAM"
default "n"
select SPIRAM
help
This enables support for an external SPI RAM chip, connected in parallel with the
main SPI flash chip.
menu "SPI RAM config"
depends on ESP32S3_SPIRAM_SUPPORT
config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
bool
default "y"
choice SPIRAM_MODE
prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
default SPIRAM_MODE_QUAD
config SPIRAM_MODE_QUAD
bool "Quad Mode PSRAM"
config SPIRAM_MODE_OCT
bool "Octal Mode PSRAM"
endchoice
choice SPIRAM_TYPE
prompt "Type of SPIRAM chip in use"
default SPIRAM_TYPE_AUTO
config SPIRAM_TYPE_AUTO
bool "Auto-detect"
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
depends on SPIRAM_MODE_QUAD
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32"
depends on SPIRAM_MODE_QUAD
config SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 , LY68L6400 or APS6408"
endchoice
config SPIRAM_SIZE
int
default -1 if SPIRAM_TYPE_AUTO
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 16777216 if SPIRAM_TYPE_ESPPSRAM128
default 33554432 if SPIRAM_TYPE_ESPPSRAM256
default 0
menu "PSRAM Clock and CS IO for ESP32S3"
depends on ESP32S3_SPIRAM_SUPPORT
config DEFAULT_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 30
help
The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design.
config DEFAULT_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 26
help
The PSRAM CS IO can be any unused GPIO, please refer to your hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM"
default n
help
If enabled, instruction in flash will be copied into SPIRAM.
If SPIRAM_RODATA also enabled, you can run the instruction when erasing or programming the flash.
config SPIRAM_RODATA
bool "Cache load read only data from SPI RAM"
default n
help
If enabled, rodata in flash will be copied into SPIRAM.
If SPIRAM_FETCH_INSTRUCTIONS is also enabled,
you can run the instruction when erasing or programming the flash.
choice SPIRAM_SPEED
prompt "Set RAM clock speed"
default SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
config SPIRAM_SPEED_120M
depends on SPIRAM_MODE_QUAD
bool "120MHz clock speed"
config SPIRAM_SPEED_80M
bool "80MHz clock speed"
config SPIRAM_SPEED_40M
bool "40Mhz clock speed"
endchoice
config SPIRAM_SPEED
int
default 120 if SPIRAM_SPEED_120M
default 80 if SPIRAM_SPEED_80M
default 40 if SPIRAM_SPEED_40M
source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common" # insert non-chip-specific items here
endmenu
config ESP32S3_MEMMAP_TRACEMEM
bool
default "n"
config ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
bool
default "n"
config ESP32S3_TRAX
bool "Use TRAX tracing feature"
default "n"
select ESP32S3_MEMMAP_TRACEMEM
help
The esp32-s3 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config ESP32S3_TRAX_TWOBANKS
bool "Reserve memory for tracing both pro as well as app cpu execution"
default "n"
depends on ESP32S3_TRAX && !FREERTOS_UNICORE
select ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
help
The esp32-s3 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config ESP32S3_TRACEMEM_RESERVE_DRAM
hex
default 0x8000 if ESP32S3_MEMMAP_TRACEMEM && ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
default 0x4000 if ESP32S3_MEMMAP_TRACEMEM && !ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
default 0x0
config ESP32S3_DEEP_SLEEP_WAKEUP_DELAY
int "Extra delay in deep sleep wake stub (in us)"
default 2000
range 0 5000
help
When ESP32S3 exits deep sleep, the CPU and the flash chip are powered on
at the same time. CPU will run deep sleep stub first, and then
proceed to load code from flash. Some flash chips need sufficient
time to pass between power on and first read operation. By default,
without any extra delay, this time is approximately 900us, although
some flash chip types need more than that.
By default extra delay is set to 2000us. When optimizing startup time
for applications which require it, this value may be reduced.
If you are seeing "flash read err, 1000" message printed to the
console after deep sleep reset, try increasing this value.
config ESP32S3_RTCDATA_IN_FAST_MEM
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
default n
help
This option allows to place .rtc_data and .rtc_rodata sections into
RTC fast memory segment to free the slow memory region for ULP programs.
config ESP32S3_USE_FIXED_STATIC_RAM_SIZE
bool "Use fixed static RAM size"
default n
help
If this option is disabled, the DRAM part of the heap starts right after the .bss section,
within the dram0_0 region. As a result, adding or removing some static variables
will change the available heap size.
If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
where its length is set with ESP32S3_FIXED_STATIC_RAM_SIZE
config ESP32S3_FIXED_STATIC_RAM_SIZE
hex "Fixed Static RAM size"
default 0x10000
range 0 0x34000
depends on ESP32S3_USE_FIXED_STATIC_RAM_SIZE
help
RAM size dedicated for static variables (.data & .bss sections).
endmenu # ESP32S3-Specific

22
components/esp_hw_support/Kconfig
View File

@ -1,4 +1,6 @@
menu "Hardware Settings"
orsource "./port/$IDF_TARGET/Kconfig.spiram"
menu "MAC Config"
config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
bool
@ -69,6 +71,26 @@ menu "Hardware Settings"
increase during light sleep. If the CS pin of Flash has an external
pull-up, you do not need to select this option, otherwise, you
should enable this option.
config ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY
int "Extra delay in deep sleep wake stub (in us)"
depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
default 2000
range 0 5000
help
When the chip exits deep sleep, the CPU and the flash chip are powered on
at the same time. CPU will run deep sleep stub first, and then
proceed to load code from flash. Some flash chips need sufficient
time to pass between power on and first read operation. By default,
without any extra delay, this time is approximately 900us, although
some flash chip types need more than that.
By default extra delay is set to 2000us. When optimizing startup time
for applications which require it, this value may be reduced.
If you are seeing "flash read err, 1000" message printed to the
console after deep sleep reset, try increasing this value.
endmenu
menu "RTC Clock Config"

6
components/esp_hw_support/Kconfig.spiram.common
View File

@ -1,10 +1,6 @@
# Common (non-chip-specific) SPIRAM options
#
# sourced into the "SPIRAM config" submenu for ESP32 or ESP32S2
# invisible option selected by ${target}_SPIRAM_SUPPORT
config SPIRAM
bool
# sourced into the "SPIRAM config" submenu for a specific chip.
config SPIRAM_BOOT_INIT
bool "Initialize SPI RAM during startup"

6
components/esp_hw_support/include/spinlock.h
View File

@ -37,7 +37,7 @@ typedef struct {
NEED_VOLATILE_MUX uint32_t count;
}spinlock_t;
#if (CONFIG_ESP32_SPIRAM_SUPPORT)
#if (CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32)
/**
* @brief Check if the pointer is on external ram
* @param p pointer
@ -108,13 +108,13 @@ static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *l
*/
result = core_id;
#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
#if (CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32)
if (spinlock_ptr_external_ram(lock)) {
compare_and_set_extram(&lock->owner, SPINLOCK_FREE, &result);
} else {
#endif
compare_and_set_native(&lock->owner, SPINLOCK_FREE, &result);
#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
#if (CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32)
}
#endif
if(result != other_core_id) {

41
components/esp_hw_support/port/esp32/Kconfig.hw_support
View File

@ -22,3 +22,44 @@ config ESP32_REV_MIN
default 1 if ESP32_REV_MIN_1
default 2 if ESP32_REV_MIN_2
default 3 if ESP32_REV_MIN_3
config ESP32_DPORT_WORKAROUND
bool
default "y" if !FREERTOS_UNICORE && ESP32_REV_MIN < 2
config ESP32_DPORT_DIS_INTERRUPT_LVL
int "Disable the interrupt level for the DPORT workarounds"
default 5
help
To prevent interrupting DPORT workarounds,
need to disable interrupt with a maximum used level in the system.
choice ESP32_XTAL_FREQ_SEL
prompt "Main XTAL frequency"
default ESP32_XTAL_FREQ_40
help
ESP32 currently supports the following XTAL frequencies:
- 26 MHz
- 40 MHz
Startup code can automatically estimate XTAL frequency. This feature
uses the internal 8MHz oscillator as a reference. Because the internal
oscillator frequency is temperature dependent, it is not recommended
to use automatic XTAL frequency detection in applications which need
to work at high ambient temperatures and use high-temperature
qualified chips and modules.
config ESP32_XTAL_FREQ_40
bool "40 MHz"
config ESP32_XTAL_FREQ_26
bool "26 MHz"
config ESP32_XTAL_FREQ_AUTO
bool "Autodetect"
endchoice
# Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h
config ESP32_XTAL_FREQ
int
default 0 if ESP32_XTAL_FREQ_AUTO
default 40 if ESP32_XTAL_FREQ_40
default 26 if ESP32_XTAL_FREQ_26

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config SPIRAM
bool "Support for external, SPI-connected RAM"
default "n"
help
This enables support for an external SPI RAM chip, connected in parallel with the
main SPI flash chip.
menu "SPI RAM config"
depends on SPIRAM
config SPIRAM_MODE_QUAD
bool
default "y"
choice SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
default SPIRAM_TYPE_AUTO
config SPIRAM_TYPE_AUTO
bool "Auto-detect"
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32"
config SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 or LY68L6400"
endchoice
config SPIRAM_SIZE
int
default -1 if SPIRAM_TYPE_AUTO
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0
choice SPIRAM_SPEED
prompt "Set RAM clock speed"
default SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz
Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
will be occupied by the system. Which SPI host to use can be selected by the config item
SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
(ESPTOOLPY_FLASHFREQ_80M is true)
config SPIRAM_SPEED_40M
bool "40MHz clock speed"
config SPIRAM_SPEED_80M
depends on ESPTOOLPY_FLASHFREQ_80M
bool "80MHz clock speed"
endchoice
# insert non-chip-specific items here
source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common"
config SPIRAM_CACHE_WORKAROUND
bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
default "y"
help
Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a
fix in the compiler (-mfix-esp32-psram-cache-issue) that makes sure the specific code that is
vulnerable to this will not be emitted.
This will also not use any bits of newlib that are located in ROM, opting for a version that is
compiled with the workaround and located in flash instead.
The workaround is not required for ESP32 revision 3 and above.
menu "SPIRAM cache workaround debugging"
choice SPIRAM_CACHE_WORKAROUND_STRATEGY
prompt "Workaround strategy"
depends on SPIRAM_CACHE_WORKAROUND
default SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
help
Select the workaround strategy. Note that the strategy for precompiled
libraries (libgcc, newlib, bt, wifi) is not affected by this selection.
Unless you know you need a different strategy, it's suggested you stay
with the default MEMW strategy. Note that DUPLDST can interfere with hardware
encryption and this will be automatically disabled if this workaround is selected.
'Insert nops' is the workaround that was used in older esp-idf versions. This workaround
still can cause faulty data transfers from/to SPI RAM in some situation.
config SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
bool "Insert memw after vulnerable instructions (default)"
config SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
bool "Duplicate LD/ST for 32-bit, memw for 8/16 bit"
config SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS
bool "Insert nops between vulnerable loads/stores (old strategy, obsolete)"
endchoice
#This needs to be Y only for the dupldst workaround
config SPIRAM_WORKAROUND_NEED_VOLATILE_SPINLOCK
bool
default "y" if SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
endmenu
menu "SPIRAM workaround libraries placement"
visible if SPIRAM_CACHE_WORKAROUND
config SPIRAM_CACHE_LIBJMP_IN_IRAM
bool "Put libc's jump related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: longjmp and setjmp.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBMATH_IN_IRAM
bool "Put libc's math related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: abs, div, labs, ldiv, quorem, fpclassify,
and nan.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM
bool "Put libc's number parsing related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: utoa, itoa, atoi, atol, strtol, and strtoul.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBIO_IN_IRAM
bool "Put libc's I/O related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: wcrtomb, fvwrite, wbuf, wsetup, fputwc, wctomb_r,
ungetc, makebuf, fflush, refill, and sccl.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBTIME_IN_IRAM
bool "Put libc's time related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: asctime, asctime_r, ctime, ctime_r, lcltime, lcltime_r,
gmtime, gmtime_r, strftime, mktime, tzset_r, tzset, time, gettzinfo, systimes, month_lengths,
timelocal, tzvars, tzlock, tzcalc_limits, and strptime.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBCHAR_IN_IRAM
bool "Put libc's characters related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: ctype_, toupper, tolower, toascii, strupr, bzero,
isalnum, isalpha, isascii, isblank, iscntrl, isdigit, isgraph, islower, isprint, ispunct,
isspace, and isupper.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBMEM_IN_IRAM
bool "Put libc's memory related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: memccpy, memchr memmove, and memrchr.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBSTR_IN_IRAM
bool "Put libc's string related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: strcasecmp, strcasestr, strchr, strcoll,
strcpy, strcspn, strdup, strdup_r, strlcat, strlcpy, strlen, strlwr, strncasecmp,
strncat, strncmp, strncpy, strndup, strndup_r, strrchr, strsep, strspn, strstr,
strtok_r, and strupr.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBRAND_IN_IRAM
bool "Put libc's random related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: srand, rand, and rand_r.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBENV_IN_IRAM
bool "Put libc's environment related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: environ, envlock, and getenv_r.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBFILE_IN_IRAM
bool "Put libc's file related functions in IRAM"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: lock, isatty, fclose, open, close, creat, read,
rshift, sbrk, stdio, syssbrk, sysclose, sysopen, creat, sysread, syswrite, impure, fwalk,
and findfp.
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
config SPIRAM_CACHE_LIBMISC_IN_IRAM
bool "Put libc's miscellaneous functions in IRAM, see help"
depends on SPIRAM_CACHE_WORKAROUND
default "y"
help
The functions affected by this option are: raise and system
Putting these function in IRAM will allow them to be called when flash cache is disabled
but it will also reduce the available size of free IRAM for the user application.
endmenu
config SPIRAM_BANKSWITCH_ENABLE
bool "Enable bank switching for >4MiB external RAM"
default y
depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
help
The ESP32 only supports 4MiB of external RAM in its address space. The hardware does support larger
memories, but these have to be bank-switched in and out of this address space. Enabling this allows you
to reserve some MMU pages for this, which allows the use of the esp_himem api to manage these banks.
#Note that this is limited to 62 banks, as esp_spiram_writeback_cache needs some kind of mapping of
#some banks below that mark to work. We cannot at this moment guarantee this to exist when himem is
#enabled.
If spiram 2T mode is enabled, the size of 64Mbit psram will be changed as 32Mbit, so himem will be
unusable.
config SPIRAM_BANKSWITCH_RESERVE
int "Amount of 32K pages to reserve for bank switching"
depends on SPIRAM_BANKSWITCH_ENABLE
default 8
range 1 62
help
Select the amount of banks reserved for bank switching. Note that the amount of RAM allocatable with
malloc/esp_heap_alloc_caps will decrease by 32K for each page reserved here.
Note that this reservation is only actually done if your program actually uses the himem API. Without
any himem calls, the reservation is not done and the original amount of memory will be available
to malloc/esp_heap_alloc_caps.
config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
bool "Allow external memory as an argument to xTaskCreateStatic"
default n
depends on SPIRAM_USE_MALLOC
help
Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround,
normally tasks cannot be safely run with their stack residing in external memory; for this reason
xTaskCreate (and related task creaton functions) always allocate stack in internal memory and
xTaskCreateStatic will check if the memory passed to it is in internal memory. If you have a task that
needs a large amount of stack and does not call on ROM code in any way (no direct calls, but also no
Bluetooth/WiFi), you can try enable this to cause xTaskCreateStatic to allow tasks stack in external
memory.
choice SPIRAM_OCCUPY_SPI_HOST
prompt "SPI host to use for 32MBit PSRAM"
default SPIRAM_OCCUPY_VSPI_HOST
depends on SPIRAM_SPEED_80M
help
When both flash and PSRAM is working under 80MHz, and the PSRAM is of type 32MBit, one of the HSPI/VSPI
host will be used to output the clock. Select which one to use here.
config SPIRAM_OCCUPY_HSPI_HOST
bool "HSPI host (SPI2)"
config SPIRAM_OCCUPY_VSPI_HOST
bool "VSPI host (SPI3)"
config SPIRAM_OCCUPY_NO_HOST
bool "Will not try to use any host, will abort if not able to use the PSRAM"
endchoice
menu "PSRAM clock and cs IO for ESP32-DOWD"
config D0WD_PSRAM_CLK_IO
int "PSRAM CLK IO number"
depends on SPIRAM
range 0 33
default 17
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
config D0WD_PSRAM_CS_IO
int "PSRAM CS IO number"
depends on SPIRAM
range 0 33
default 16
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu
menu "PSRAM clock and cs IO for ESP32-D2WD"
config D2WD_PSRAM_CLK_IO
int "PSRAM CLK IO number"
depends on SPIRAM
range 0 33
default 9
help
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
config D2WD_PSRAM_CS_IO
int "PSRAM CS IO number"
depends on SPIRAM
range 0 33
default 10
help
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu
menu "PSRAM clock and cs IO for ESP32-PICO"
config PICO_PSRAM_CS_IO
int "PSRAM CS IO number"
depends on SPIRAM
range 0 33
default 10
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
IO.
For the reference hardware design, please refer to
https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
endmenu
config SPIRAM_CUSTOM_SPIWP_SD3_PIN
bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
default n
help
This setting is only used if the SPI flash pins have been overridden by setting the eFuses
SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
mode, so a WP pin setting is necessary.
If this config item is set to N (default), the correct WP pin will be automatically used for any
Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
to Y and specify the GPIO number connected to the WP pin.
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
configured in the bootloader.
config SPIRAM_SPIWP_SD3_PIN
int "Custom SPI PSRAM WP(SD3) Pin"
depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
#depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN # backwards compatibility, can uncomment in IDF 5
range 0 33
default 7
help
The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
value to the GPIO number of the SPIRAM WP pin.
config SPIRAM_2T_MODE
bool "Enable SPI PSRAM 2T mode"
depends on SPIRAM
default "n"
help
Enable this option to fix single bit errors inside 64Mbit PSRAM.
Some 64Mbit PSRAM chips have a hardware issue in the RAM which causes bit errors at multiple
fixed bit positions.
Note: If this option is enabled, the 64Mbit PSRAM chip will appear to be 32Mbit in size.
Applications will not be affected unless the use the esp_himem APIs, which are not supported
in 2T mode.
endmenu # "SPI RAM config"

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config SPIRAM
bool "Support for external, SPI-connected RAM"
default "n"
help
This enables support for an external SPI RAM chip, connected in parallel with the
main SPI flash chip.
menu "SPI RAM config"
depends on SPIRAM
config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
bool
default "y"
config SPIRAM_MODE_QUAD
bool
default "y"
choice SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
default SPIRAM_TYPE_AUTO
config SPIRAM_TYPE_AUTO
bool "Auto-detect"
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32"
config SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 or LY68L6400"
endchoice
config SPIRAM_SIZE
int
default -1 if SPIRAM_TYPE_AUTO
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0
menu "PSRAM clock and cs IO for ESP32S2"
depends on SPIRAM
config DEFAULT_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 30
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design.
config DEFAULT_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 26
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM"
default n
help
If enabled, instruction in flash will be copied into SPIRAM.
If SPIRAM_RODATA also enabled,
you can run the instruction when erasing or programming the flash.
config SPIRAM_RODATA
bool "Cache load read only data from SPI RAM"
default n
help
If enabled, radata in flash will be copied into SPIRAM.
If SPIRAM_FETCH_INSTRUCTIONS also enabled,
you can run the instruction when erasing or programming the flash.
choice SPIRAM_SPEED
prompt "Set RAM clock speed"
default SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
config SPIRAM_SPEED_80M
bool "80MHz clock speed"
config SPIRAM_SPEED_40M
bool "40Mhz clock speed"
config SPIRAM_SPEED_26M
bool "26Mhz clock speed"
config SPIRAM_SPEED_20M
bool "20Mhz clock speed"
endchoice
config SPIRAM_SPEED
int
default 80 if SPIRAM_SPEED_80M
default 40 if SPIRAM_SPEED_40M
default 40 if SPIRAM_SPEED_26M
default 40 if SPIRAM_SPEED_20M
source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common" #insert non-chip-specific items here
endmenu

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config SPIRAM
bool "Support for external, SPI-connected RAM"
default "n"
help
This enables support for an external SPI RAM chip, connected in parallel with the
main SPI flash chip.
menu "SPI RAM config"
depends on SPIRAM
config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
bool
default "y"
choice SPIRAM_MODE
prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
default SPIRAM_MODE_QUAD
config SPIRAM_MODE_QUAD
bool "Quad Mode PSRAM"
config SPIRAM_MODE_OCT
bool "Octal Mode PSRAM"
endchoice
choice SPIRAM_TYPE
prompt "Type of SPIRAM chip in use"
default SPIRAM_TYPE_AUTO
config SPIRAM_TYPE_AUTO
bool "Auto-detect"
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
depends on SPIRAM_MODE_QUAD
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32"
depends on SPIRAM_MODE_QUAD
config SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 , LY68L6400 or APS6408"
endchoice
config SPIRAM_SIZE
int
default -1 if SPIRAM_TYPE_AUTO
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 16777216 if SPIRAM_TYPE_ESPPSRAM128
default 33554432 if SPIRAM_TYPE_ESPPSRAM256
default 0
menu "PSRAM Clock and CS IO for ESP32S3"
depends on SPIRAM
config DEFAULT_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 30
help
The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design.
config DEFAULT_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 26
help
The PSRAM CS IO can be any unused GPIO, please refer to your hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM"
default n
help
If enabled, instruction in flash will be copied into SPIRAM.
If SPIRAM_RODATA also enabled, you can run the instruction when erasing or programming the flash.
config SPIRAM_RODATA
bool "Cache load read only data from SPI RAM"
default n
help
If enabled, rodata in flash will be copied into SPIRAM.
If SPIRAM_FETCH_INSTRUCTIONS is also enabled,
you can run the instruction when erasing or programming the flash.
choice SPIRAM_SPEED
prompt "Set RAM clock speed"
default SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
config SPIRAM_SPEED_120M
depends on SPIRAM_MODE_QUAD
bool "120MHz clock speed"
config SPIRAM_SPEED_80M
bool "80MHz clock speed"
config SPIRAM_SPEED_40M
bool "40Mhz clock speed"
endchoice
config SPIRAM_SPEED
int
default 120 if SPIRAM_SPEED_120M
default 80 if SPIRAM_SPEED_80M
default 40 if SPIRAM_SPEED_40M
source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common" # insert non-chip-specific items here
endmenu

6
components/esp_hw_support/sdkconfig.rename.esp32
View File

@ -16,3 +16,9 @@ CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC CONFIG_RTC_CLK_SRC_INT_R
CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL CONFIG_RTC_CLK_SRC_EXT_CRYS
CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC CONFIG_RTC_CLK_SRC_EXT_OSC
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 CONFIG_RTC_CLK_SRC_INT_8MD256
CONFIG_SPIRAM_SUPPORT CONFIG_SPIRAM
CONFIG_ESP32_SPIRAM_SUPPORT CONFIG_SPIRAM
CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY

2
components/esp_hw_support/sdkconfig.rename.esp32s2
View File

@ -7,3 +7,5 @@ CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC CONFIG_RTC_CLK_SRC_EXT
CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 CONFIG_RTC_CLK_SRC_INT_8MD256
CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
CONFIG_ESP32S2_RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RETRY
CONFIG_ESP32S2_SPIRAM_SUPPORT CONFIG_SPIRAM

4
components/esp_hw_support/sdkconfig.rename.esp32s3
View File

@ -7,3 +7,7 @@ CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC CONFIG_RTC_CLK_SRC_EXT
CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 CONFIG_RTC_CLK_SRC_INT_8MD256
CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
CONFIG_ESP32S3_RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RETRY
CONFIG_ESP32S3_SPIRAM_SUPPORT CONFIG_SPIRAM
CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY

6
components/esp_hw_support/sleep_modes.c
View File

@ -112,10 +112,8 @@
#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
#endif
#if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY)
#define DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY
#elif defined(CONFIG_IDF_TARGET_ESP32S3) && defined(CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY)
#define DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY
#if CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY
#define DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY
#else
#define DEEP_SLEEP_WAKEUP_DELAY 0
#endif

2
components/esp_hw_support/sleep_retention.c
View File

@ -110,7 +110,7 @@ static esp_err_t esp_sleep_tagmem_pd_low_init(bool enable)
extern char _stext[], _etext[];
uint32_t code_start = (uint32_t)_stext;
uint32_t code_size = (uint32_t)(_etext - _stext);
#if !CONFIG_ESP32S3_SPIRAM_SUPPORT
#if !(CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32S3)
extern char _rodata_start[], _rodata_reserved_end[];
uint32_t data_start = (uint32_t)_rodata_start;
uint32_t data_size = (uint32_t)(_rodata_reserved_end - _rodata_start);

2
components/esp_lcd/test_apps/rgb_lcd/sdkconfig.defaults.esp32s3
View File

@ -1,3 +1,3 @@
CONFIG_ESP32S3_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_MODE_OCT=y
CONFIG_SPIRAM_SPEED_80M=y

10
components/esp_system/Kconfig
View File

@ -3,6 +3,12 @@ menu "ESP System Settings"
# Insert chip-specific cpu config
rsource "./port/soc/$IDF_TARGET/Kconfig.cpu"
orsource "./port/soc/$IDF_TARGET/Kconfig.cache"
orsource "./port/soc/$IDF_TARGET/Kconfig.memory"
orsource "./port/soc/$IDF_TARGET/Kconfig.tracemem"
choice ESP_SYSTEM_PANIC
prompt "Panic handler behaviour"
default ESP_SYSTEM_PANIC_PRINT_REBOOT
@ -377,8 +383,8 @@ menu "ESP System Settings"
config ESP_INT_WDT_TIMEOUT_MS
int "Interrupt watchdog timeout (ms)"
depends on ESP_INT_WDT
default 300 if !ESP32_SPIRAM_SUPPORT
default 800 if ESP32_SPIRAM_SUPPORT
default 300 if !(SPIRAM && IDF_TARGET_ESP32)
default 800 if (SPIRAM && IDF_TARGET_ESP32)
range 10 10000
help
The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.

44
components/esp_system/port/soc/esp32/Kconfig.memory Normal file
View File

@ -0,0 +1,44 @@
menu "Memory"
config ESP32_RTCDATA_IN_FAST_MEM
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
default n
depends on FREERTOS_UNICORE
help
This option allows to place .rtc_data and .rtc_rodata sections into
RTC fast memory segment to free the slow memory region for ULP programs.
This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory
can be accessed only by PRO_CPU core.
config ESP32_USE_FIXED_STATIC_RAM_SIZE
bool "Use fixed static RAM size"
default n
help
If this option is disabled, the DRAM part of the heap starts right after the .bss section,
within the dram0_0 region. As a result, adding or removing some static variables
will change the available heap size.
If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
where its length is set with ESP32_FIXED_STATIC_RAM_SIZE
config ESP32_FIXED_STATIC_RAM_SIZE
hex "Fixed Static RAM size"
default 0x1E000
range 0 0x2c200
depends on ESP32_USE_FIXED_STATIC_RAM_SIZE
help
RAM size dedicated for static variables (.data & .bss sections).
Please note that the actual length will be reduced by BTDM_RESERVE_DRAM if Bluetooth
controller is enabled.
config ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
bool "Enable IRAM as 8 bit accessible memory"
depends on FREERTOS_UNICORE
help
If enabled, application can use IRAM as byte accessible region for storing data
(Note: IRAM region cannot be used as task stack)
This is possible due to handling of exceptions `LoadStoreError (3)` and `LoadStoreAlignmentError (9)`
Each unaligned read/write access will incur a penalty of maximum of 167 CPU cycles.
endmenu # Memory

17
components/esp_system/port/soc/esp32/Kconfig.system
View File

@ -50,3 +50,20 @@ menu "Brownout Detector"
default 7 if ESP_BROWNOUT_DET_LVL_SEL_7
endmenu
config ESP32_DISABLE_BASIC_ROM_CONSOLE
bool "Permanently disable BASIC ROM Console"
default n
help
If set, the first time the app boots it will disable the BASIC ROM Console
permanently (by burning an eFuse).
Otherwise, the BASIC ROM Console starts on reset if no valid bootloader is
read from the flash.
(Enabling secure boot also disables the BASIC ROM Console by default.)
config ESP32_ECO3_CACHE_LOCK_FIX
bool
default y
depends on !FREERTOS_UNICORE && SPIRAM

39
components/esp_system/port/soc/esp32/Kconfig.tracemem Normal file
View File

@ -0,0 +1,39 @@
menu "Trace memory"
config ESP32_MEMMAP_TRACEMEM
bool
default "n"
config ESP32_MEMMAP_TRACEMEM_TWOBANKS
bool
default "n"
config ESP32_TRAX
bool "Use TRAX tracing feature"
default "n"
select ESP32_MEMMAP_TRACEMEM
help
The ESP32 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config ESP32_TRAX_TWOBANKS
bool "Reserve memory for tracing both pro as well as app cpu execution"
default "n"
depends on ESP32_TRAX && !FREERTOS_UNICORE
select ESP32_MEMMAP_TRACEMEM_TWOBANKS
help
The ESP32 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
# Memory to reverse for trace, used in linker script
config ESP32_TRACEMEM_RESERVE_DRAM
hex
default 0x8000 if ESP32_MEMMAP_TRACEMEM && ESP32_MEMMAP_TRACEMEM_TWOBANKS
default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS
default 0x0
endmenu # Trace memory

4
components/esp_system/port/soc/esp32/clk.c
View File

@ -117,7 +117,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
rtc_init(cfg);
#if (CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS || CONFIG_ESP32_APP_INIT_CLK)
#if (CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS || CONFIG_APP_INIT_CLK)
/* Check the bootloader set the XTAL frequency.
Bootloaders pre-v2.1 don't do this.
@ -128,7 +128,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
bootloader_clock_configure();
}
#else
/* If this assertion fails, either upgrade the bootloader or enable CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
/* If this assertion fails, either upgrade the bootloader or enable CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
#endif

33
components/esp_system/port/soc/esp32c2/Kconfig.cache Normal file
View File

@ -0,0 +1,33 @@
menu "Cache config"
choice ESP32C2_MMU_PAGE_SIZE
# TODO: IDF-3821
prompt "Cache page size"
default ESP32C2_MMU_PAGE_SIZE_64KB
help
Cache page size to be set on application startup
config ESP32C2_MMU_PAGE_SIZE_16KB
bool "16KB"
config ESP32C2_MMU_PAGE_SIZE_32KB
bool "32KB"
config ESP32C2_MMU_PAGE_SIZE_64KB
bool "64KB"
endchoice
config ESP32C2_INSTRUCTION_CACHE_WRAP
# TODO: IDF-4194
bool
prompt "Instruction cache wrap"
help
If enabled, instruction cache will use wrap mode to read spi flash.
The wrap length is fixed to 32B
config ESP32C2_MMU_PAGE_MODE
int
default 0 if ESP32C2_MMU_PAGE_SIZE_16KB
default 1 if ESP32C2_MMU_PAGE_SIZE_32KB
default 2 if ESP32C2_MMU_PAGE_SIZE_64KB
endmenu

75
components/esp_system/port/soc/esp32s2/Kconfig.cache Normal file
View File

@ -0,0 +1,75 @@
menu "Cache config"
choice ESP32S2_INSTRUCTION_CACHE_SIZE
prompt "Instruction cache size"
default ESP32S2_INSTRUCTION_CACHE_8KB
help
Instruction cache size to be set on application startup.
If you use 8KB instruction cache rather than 16KB instruction cache,
then the other 8KB will be added to the heap.
config ESP32S2_INSTRUCTION_CACHE_8KB
bool "8KB"
config ESP32S2_INSTRUCTION_CACHE_16KB
bool "16KB"
endchoice
choice ESP32S2_INSTRUCTION_CACHE_LINE_SIZE
prompt "Instruction cache line size"
default ESP32S2_INSTRUCTION_CACHE_LINE_32B
help
Instruction cache line size to be set on application startup.
config ESP32S2_INSTRUCTION_CACHE_LINE_16B
bool "16 Bytes"
config ESP32S2_INSTRUCTION_CACHE_LINE_32B
bool "32 Bytes"
endchoice
choice ESP32S2_DATA_CACHE_SIZE
prompt "Data cache size"
default ESP32S2_DATA_CACHE_0KB if !SPIRAM
default ESP32S2_DATA_CACHE_8KB if SPIRAM
help
Data cache size to be set on application startup.
If you use 0KB data cache, the other 16KB will be added to the heap
If you use 8KB data cache rather than 16KB data cache, the other 8KB will be added to the heap
config ESP32S2_DATA_CACHE_0KB
depends on !SPIRAM
bool "0KB"
config ESP32S2_DATA_CACHE_8KB
bool "8KB"
config ESP32S2_DATA_CACHE_16KB
bool "16KB"
endchoice
choice ESP32S2_DATA_CACHE_LINE_SIZE
prompt "Data cache line size"
default ESP32S2_DATA_CACHE_LINE_32B
help
Data cache line size to be set on application startup.
config ESP32S2_DATA_CACHE_LINE_16B
bool "16 Bytes"
config ESP32S2_DATA_CACHE_LINE_32B
bool "32 Bytes"
endchoice
config ESP32S2_INSTRUCTION_CACHE_WRAP
bool "Enable instruction cache wrap"
default "n"
help
If enabled, instruction cache will use wrap mode to read spi flash (maybe spiram).
The wrap length equals to INSTRUCTION_CACHE_LINE_SIZE.
However, it depends on complex conditions.
config ESP32S2_DATA_CACHE_WRAP
bool "Enable data cache wrap"
default "n"
help
If enabled, data cache will use wrap mode to read spiram (maybe spi flash).
The wrap length equals to DATA_CACHE_LINE_SIZE.
However, it depends on complex conditions.
endmenu # Cache config

29
components/esp_system/port/soc/esp32s2/Kconfig.memory Normal file
View File

@ -0,0 +1,29 @@
menu "Memory"
config ESP32S2_RTCDATA_IN_FAST_MEM
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
default n
help
This option allows to place .rtc_data and .rtc_rodata sections into
RTC fast memory segment to free the slow memory region for ULP programs.
config ESP32S2_USE_FIXED_STATIC_RAM_SIZE
bool "Use fixed static RAM size"
default n
help
If this option is disabled, the DRAM part of the heap starts right after the .bss section,
within the dram0_0 region. As a result, adding or removing some static variables
will change the available heap size.
If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
where its length is set with ESP32S2_FIXED_STATIC_RAM_SIZE
config ESP32S2_FIXED_STATIC_RAM_SIZE
hex "Fixed Static RAM size"
default 0x10000
range 0 0x34000
depends on ESP32S2_USE_FIXED_STATIC_RAM_SIZE
help
RAM size dedicated for static variables (.data & .bss sections).
endmenu # Memory

8
components/esp_system/port/soc/esp32s2/Kconfig.system
View File

@ -47,3 +47,11 @@ menu "Brownout Detector"
default 7 if ESP_BROWNOUT_DET_LVL_SEL_7
endmenu
config ESP32S2_KEEP_USB_ALIVE
bool "Keep USB peripheral enabled at start up" if !ESP_CONSOLE_USB_CDC
default y if ESP_CONSOLE_USB_CDC
help
During the application initialization process, all the peripherals except UARTs and timers
are reset. Enable this option to keep USB peripheral enabled.
This option is automatically enabled if "USB CDC" console is selected.

27
components/esp_system/port/soc/esp32s2/Kconfig.tracemem Normal file
View File

@ -0,0 +1,27 @@
menu "Trace memory"
config ESP32S2_MEMMAP_TRACEMEM
bool
default "n"
config ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
bool
default "n"
config ESP32S2_TRAX
bool "Use TRAX tracing feature"
default "n"
select ESP32S2_MEMMAP_TRACEMEM
help
The ESP32S2 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config ESP32S2_TRACEMEM_RESERVE_DRAM
hex
default 0x8000 if ESP32S2_MEMMAP_TRACEMEM && ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
default 0x4000 if ESP32S2_MEMMAP_TRACEMEM && !ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
default 0x0
endmenu # Trace memory

136
components/esp_system/port/soc/esp32s3/Kconfig.cache Normal file
View File

@ -0,0 +1,136 @@
menu "Cache config"
choice ESP32S3_INSTRUCTION_CACHE_SIZE
prompt "Instruction cache size"
default ESP32S3_INSTRUCTION_CACHE_16KB
help
Instruction cache size to be set on application startup.
If you use 16KB instruction cache rather than 32KB instruction cache,
then the other 16KB will be managed by heap allocator.
config ESP32S3_INSTRUCTION_CACHE_16KB
bool "16KB"
config ESP32S3_INSTRUCTION_CACHE_32KB
bool "32KB"
endchoice
config ESP32S3_INSTRUCTION_CACHE_SIZE
hex
default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB
default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB
choice ESP32S3_ICACHE_ASSOCIATED_WAYS
prompt "Instruction cache associated ways"
default ESP32S3_INSTRUCTION_CACHE_8WAYS
help
Instruction cache associated ways to be set on application startup.
config ESP32S3_INSTRUCTION_CACHE_4WAYS
bool "4 ways"
config ESP32S3_INSTRUCTION_CACHE_8WAYS
bool "8 ways"
endchoice
config ESP32S3_ICACHE_ASSOCIATED_WAYS
int
default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS
default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS
choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
prompt "Instruction cache line size"
default ESP32S3_INSTRUCTION_CACHE_LINE_32B
help
Instruction cache line size to be set on application startup.
config ESP32S3_INSTRUCTION_CACHE_LINE_16B
bool "16 Bytes"
depends on ESP32S3_INSTRUCTION_CACHE_16KB
config ESP32S3_INSTRUCTION_CACHE_LINE_32B
bool "32 Bytes"
endchoice
config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
int
default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B
default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B
config ESP32S3_INSTRUCTION_CACHE_WRAP
bool ## TODO IDF-4307
default "n"
depends on !SPIRAM_ECC_ENABLE
help
If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE.
However, it depends on complex conditions.
choice ESP32S3_DATA_CACHE_SIZE
prompt "Data cache size"
default ESP32S3_DATA_CACHE_32KB
help
Data cache size to be set on application startup.
If you use 32KB data cache rather than 64KB data cache,
the other 32KB will be added to the heap.
config ESP32S3_DATA_CACHE_16KB
bool "16KB"
config ESP32S3_DATA_CACHE_32KB
bool "32KB"
config ESP32S3_DATA_CACHE_64KB
bool "64KB"
endchoice
config ESP32S3_DATA_CACHE_SIZE
hex
# For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
default 0x8000 if ESP32S3_DATA_CACHE_16KB
default 0x8000 if ESP32S3_DATA_CACHE_32KB
default 0x10000 if ESP32S3_DATA_CACHE_64KB
choice ESP32S3_DCACHE_ASSOCIATED_WAYS
prompt "Data cache associated ways"
default ESP32S3_DATA_CACHE_8WAYS
help
Data cache associated ways to be set on application startup.
config ESP32S3_DATA_CACHE_4WAYS
bool "4 ways"
config ESP32S3_DATA_CACHE_8WAYS
bool "8 ways"
endchoice
config ESP32S3_DCACHE_ASSOCIATED_WAYS
int
default 4 if ESP32S3_DATA_CACHE_4WAYS
default 8 if ESP32S3_DATA_CACHE_8WAYS
choice ESP32S3_DATA_CACHE_LINE_SIZE
prompt "Data cache line size"
default ESP32S3_DATA_CACHE_LINE_32B
help
Data cache line size to be set on application startup.
config ESP32S3_DATA_CACHE_LINE_16B
bool "16 Bytes"
depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB
config ESP32S3_DATA_CACHE_LINE_32B
bool "32 Bytes"
config ESP32S3_DATA_CACHE_LINE_64B
bool "64 Bytes"
endchoice
config ESP32S3_DATA_CACHE_LINE_SIZE
int
default 16 if ESP32S3_DATA_CACHE_LINE_16B
default 32 if ESP32S3_DATA_CACHE_LINE_32B
default 64 if ESP32S3_DATA_CACHE_LINE_64B
config ESP32S3_DATA_CACHE_WRAP
bool ## TODO IDF-4307
default "n"
depends on !SPIRAM_ECC_ENABLE
help
If enabled, data cache will use wrap mode to read spi flash or spi ram.
The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE.
However, it depends on complex conditions.
endmenu # Cache config

29
components/esp_system/port/soc/esp32s3/Kconfig.memory Normal file
View File

@ -0,0 +1,29 @@
menu "Memory"
config ESP32S3_RTCDATA_IN_FAST_MEM
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
default n
help
This option allows to place .rtc_data and .rtc_rodata sections into
RTC fast memory segment to free the slow memory region for ULP programs.
config ESP32S3_USE_FIXED_STATIC_RAM_SIZE
bool "Use fixed static RAM size"
default n
help
If this option is disabled, the DRAM part of the heap starts right after the .bss section,
within the dram0_0 region. As a result, adding or removing some static variables
will change the available heap size.
If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
where its length is set with ESP32S3_FIXED_STATIC_RAM_SIZE
config ESP32S3_FIXED_STATIC_RAM_SIZE
hex "Fixed Static RAM size"
default 0x10000
range 0 0x34000
depends on ESP32S3_USE_FIXED_STATIC_RAM_SIZE
help
RAM size dedicated for static variables (.data & .bss sections).
endmenu # Memory

38
components/esp_system/port/soc/esp32s3/Kconfig.tracemem Normal file
View File

@ -0,0 +1,38 @@
menu "Trace memory"
config ESP32S3_MEMMAP_TRACEMEM
bool
default "n"
config ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
bool
default "n"
config ESP32S3_TRAX
bool "Use TRAX tracing feature"
default "n"
select ESP32S3_MEMMAP_TRACEMEM
help
The esp32-s3 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config ESP32S3_TRAX_TWOBANKS
bool "Reserve memory for tracing both pro as well as app cpu execution"
default "n"
depends on ESP32S3_TRAX && !FREERTOS_UNICORE
select ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
help
The esp32-s3 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config ESP32S3_TRACEMEM_RESERVE_DRAM
hex
default 0x8000 if ESP32S3_MEMMAP_TRACEMEM && ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
default 0x4000 if ESP32S3_MEMMAP_TRACEMEM && !ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
default 0x0
endmenu # Trace memory

5
components/esp_system/sdkconfig.rename.esp32
View File

@ -27,3 +27,8 @@ CONFIG_ESP32_DEFAULT_CPU_FREQ_40 CONFIG_ESP_DEFAULT_CPU_F
CONFIG_ESP32_DEFAULT_CPU_FREQ_80 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80
CONFIG_ESP32_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
CONFIG_ESP32_DEFAULT_CPU_FREQ_240 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240
CONFIG_DISABLE_BASIC_ROM_CONSOLE CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
CONFIG_MEMMAP_TRACEMEM CONFIG_ESP32_MEMMAP_TRACEMEM
CONFIG_MEMMAP_TRACEMEM_TWOBANKS CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS
CONFIG_TRACEMEM_RESERVE_DRAM CONFIG_ESP32_TRACEMEM_RESERVE_DRAM

8
components/esp_wifi/Kconfig
View File

@ -98,7 +98,7 @@ menu "Wi-Fi"
config ESP32_WIFI_CACHE_TX_BUFFER_NUM
int "Max number of WiFi cache TX buffers"
depends on (ESP32_SPIRAM_SUPPORT || ESP32S2_SPIRAM_SUPPORT || ESP32S3_SPIRAM_SUPPORT)
depends on SPIRAM
range 16 128
default 32
help
@ -171,7 +171,7 @@ menu "Wi-Fi"
config ESP32_WIFI_AMSDU_TX_ENABLED
bool "WiFi AMSDU TX"
depends on (ESP32_SPIRAM_SUPPORT || ESP32S2_SPIRAM_SUPPORT || ESP32S3_SPIRAM_SUPPORT)
depends on SPIRAM
default n
help
Select this option to enable AMSDU TX feature
@ -226,7 +226,7 @@ menu "Wi-Fi"
config ESP32_WIFI_IRAM_OPT
bool "WiFi IRAM speed optimization"
default n if (BT_ENABLED && ESP32_SPIRAM_SUPPORT)
default n if (BT_ENABLED && SPIRAM && IDF_TARGET_ESP32)
default y
help
Select this option to place frequently called Wi-Fi library functions in IRAM.
@ -235,7 +235,7 @@ menu "Wi-Fi"
config ESP32_WIFI_RX_IRAM_OPT
bool "WiFi RX IRAM speed optimization"
default n if (BT_ENABLED && ESP32_SPIRAM_SUPPORT)
default n if (BT_ENABLED && SPIRAM && IDF_TARGET_ESP32)
default y
help
Select this option to place frequently called Wi-Fi library RX functions in IRAM.

2
components/esp_wifi/src/wifi_init.c
View File

@ -44,7 +44,7 @@ uint64_t g_wifi_feature_caps =
#if CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE
CONFIG_FEATURE_WPA3_SAE_BIT |
#endif
#if (CONFIG_ESP32_SPIRAM_SUPPORT || CONFIG_ESP32S2_SPIRAM_SUPPORT || CONFIG_ESP32S3_SPIRAM_SUPPORT)
#if CONFIG_SPIRAM
CONFIG_FEATURE_CACHE_TX_BUF_BIT |
#endif
#if CONFIG_ESP_WIFI_FTM_INITIATOR_SUPPORT

2
components/esp_wifi/src/wifi_netif.c
View File

@ -62,7 +62,7 @@ static esp_err_t wifi_transmit(void *h, void *buffer, size_t len)
static esp_err_t wifi_transmit_wrap(void *h, void *buffer, size_t len, void *netstack_buf)
{
wifi_netif_driver_t driver = h;
#if (CONFIG_ESP32_SPIRAM_SUPPORT || CONFIG_ESP32S2_SPIRAM_SUPPORT || CONFIG_ESP32S3_SPIRAM_SUPPORT)
#if CONFIG_SPIRAM
return esp_wifi_internal_tx_by_ref(driver->wifi_if, buffer, len, netstack_buf);
#else
return esp_wifi_internal_tx(driver->wifi_if, buffer, len);

2
components/mdns/test_afl_fuzz_host/sdkconfig.h
View File

@ -74,7 +74,7 @@
#define CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT 1
#define CONFIG_RTC_CLK_SRC_INT_RC 1
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
#define CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY 2000
#define CONFIG_ESP32_XTAL_FREQ_40 1
#define CONFIG_ESP32_XTAL_FREQ 40
#define CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL 5

2
components/partition_table/Kconfig.projbuild
View File

@ -121,7 +121,7 @@ menu "Partition Table"
config PARTITION_TABLE_MD5
bool "Generate an MD5 checksum for the partition table"
default y
depends on !ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS && !IDF_TARGET_LINUX
depends on !APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS && !IDF_TARGET_LINUX
help
Generate an MD5 checksum for the partition table for protecting the
integrity of the table. The generation should be turned off for legacy

16
components/spi_flash/cache_utils.c
View File

@ -491,7 +491,7 @@ static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache)
}
}
#if CONFIG_ESP32S2_SPIRAM_SUPPORT
#if (CONFIG_IDF_TARGET_ESP32S2 && CONFIG_SPIRAM)
static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache)
{
uint32_t i_autoload, d_autoload;
@ -569,7 +569,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
flash_wrap_sizes[1] = dcache_wrap_size;
}
}
#ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT
#if (CONFIG_IDF_TARGET_ESP32S2 && CONFIG_SPIRAM)
spiram_wrap_sizes[1] = dcache_wrap_size;
#endif
for (i = 0; i < 2; i++) {
@ -627,7 +627,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap.");
#endif
#ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT
#if (CONFIG_IDF_TARGET_ESP32S2 && CONFIG_SPIRAM)
extern bool psram_support_wrap_size(uint32_t wrap_size);
if (!psram_support_wrap_size(spiram_wrap_size)) {
spiram_support_wrap = false;
@ -646,7 +646,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
spi_flash_enable_wrap(flash_wrap_size);
esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0));
}
#if CONFIG_ESP32S2_SPIRAM_SUPPORT
#if (CONFIG_IDF_TARGET_ESP32S2 && CONFIG_SPIRAM)
extern esp_err_t psram_enable_wrap(uint32_t wrap_size);
if (spiram_support_wrap && spiram_wrap_size > 0) {
ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled, size = %d.", spiram_wrap_size);
@ -740,7 +740,7 @@ static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache)
}
}
#if CONFIG_ESP32S3_SPIRAM_SUPPORT
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache)
{
uint32_t i_autoload, d_autoload;
@ -818,7 +818,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
flash_wrap_sizes[1] = dcache_wrap_size;
}
}
#ifdef CONFIG_ESP32S3_SPIRAM_SUPPORT
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
spiram_wrap_sizes[1] = dcache_wrap_size;
#endif
for (i = 0; i < 2; i++) {
@ -876,7 +876,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
#endif
#ifdef CONFIG_ESP32S3_SPIRAM_SUPPORT
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
extern bool psram_support_wrap_size(uint32_t wrap_size);
if (!psram_support_wrap_size(spiram_wrap_size)) {
spiram_support_wrap = false;
@ -895,7 +895,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
spi_flash_enable_wrap(flash_wrap_size);
esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0));
}
#if CONFIG_ESP32S3_SPIRAM_SUPPORT
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
extern esp_err_t psram_enable_wrap(uint32_t wrap_size);
if (spiram_support_wrap && spiram_wrap_size > 0) {
ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled, size = %d.", spiram_wrap_size);

4
components/spi_flash/esp32s3/spi_timing_config.h
View File

@ -67,7 +67,7 @@ extern "C" {
#define SPI_TIMING_PSRAM_DTR_MODE CONFIG_SPIRAM_MODE_OCT
#define SPI_TIMING_PSRAM_STR_MODE !CONFIG_SPIRAM_MODE_OCT
//--------------------------------------PSRAM Module Clock --------------------------------------//
#if CONFIG_ESP32S3_SPIRAM_SUPPORT
#if CONFIG_SPIRAM
#if CONFIG_SPIRAM_SPEED_40M
#define SPI_TIMING_PSRAM_MODULE_CLOCK 40
#elif CONFIG_SPIRAM_SPEED_80M
@ -96,7 +96,7 @@ extern "C" {
*/
#if (SPI_TIMING_FLASH_DTR_MODE || SPI_TIMING_PSRAM_DTR_MODE)
#define SPI_TIMING_CORE_CLOCK_DIV 2
#else //#if (SPI_TIMING_FLASH_STR_MODE && (SPI_TIMING_PSRAM_STR_MODE || !CONFIG_ESP32S3_SPIRAM_SUPPORT))
#else //#if (SPI_TIMING_FLASH_STR_MODE && (SPI_TIMING_PSRAM_STR_MODE))
#define SPI_TIMING_CORE_CLOCK_DIV 1
#endif

4
docs/en/api-guides/bootloader.rst
View File

@ -34,12 +34,12 @@ The bootloader does not support booting apps from older versions of ESP-IDF. Whe
Before ESP-IDF V2.1
^^^^^^^^^^^^^^^^^^^
Bootloaders built from very old versions of ESP-IDF (before ESP-IDF V2.1) perform less hardware configuration than newer versions. When using a bootloader from these early ESP-IDF versions and building a new app, enable the config option :ref:`CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS`.
Bootloaders built from very old versions of ESP-IDF (before ESP-IDF V2.1) perform less hardware configuration than newer versions. When using a bootloader from these early ESP-IDF versions and building a new app, enable the config option :ref:`CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS`.
Before ESP-IDF V3.1
^^^^^^^^^^^^^^^^^^^
Bootloaders built from versions of ESP-IDF before V3.1 do not support MD5 checksums in the partition table binary. When using a bootloader from these ESP-IDF versions and building a new app, enable the config option :ref:`CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS`.
Bootloaders built from versions of ESP-IDF before V3.1 do not support MD5 checksums in the partition table binary. When using a bootloader from these ESP-IDF versions and building a new app, enable the config option :ref:`CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS`.
SPI Flash Configuration
^^^^^^^^^^^^^^^^^^^^^^^

2
docs/en/api-guides/flash_psram_config.rst
View File

@ -43,7 +43,7 @@ The Flash related configurations are under ``Serial flasher config`` menu.
Configure the PSRAM
^^^^^^^^^^^^^^^^^^^
To enable PSRAM, please enable the :ref:`CONFIG_{IDF_TARGET_CFG_PREFIX}_SPIRAM_SUPPORT` under ``Component config / {IDF_TARGET_NAME}-Specific`` menu. Then all the PSRAM related configurations will be visible under ``SPI RAM config`` menu.
To enable PSRAM, please enable the :ref:`CONFIG_SPIRAM` under ``Component config / Hardware Settings`` menu. Then all the PSRAM related configurations will be visible under ``SPI RAM config`` menu.
1. PSRAM type used on the board. Select a type in :ref:`CONFIG_SPIRAM_MODE` for Quad or Octal PSRAM.
2. PSRAM speed. Select a PSRAM frequency in :ref:`CONFIG_SPIRAM_SPEED`.

2
docs/en/api-guides/partition-tables.rst
View File

@ -191,7 +191,7 @@ The binary format of the partition table contains an MD5 checksum computed based
.. only:: esp32
The MD5 checksum generation can be disabled by the ``--disable-md5sum`` option of ``gen_esp32part.py`` or by the :ref:`CONFIG_PARTITION_TABLE_MD5` option. This is useful for example when one :ref:`uses a bootloader from ESP-IDF before v3.1 <CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS>` which cannot process MD5 checksums and the boot fails with the error message ``invalid magic number 0xebeb``.
The MD5 checksum generation can be disabled by the ``--disable-md5sum`` option of ``gen_esp32part.py`` or by the :ref:`CONFIG_PARTITION_TABLE_MD5` option. This is useful for example when one :ref:`uses a bootloader from ESP-IDF before v3.1 <CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS>` which cannot process MD5 checksums and the boot fails with the error message ``invalid magic number 0xebeb``.
.. only:: not esp32

4
docs/zh_CN/api-guides/bootloader.rst
View File

@ -34,12 +34,12 @@ ESP-IDF 软件引导加载程序 (Bootloader) 主要执行以下任务：
ESP-IDF V2.1 之前的版本
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
与新版本相比，ESP-IDF V2.1 之前的版本构建的引导加载程序对硬件的配置更少。使用这些早期 ESP-IDF 版本的引导加载程序并构建新应用程序时，请启用配置选项 :ref:`CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS`。
与新版本相比，ESP-IDF V2.1 之前的版本构建的引导加载程序对硬件的配置更少。使用这些早期 ESP-IDF 版本的引导加载程序并构建新应用程序时，请启用配置选项 :ref:`CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS`。
ESP-IDF V3.1 之前的版本
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ESP-IDF V3.1 之前的版本构建的引导加载程序不支持分区表二进制文件中的 MD5 校验。使用这些 ESP-IDF 版本的引导加载程序并构建新应用程序时，请启用配置选项 :ref:`CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS`。
ESP-IDF V3.1 之前的版本构建的引导加载程序不支持分区表二进制文件中的 MD5 校验。使用这些 ESP-IDF 版本的引导加载程序并构建新应用程序时，请启用配置选项 :ref:`CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS`。
配置 SPI Flash
^^^^^^^^^^^^^^^^^^^^^^^

2
docs/zh_CN/api-guides/partition-tables.rst
View File

@ -191,7 +191,7 @@ MD5 校验和
.. only:: esp32
用户可通过 ``gen_esp32part.py`` 的 ``--disable-md5sum`` 选项或者 :ref:`CONFIG_PARTITION_TABLE_MD5` 选项关闭 MD5 校验。对于 :ref:`ESP-IDF v3.1 版本前的引导加载程序 <CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS>`，因为它不支持 MD5 校验，所以无法正常启动并报错 ``invalid magic number 0xebeb``，此时用户可以使用此选项关闭 MD5 校验。
用户可通过 ``gen_esp32part.py`` 的 ``--disable-md5sum`` 选项或者 :ref:`CONFIG_PARTITION_TABLE_MD5` 选项关闭 MD5 校验。对于 :ref:`ESP-IDF v3.1 版本前的引导加载程序 <CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS>`，因为它不支持 MD5 校验，所以无法正常启动并报错 ``invalid magic number 0xebeb``，此时用户可以使用此选项关闭 MD5 校验。
.. only:: not esp32

5
examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32
View File

@ -1091,7 +1091,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1120,13 +1119,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32
View File

@ -1095,7 +1095,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1124,13 +1123,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

1
examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32
View File

@ -1095,7 +1095,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1124,13 +1123,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32
View File

@ -1092,7 +1092,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1121,13 +1120,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32
View File

@ -1094,7 +1094,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1123,13 +1122,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32
View File

@ -1092,7 +1092,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1121,13 +1120,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32
View File

@ -1094,7 +1094,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1123,13 +1122,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32
View File

@ -1092,7 +1092,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1121,13 +1120,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32
View File

@ -1094,7 +1094,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1123,13 +1122,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32
View File

@ -1090,7 +1090,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1119,13 +1118,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32
View File

@ -1094,7 +1094,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1123,13 +1122,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32
View File

@ -1092,7 +1092,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1121,13 +1120,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32
View File

@ -1092,7 +1092,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1121,13 +1120,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32
View File

@ -1094,7 +1094,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1123,13 +1122,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

1
examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32s3
View File

@ -351,7 +351,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

1
examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32s3
View File

@ -351,7 +351,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

1
examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32s3
View File

@ -351,7 +351,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

1
examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32s3
View File

@ -351,7 +351,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

1
examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32s3
View File

@ -351,7 +351,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

1
examples/bluetooth/bluedroid/coex/gattc_gatts_coex/sdkconfig.defaults.esp32s3
View File

@ -354,7 +354,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

5
examples/bluetooth/bluedroid/coex/gattc_gatts_coex/sdkconfig.defauts.esp32
View File

@ -1094,7 +1094,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1123,13 +1122,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

5
examples/bluetooth/blufi/sdkconfig.defaults.esp32
View File

@ -1080,7 +1080,6 @@ CONFIG_ESP32_DPORT_WORKAROUND=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
# CONFIG_ESP32_SPIRAM_SUPPORT is not set
# CONFIG_ESP32_TRAX is not set
CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
@ -1109,13 +1108,13 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
# CONFIG_ESP32_XTAL_FREQ_26 is not set
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
CONFIG_ESP32_XTAL_FREQ=40
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
# end of ESP32-specific

1
examples/bluetooth/blufi/sdkconfig.defaults.esp32s3
View File

@ -342,7 +342,6 @@ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
# CONFIG_ESP32S3_TRAX is not set
CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set

2
examples/bluetooth/esp_ble_mesh/ble_mesh_coex_test/sdkconfig.defaults
View File

@ -53,7 +53,7 @@ CONFIG_BTDM_RESERVE_DRAM=0x10000
#
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
CONFIG_MEMMAP_SMP=y
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_80M=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=4096
CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y

2
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/fast_prov_server/sdkconfig.ci.psram
View File

@ -13,7 +13,7 @@ CONFIG_BLE_MESH_FAST_PROV=y
CONFIG_BLE_MESH_PB_GATT=y
CONFIG_BLE_MESH_CFG_CLI=y
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
CONFIG_BLE_MESH_MEM_ALLOC_MODE_EXTERNAL=y
CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC=y

2
examples/peripherals/lcd/i80_controller/sdkconfig.defaults.esp32s3
View File

@ -1,4 +1,4 @@
CONFIG_ESP32S3_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_80M=y
# Can't set the FPS too high due to the limitation of PSRAM bandwidth
CONFIG_LV_DISP_DEF_REFR_PERIOD=100

2
examples/peripherals/lcd/rgb_panel/sdkconfig.defaults.esp32s3
View File

@ -1,3 +1,3 @@
CONFIG_ESP32S3_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_MODE_OCT=y
CONFIG_SPIRAM_SPEED_80M=y

2
examples/protocols/http2_request/sdkconfig.ci
View File

@ -1,4 +1,4 @@
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=y
CONFIG_EXAMPLE_CONNECT_ETHERNET=y
CONFIG_EXAMPLE_CONNECT_WIFI=n

2
examples/protocols/https_mbedtls/sdkconfig.ci
View File

@ -1,4 +1,4 @@
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=y
CONFIG_EXAMPLE_CONNECT_ETHERNET=y
CONFIG_EXAMPLE_CONNECT_WIFI=n

2
examples/protocols/https_request/sdkconfig.ci
View File

@ -1,4 +1,4 @@
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=y
CONFIG_EXAMPLE_CONNECT_ETHERNET=y
CONFIG_EXAMPLE_CONNECT_WIFI=n

2
examples/protocols/https_request/sdkconfig.ci.ssldyn
View File

@ -1,4 +1,4 @@
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=y
CONFIG_EXAMPLE_CONNECT_ETHERNET=y
CONFIG_EXAMPLE_CONNECT_WIFI=n

2
examples/system/himem/sdkconfig.defaults
View File

@ -1,4 +1,4 @@
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_BOOT_INIT=y
CONFIG_SPIRAM_IGNORE_NOTFOUND=n
CONFIG_SPIRAM_USE_MALLOC=y

2
examples/system/ota/simple_ota_example/sdkconfig.ci.spiram
View File

@ -1,6 +1,6 @@
CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL="FROM_STDIN"
CONFIG_EXAMPLE_SKIP_COMMON_NAME_CHECK=y
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
CONFIG_EXAMPLE_CONNECT_ETHERNET=y
CONFIG_EXAMPLE_CONNECT_WIFI=n

2
sdkconfig.rename
View File

@ -22,3 +22,5 @@ CONFIG_STACK_CHECK CONFIG_COMPILER_STACK_CHECK
CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
CONFIG_DISABLE_GCC8_WARNINGS CONFIG_COMPILER_DISABLE_GCC8_WARNINGS
CONFIG_NO_BLOBS CONFIG_APP_NO_BLOBS
CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS
CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS

22
tools/ci/test_build_system_cmake.sh
View File

@ -518,7 +518,7 @@ function run_tests()
print_status "Building a project with CMake library imported and PSRAM workaround, all files compile with workaround"
# Test for libraries compiled within ESP-IDF
rm -r build sdkconfig
echo "CONFIG_ESP32_SPIRAM_SUPPORT=y" >> sdkconfig.defaults
echo "CONFIG_SPIRAM=y" >> sdkconfig.defaults
echo "CONFIG_SPIRAM_CACHE_WORKAROUND=y" >> sdkconfig.defaults
# note: we do 'reconfigure' here, as we just need to run cmake
idf.py -C $IDF_PATH/examples/build_system/cmake/import_lib -B `pwd`/build -D SDKCONFIG_DEFAULTS="`pwd`/sdkconfig.defaults" reconfigure
@ -529,7 +529,7 @@ function run_tests()
print_status "Test for external libraries in custom CMake projects with ESP-IDF components linked"
mkdir build
IDF_AS_LIB=$IDF_PATH/examples/build_system/cmake/idf_as_lib
echo "CONFIG_ESP32_SPIRAM_SUPPORT=y" > $IDF_AS_LIB/sdkconfig
echo "CONFIG_SPIRAM=y" > $IDF_AS_LIB/sdkconfig
echo "CONFIG_SPIRAM_CACHE_WORKAROUND=y" >> $IDF_AS_LIB/sdkconfig
# note: we just need to run cmake
(cd build && cmake $IDF_AS_LIB -DCMAKE_TOOLCHAIN_FILE=$IDF_PATH/tools/cmake/toolchain-esp32.cmake -DTARGET=esp32)
@ -540,7 +540,7 @@ function run_tests()
print_status "Test for external libraries in custom CMake projects with PSRAM strategy $strat"
rm -r build sdkconfig sdkconfig.defaults sdkconfig.defaults.esp32
stratlc=`echo $strat | tr A-Z a-z`
echo "CONFIG_ESP32_SPIRAM_SUPPORT=y" > sdkconfig.defaults
echo "CONFIG_SPIRAM=y" > sdkconfig.defaults
echo "CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_$strat=y" >> sdkconfig.defaults
echo "CONFIG_SPIRAM_CACHE_WORKAROUND=y" >> sdkconfig.defaults
# note: we do 'reconfigure' here, as we just need to run cmake
@ -899,15 +899,15 @@ endmenu\n" >> ${IDF_PATH}/Kconfig
print_status "Getting component overriden dir"
clean_build_dir
mkdir -p components/esp32
echo "idf_component_get_property(overriden_dir \${COMPONENT_NAME} COMPONENT_OVERRIDEN_DIR)" >> components/esp32/CMakeLists.txt
echo "message(STATUS overriden_dir:\${overriden_dir})" >> components/esp32/CMakeLists.txt
(idf.py reconfigure | grep "overriden_dir:$IDF_PATH/components/esp32") || failure "Failed to get overriden dir" # no registration, overrides registration as well
mkdir -p components/hal
echo "idf_component_get_property(overriden_dir \${COMPONENT_NAME} COMPONENT_OVERRIDEN_DIR)" >> components/hal/CMakeLists.txt
echo "message(STATUS overriden_dir:\${overriden_dir})" >> components/hal/CMakeLists.txt
(idf.py reconfigure | grep "overriden_dir:$IDF_PATH/components/hal") || failure "Failed to get overriden dir" # no registration, overrides registration as well
print_status "Overriding Kconfig"
echo "idf_component_register(KCONFIG \${overriden_dir}/Kconfig)" >> components/esp32/CMakeLists.txt
echo "idf_component_get_property(kconfig \${COMPONENT_NAME} KCONFIG)" >> components/esp32/CMakeLists.txt
echo "message(STATUS kconfig:\${overriden_dir}/Kconfig)" >> components/esp32/CMakeLists.txt
(idf.py reconfigure | grep "kconfig:$IDF_PATH/components/esp32/Kconfig") || failure "Failed to verify original `main` directory"
echo "idf_component_register(KCONFIG \${overriden_dir}/Kconfig)" >> components/hal/CMakeLists.txt
echo "idf_component_get_property(kconfig \${COMPONENT_NAME} KCONFIG)" >> components/hal/CMakeLists.txt
echo "message(STATUS kconfig:\${overriden_dir}/Kconfig)" >> components/hal/CMakeLists.txt
(idf.py reconfigure | grep "kconfig:$IDF_PATH/components/hal/Kconfig") || failure "Failed to verify original `main` directory"
rm -rf components
print_status "Project components prioritized over EXTRA_COMPONENT_DIRS"

6
tools/ldgen/samples/sdkconfig
View File

@ -123,7 +123,7 @@ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=240
CONFIG_ESP32_SPIRAM_SUPPORT=
CONFIG_SPIRAM=
CONFIG_ESP32_MEMMAP_TRACEMEM=
CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS=
CONFIG_ESP32_TRAX=
@ -183,14 +183,14 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
CONFIG_RTC_CLK_SRC_EXT_CRYS=
CONFIG_RTC_CLK_CAL_CYCLES=1024
CONFIG_RTC_XTAL_BOOTSTRAP_CYCLES=100
CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
CONFIG_ESP32_XTAL_FREQ_40=y
CONFIG_ESP32_XTAL_FREQ_26=
CONFIG_ESP32_XTAL_FREQ_AUTO=
CONFIG_ESP32_XTAL_FREQ=40
CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE=
CONFIG_ESP_TIMER_PROFILING=
CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
#

2
tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_120sdr
View File

@ -3,5 +3,5 @@
CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
CONFIG_ESP32S3_SPIRAM_SUPPORT=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_120M=y

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