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Merge branch 'bugfix/fix_memory_miss_bug_esp32c3_esp32s3' into 'master'
ESP32C3/ESP32S3: Fix cpu crash bug when wakeup from lightsleep for memory data miss Closes IDF-162 and IDF-4923 See merge request espressif/esp-idf!17823
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commit
0adb814af3
@ -161,6 +161,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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}
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/* mem force pu */
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
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if (!cfg.int_8m_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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@ -29,7 +29,6 @@
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*/
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void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
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{
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#if !CONFIG_IDF_ENV_FPGA
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REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
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REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
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REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
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@ -43,7 +42,6 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
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REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
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#endif
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if (cfg.sram_fpu) {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
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} else {
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@ -170,8 +168,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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}
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/* mem pd */
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
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/* mem force pu */
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
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if (!cfg.int_8m_pd_en) {
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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@ -58,9 +58,8 @@ extern "C" {
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/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
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* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
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* Valid if RTC_CNTL_DBG_ATTEN is 0.
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*/
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#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias
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#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
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#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
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#define RTC_CNTL_DBIAS_0V95 16
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#define RTC_CNTL_DBIAS_1V00 18
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@ -105,7 +104,7 @@ extern "C" {
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/*
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set sleep_init default param
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*/
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#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3
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#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
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#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
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#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
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#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
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@ -59,9 +59,8 @@ extern "C" {
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/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
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* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
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* Valid if RTC_CNTL_DBG_ATTEN is 0.
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*/
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#define RTC_CNTL_DBIAS_SLP 0 ///< sleep dig_dbias & rtc_dbias
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#define RTC_CNTL_DBIAS_SLP 5 ///< sleep dig_dbias & rtc_dbias
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#define RTC_CNTL_DBIAS_0V90 13 ///< digital voltage
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#define RTC_CNTL_DBIAS_0V95 16
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#define RTC_CNTL_DBIAS_1V00 18
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