G0: Support Xtensa targets for G0-only compilation

G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore

components/bootloader_support/src/bootloader_random_esp32c2.c

@@ -11,7 +11,7 @@
 #include "soc/apb_saradc_reg.h"
 #include "soc/system_reg.h"
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 
 void bootloader_random_enable(void)
 {

components/bootloader_support/src/bootloader_random_esp32c3.c

@@ -11,7 +11,7 @@
 #include "soc/apb_saradc_reg.h"
 #include "soc/system_reg.h"
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 
 void bootloader_random_enable(void)
 {

components/bootloader_support/src/bootloader_random_esp32s3.c

@@ -11,8 +11,8 @@
 #include "soc/apb_saradc_reg.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/sens_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
 
 void bootloader_random_enable(void)
 {

components/driver/deprecated/rtc_temperature_legacy.c

@@ -13,7 +13,7 @@
 #include "esp_check.h"
 #include "soc/rtc_cntl_reg.h"
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 #include "esp_log.h"
 #include "esp_efuse_rtc_calib.h"
 #include "hal/temperature_sensor_ll.h"

components/driver/test/test_adc.c

@@ -392,7 +392,7 @@ TEST_CASE("test_adc_single_cali_time", "[adc][ignore][manual]")
 #include "esp_sleep.h"
 #include "esp_private/regi2c_ctrl.h"
 #if REGI2C_ANA_CALI_PD_WORKAROUND
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 #endif
 
 //ADC Channels

components/esp_hw_support/port/esp32c2/private_include/regi2c_saradc.h

@@ -1,9 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/regi2c_saradc.h"

components/esp_hw_support/port/esp32c3/private_include/regi2c_saradc.h

@@ -1,9 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/regi2c_saradc.h"

components/esp_hw_support/port/esp32h2/private_include/regi2c_saradc.h

@@ -1,9 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/regi2c_saradc.h"

components/esp_hw_support/regi2c_ctrl.c

@@ -9,7 +9,7 @@
 #include <stdint.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
-#include "regi2c_ctrl.h"
+#include "hal/regi2c_ctrl.h"
 
 static portMUX_TYPE mux = portMUX_INITIALIZER_UNLOCKED;
 
@@ -58,7 +58,7 @@ void IRAM_ATTR regi2c_exit_critical(void)
  * This is a workaround, and is fixed on later chips
  */
 #if REGI2C_ANA_CALI_PD_WORKAROUND
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 
 static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM];
 

components/hal/esp32c3/include/hal/temperature_sensor_ll.h

@@ -17,7 +17,7 @@
 #include <stdbool.h>
 #include <stdlib.h>
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/soc.h"
 #include "soc/soc_caps.h"

components/hal/esp32h2/include/hal/temperature_sensor_ll.h

@@ -17,7 +17,7 @@
 #include <stdbool.h>
 #include <stdlib.h>
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/soc.h"
 #include "soc/soc_caps.h"

components/hal/esp32s2/brownout_hal.c

@@ -8,9 +8,9 @@
 #include "hal/brownout_hal.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_brownout.h"
 #include "esp_attr.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_brownout.h"
 
 void brownout_hal_config(const brownout_hal_config_t *cfg)
 {

components/hal/esp32s2/include/hal/adc_ll.h

@@ -17,8 +17,9 @@
 #include "soc/apb_saradc_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_defs.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32s2/include/hal/temperature_sensor_ll.h

@@ -16,7 +16,7 @@
 
 #include <stdbool.h>
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/sens_struct.h"

components/hal/esp32s3/brownout_hal.c

@@ -8,9 +8,9 @@
 #include "hal/brownout_hal.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_brownout.h"
 #include "esp_attr.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_brownout.h"
 
 
 void brownout_hal_config(const brownout_hal_config_t *cfg)

components/hal/esp32s3/include/hal/adc_ll.h

@@ -18,9 +18,9 @@
 #include "soc/apb_saradc_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_defs.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32s3/include/hal/gdma_ll.h

@@ -5,6 +5,7 @@
  */
 #pragma once
 
+#include <stddef.h> /* For NULL declaration */
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/soc_caps.h"

components/hal/esp32s3/include/hal/hmac_ll.h

@@ -12,6 +12,7 @@
 
 #pragma once
 
+#include <stddef.h> /* For size_t type */
 #include "soc/hwcrypto_reg.h"
 
 #define SHA256_BLOCK_SZ 64

components/hal/esp32s3/include/hal/lcd_ll.h

@@ -5,6 +5,7 @@
  */
 #pragma once
 
+#include <stddef.h> /* For NULL declaration */
 #include <stdint.h>
 #include <stdbool.h>
 #include "hal/misc.h"

components/hal/esp32s3/include/hal/temperature_sensor_ll.h

@@ -16,7 +16,7 @@
 
 #include <stdbool.h>
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_saradc.h"
+#include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/sens_struct.h"

components/hal/platform_port/include/hal/regi2c_ctrl.h

@@ -5,6 +5,14 @@
  */
 #pragma once
 
+/**
+ * When compiling G0-layer only, we can't depend on `esp_hw_support` component.
+ * However, `esp_private/regi2c_ctrl.h` is part of that component.
+ * Thus, if we don't have this header file in our compilation unit, we should use
+ * ROM functions.
+ * The main difference is that `regi2c_ctrl.h` implementation protects the functions
+ * with mutex. ROM functions must be protected explicitly by the user.
+ */
 #if __has_include("esp_private/regi2c_ctrl.h")
     #include "esp_private/regi2c_ctrl.h"
 #else

components/xtensa/xtensa_intr.c

@@ -30,13 +30,25 @@
 #include <stdlib.h>
 
 #include <xtensa/config/core.h>
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/portable.h"
+#include "esp_attr.h"
 #include "xtensa/xtensa_api.h"
 #include "sdkconfig.h"
 #include "esp_rom_sys.h"
 
+/*
+ * When compiling for G0-only, we don't have FreeRTOS component.
+ * In fact, FreeRTOS component is only used for the core configuration, so
+ * the macro portNUM_PROCESSORS and the macro/function xPortGetCoreID need to
+ * be defined.
+ */
+#if __has_include("freertos/FreeRTOS.h")
+    #include "freertos/FreeRTOS.h"
+    #include "freertos/portable.h"
+#else
+    _Static_assert(portNUM_PROCESSORS == 1, "G0-only Xtensa builds can only be compiled in single-core mode");
+    #define xPortGetCoreID()    0
+#endif
+
 #if XCHAL_HAVE_EXCEPTIONS
 
 /* Handler table is in xtensa_intr_asm.S */

components/xtensa/xtensa_intr_asm.S

@@ -1,4 +1,10 @@
-
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
@@ -31,7 +37,15 @@
 #include <xtensa/config/core.h>
 
 #include "xtensa/xtensa_context.h"
-#include "freertos/FreeRTOSConfig.h"
+
+/*
+ * When compiling for G0-only, we don't have FreeRTOS component.
+ * In fact, FreeRTOS component is only used for the configuration, so only the
+ * macro portNUM_PROCESSORS needs to be defined (in the build file).
+ */
+#if __has_include("freertos/FreeRTOSConfig.h")
+    #include "freertos/FreeRTOSConfig.h"
+#endif
 
 #if XCHAL_HAVE_INTERRUPTS
 

tools/ci/check_copyright_config.yaml

@@ -118,6 +118,13 @@ argtable3:
     - BSD-3-Clause
     - Apache-2.0
 
+xtensa:
+  include:
+    - 'components/xtensa/**'
+  allowed_licenses:
+    - Apache-2.0    #Files added to the xtensa component by us
+    - MIT           #Cadence sources
+
 # files matching this section do not perform the check
 # file patterns starting with ! are negated, meaning files matching them won't match the section.
 ignore:

tools/test_apps/system/g0_components/CMakeLists.txt

@@ -2,7 +2,7 @@
 # https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html
 # The following five lines of boilerplate have to be in your project's
 # CMakeLists in this exact order for cmake to work correctly
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.16)
 
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 
@@ -32,6 +32,12 @@ if(CONFIG_IDF_TARGET_ESP32C2)
     idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_MMU_PAGE_SIZE=64" APPEND)
 endif()
 
+# Currently, only support a single core on Xtensa targets.
+if(CONFIG_IDF_TARGET_ARCH_XTENSA)
+    idf_build_set_property(C_COMPILE_OPTIONS "-DportNUM_PROCESSORS=1" APPEND)
+    idf_build_set_property(ASM_COMPILE_OPTIONS "-DportNUM_PROCESSORS=1" APPEND)
+endif()
+
 # Now that the project has been initialized, let's check which components it is using
 # The following variable lists all the components that shall be used by this project
 set(expected_components

tools/test_apps/system/g0_components/README.md

@@ -1,22 +1,18 @@
-| Supported Targets | ESP32-C3 | ESP32-C2 | ESP32-H2 |
-| ----------------- | -------- | -------- | -------- |
-
-All Xtensa based targets (ESP32, ESP32-S2, ESP32-S3) are currently not supported by this test, because their components having dependencies on G1+ components.
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 | ESP32-C2 | ESP32-H2 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
 
 # "G0"-components-only app
 
-This test application will compile ESP-IDF and this test's main component with G0 components only. The goal is to make sure that no G0 component depends
-on G1 or higher component.
+This test application will compile ESP-IDF and this test's main component with G0 components only.
+The goal is to make sure that no G0 component depends on G1 or higher component.
 
-Currently, this test only supports RISC-V based targets as Xtensa ones still have some G0 components depending on G1+ components.
-
-Compiling this test with an Xtensa based target will result in a CMake error, showing all the non-G0 components included in the build file generation.
+This supports all Xtensa and RISC-V based ESP targets.
 
 The purpose of this example is to make sure that any modification to ESP-IDF doesn't violate the G0-G1+ dependency rule.
 
 # Using this test app
 
-Set the target to a RISC-V based, `esp32c3` for example:
+Set the target, `esp32c3` for example:
 ```bash
 idf.py set-target esp32c3
 ```

tools/test_apps/system/g0_components/main/CMakeLists.txt

@@ -1,2 +1,2 @@
-idf_component_register(SRCS "g0_components.c"
+idf_component_register(SRCS ""
                     INCLUDE_DIRS ".")

tools/test_apps/system/g0_components/main/g0_components.c

@@ -1,11 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <stdio.h>
-
-void app_main(void)
-{
-
-}