Commit Graph

84 Commits

Author SHA1 Message Date
wuzhenghui
783059a592 fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting 2023-11-16 18:11:57 +08:00
Omar Chebib
e56f5b15cc fix(riscv): fix a bug in FPU exception handling
On the ESP32-P4, it is possible to have an exception because of an FPU instruction
while EXT_ILL CSR is not zero and its FPU bit is not set.
2023-11-14 06:55:08 +00:00
Marius Vikhammer
22091c8744 feat(wdt): add multicore support for WDTs on RISCV 2023-10-23 18:26:08 +08:00
Omar Chebib
a8b1475fe7 feat(riscv): implement coprocessors save area and FPU support
This commit mainly targets the ESP32-P4. It adds supports for coprocessors on
RISC-V based targets. The coprocessor save area, describing the used coprocessors
is stored at the end of the stack of each task (highest address) whereas each
coprocessor save area is allocated at the beginning of the task (lowest address).
The context of each coprocessor is saved lazily, by the task that want to use it.
2023-10-23 11:10:28 +08:00
Sudeep Mohanty
cf55ab899a fix(freertos): Fixed xPortCanYield to correctly determine ISR context on esp32p4
This commit fixes an issue where xPortCanYield() function may not be
able to detect an ISR context when HW interrupt nesting is active on
a CLIC interrupt controller such as on esp32p4.
2023-10-09 09:12:15 +02:00
KonstantinKondrashov
7a878bdc50 feat(esp_system): Support IPC_ISR for ESP32P4 2023-09-15 23:38:12 +08:00
KonstantinKondrashov
25c7a59e31 fix(freertos): Use INTERRUPT_CURRENT_CORE_INT_THRESH_REG for esp32p4 2023-09-07 15:25:35 +08:00
Sudeep Mohanty
5cd989f23b fix(interrupts): Cleanup pending tags in the code base regarding interrupt vectors 2023-09-01 17:18:39 +08:00
Omar Chebib
8ca191e4c1 fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-31 12:16:08 +08:00
Marius Vikhammer
0d9f9e6816 feat(core-systems): add support for spinlock/compare and set on esp32p4 2023-08-24 10:30:25 +08:00
Armando
fd096c012d change(vector.S): port hw stack guard change to p4 2023-07-25 05:59:10 +00:00
Armando
ecf1461f1c feat(panic): base support on p4 2023-07-25 05:59:10 +00:00
Armando
5986e63c47 change(riscv): added fence after CLIC_INT_THRESH_REG is set 2023-07-25 05:59:10 +00:00
Armando
e11b154c99 feat(interrupt): mtvt, mtvec base support on p4 2023-07-25 05:59:10 +00:00
Armando
c156e56684 feat(spinlock): added spinlock base support on p4 2023-07-25 05:59:10 +00:00
Armando
019e68bb15 feat(interrupt): added clic support on p4 2023-07-25 05:59:10 +00:00
Armando
c76de79f4c feat(cpu): added cpu utils base support on p4 2023-07-25 05:59:10 +00:00
Armando
bc182ef010 feat(brc_predictor): p4 base support for branch predictor 2023-07-25 05:59:10 +00:00
Alexey Lapshin
4df3ff619e feat(esp_system): implement hw stack guard for riscv chips
- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
2023-07-01 16:27:40 +00:00
wuzhenghui
756b5f628d bugfix: fix pmp retention and add pma retention 2023-05-29 16:35:03 +08:00
Alexey Lapshin
9322c2b82d esp_gdbstup: implement runtime gdbstub for riscv 2023-05-19 20:15:58 +08:00
Alexey Lapshin
36588c4b35 riscv: remove outdated macros 2023-05-19 20:15:58 +08:00
Alexey Lapshin
a89b799642 riscv: fix trigger add from trap handlers 2023-05-19 20:15:58 +08:00
Alexey Lapshin
d41d12fe7a riscv: fix & refactor triggers add/delete 2023-05-19 20:15:58 +08:00
Jakob Hasse
0a3cfce671 Merge branch 'contrib/github_pr_10895' into 'master'
Fix possible conversion errors by using __builtin_ffsll (GitHub PR)

Closes IDFGH-9541

See merge request espressif/esp-idf!23429
2023-05-04 10:41:46 +08:00
Jakob Hasse
ca44fc3847 cxx/esp_hw_support: added build test, changed parameter types
Changed rv_utils_intr_edge_ack and esp_cpu_intr_edge_ack to
take uint32_t instead of int to avoid build errors.

The test is to test in particular that __builtin_ffsll, used in
xt_utils.h, which is included via esp_cpu.h, compiles fine
in C++20 with -Wsign-conversion enabled.

Closes https://github.com/espressif/esp-idf/pull/10895
2023-04-26 19:06:39 +08:00
Wu Zheng Hui
98849634b3 Merge branch 'bugfix/fix_wrong_frame_ptr_after_wake_restore' into 'master'
bugfix: fix wrong RvCoreCriticalSleepFrame ptr value after wake restore

See merge request espressif/esp-idf!23113
2023-04-14 13:22:24 +08:00
wuzhenghui
332d6fddb9 esp_pm: check sleep retention frame integrity in ci UT 2023-04-11 11:18:52 +08:00
Marius Vikhammer
f7d045ad5c riscv: moved some interrupt functions from IRAM to flash
These functions dont need to be in IRAM.
2023-04-10 12:21:11 +08:00
Sachin Parekh
ed0a1f7b52 esp32c6: Fix incorrect PMP configuration
- Enable pytest memprot tests for C6
2023-03-09 11:37:29 +05:30
Li Shuai
9b99fc9033 cpu retention: software cpu retention support for esp32c6
cpu retention: add riscv core sleep critical and non-critical register layout structure definition

cpu retention: add assembly subroutine for cpu critical register backup and restore

cpu retention: add cpu core critical register context backup and restore support

cpu retention: add cpu core non-critical register context backup and restore support

cpu retention: add interrupt priority register context backup and restore support

cpu retention: add cache config register context backup and restore support

cpu retention: add plic interrupt register context backup and restore support

cpu retention: add clint interrupt register context backup and restore support

cpu retention: wait icache state idle before pmu enter sleep
2023-01-31 22:12:54 +08:00
Andrei Safronov
2c5a9494fe Merge branch 'bugfix/fix_gnu_asm_struct' into 'master'
xtensa: remove asm struct expressions in header files

See merge request espressif/esp-idf!18836
2022-12-07 20:21:31 +08:00
Alexey Gerenkov
002411b169 riscv: Use 'li' instead of 'la' for loading peripheral reg address 2022-12-06 21:54:50 +03:00
Sachin Parekh
7af998d23f esp32c6: Enable IRAM-DRAM split using PMP 2022-12-06 14:50:55 +00:00
Alexey Gerenkov
2710749f21 riscv: Remove asm struct expressions in header files 2022-12-06 13:35:27 +03:00
Alexey Gerenkov
47c2c13de5 build: Adds support for universal Clang toolchain 2022-11-23 13:25:16 +03:00
Omar Chebib
cd21058097 C/Cxx: unify static assertions with the macro ESP_STATIC_ASSERT
Closes https://github.com/espressif/esp-idf/issues/9938
2022-11-21 16:18:08 +08:00
Song Ruo Jing
1eb9a24a48 esp_system: Minor update for esp32c6 2022-09-26 20:32:13 +08:00
Darian Leung
abf0bc13e6 riscv: Fix esprv_intc_int_set_threshold() naming
This commit fixes the function declaration naming from esprv_intc_set_threshold()
to esprv_intc_int_set_threshold(), thus allowing the underlying ROM funciton to be
exposed via the header.
2022-09-16 16:45:43 +08:00
Darian Leung
0c97fbd5ba riscv: Remove redundant riscv_interrupts.h header
This commit removes the riscv_interrupts.h header is it has become redundant. The previously
exposed API has been handled as follows:

- "riscv_interrupt_enable()" and "riscv_interrupt_disable()" have been removed. These functions
  were declarations only and never had any implementation.
- "riscv_global_interrupts_enable()" and "riscv_global_interrupts_disable()" renamed to
  "rv_utils_intr_global_enable()" and "rv_utils_intr_global_disable()" respectively and now
  placed in rv_utils.h
2022-09-16 16:45:43 +08:00
Omar Chebib
53c7dd4efc WDT: implement interrupt wdt and task wdt for ESP32-C2
ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
2022-09-15 14:37:59 +08:00
songruojing
9d515185d0 esp32c6: clean up existing soc files and header file inclusion in IDF to be compatible with the new chip 2022-09-01 12:28:06 +08:00
Ivan Grokhotkov
879352b7f3 build system: remove -Wno-format flag for RISC-V targets 2022-08-03 16:42:47 +04:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
2022-06-16 11:53:39 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer
G0 doesn't depend on any G1+ layer for RISC-V based targets
2022-06-14 15:00:53 +08:00
Darian Leung
61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
2022-06-14 14:30:58 +08:00
Marius Vikhammer
cf1b222cac build system: removed target component
After refactoring the target components (e.g. esp32) no longer contained any real functionality.
What remained in these components have been moved elsewhere and the component itself deleted from the
build system.
2022-05-24 09:12:59 +08:00
Marius Vikhammer
9362434c47 build-system: add property for architecture (riscv/xtensa)
riscv/xtensa is now a common component.
2022-05-20 09:00:32 +08:00
Erhan Kurubas
0fc0254734 semihosting: version 2 2022-05-05 09:12:42 +00:00
Alexey Gerenkov
dea45a9d72 riscv: Use semihosting to set breakpoint and watchpoint when running under debugger 2022-02-24 08:55:40 +00:00