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feat(cpu): added cpu utils base support on p4
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -16,6 +16,9 @@
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#include "soc/pcr_reg.h"
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#define SYSTEM_CPU_PER_CONF_REG PCR_CPU_WAITI_CONF_REG
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#define SYSTEM_CPU_WAIT_MODE_FORCE_ON PCR_CPU_WAIT_MODE_FORCE_ON
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#elif CONFIG_IDF_TARGET_ESP32P4
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#include "soc/lp_clkrst_reg.h"
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#include "soc/pmu_reg.h"
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#else
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#include "soc/rtc_cntl_reg.h"
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#endif
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@ -45,6 +48,10 @@ void esp_cpu_stall(int core_id)
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{
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assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM);
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#if SOC_CPU_CORES_NUM > 1 // We don't allow stalling of the current core
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#if CONFIG_IDF_TARGET_ESP32P4
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//TODO: IDF-7848
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REG_SET_FIELD(PMU_CPU_SW_STALL_REG, core_id ? PMU_HPCORE1_SW_STALL_CODE : PMU_HPCORE0_SW_STALL_CODE, 0x86);
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#else
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/*
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We need to write the value "0x86" to stall a particular core. The write location is split into two separate
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bit fields named "c0" and "c1", and the two fields are located in different registers. Each core has its own pair of
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@ -62,13 +69,18 @@ void esp_cpu_stall(int core_id)
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2 << rtc_cntl_c0_s);
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CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, rtc_cntl_c1_m);
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SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21 << rtc_cntl_c1_s);
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#endif
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#endif // CONFIG_IDF_TARGET_ESP32P4
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#endif // SOC_CPU_CORES_NUM > 1
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}
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void esp_cpu_unstall(int core_id)
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{
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assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM);
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#if SOC_CPU_CORES_NUM > 1 // We don't allow stalling of the current core
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#if CONFIG_IDF_TARGET_ESP32P4
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//TODO: IDF-7848
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REG_SET_FIELD(PMU_CPU_SW_STALL_REG, core_id ? PMU_HPCORE1_SW_STALL_CODE : PMU_HPCORE0_SW_STALL_CODE, 0);
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#else
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/*
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We need to write clear the value "0x86" to unstall a particular core. The location of this value is split into
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two separate bit fields named "c0" and "c1", and the two fields are located in different registers. Each core has
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@ -82,11 +94,19 @@ void esp_cpu_unstall(int core_id)
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int rtc_cntl_c1_m = (core_id == 0) ? RTC_CNTL_SW_STALL_PROCPU_C1_M : RTC_CNTL_SW_STALL_APPCPU_C1_M;
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_c0_m);
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CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, rtc_cntl_c1_m);
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#endif
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#endif // CONFIG_IDF_TARGET_ESP32P4
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#endif // SOC_CPU_CORES_NUM > 1
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}
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void esp_cpu_reset(int core_id)
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{
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#if CONFIG_IDF_TARGET_ESP32P4
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//TODO: IDF-7848
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if (core_id == 0)
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REG_SET_BIT(LP_CLKRST_HPCPU_RESET_CTRL0_REG, LP_CLKRST_HPCORE0_SW_RESET);
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else
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REG_SET_BIT(LP_CLKRST_HPCPU_RESET_CTRL0_REG, LP_CLKRST_HPCORE1_SW_RESET);
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#else
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#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2// TODO: IDF-5645
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SET_PERI_REG_MASK(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET);
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#else
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@ -103,6 +123,7 @@ void esp_cpu_reset(int core_id)
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#endif // SOC_CPU_CORES_NUM > 1
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst_m);
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#endif
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#endif // CONFIG_IDF_TARGET_ESP32P4
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}
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void esp_cpu_wait_for_intr(void)
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@ -110,12 +131,15 @@ void esp_cpu_wait_for_intr(void)
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#if __XTENSA__
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xt_utils_wait_for_intr();
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#else
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//TODO: IDF-7848
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#if !CONFIG_IDF_TARGET_ESP32P4
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// TODO: IDF-5645 (better to implement with ll) C6 register names converted in the #include section at the top
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if (esp_cpu_dbgr_is_attached() && DPORT_REG_GET_BIT(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON) == 0) {
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/* when SYSTEM_CPU_WAIT_MODE_FORCE_ON is disabled in WFI mode SBA access to memory does not work for debugger,
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so do not enter that mode when debugger is connected */
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return;
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}
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#endif
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rv_utils_wait_for_intr();
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#endif // __XTENSA__
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}
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@ -57,12 +57,22 @@ FORCE_INLINE_ATTR void *rv_utils_get_sp(void)
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FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_get_cycle_count(void)
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{
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#if SOC_INT_CLIC_SUPPORTED
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//TODO: IDF-7848
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return RV_READ_CSR(mcycle);
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#else
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return RV_READ_CSR(CSR_PCCR_MACHINE);
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#endif
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}
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_set_cycle_count(uint32_t ccount)
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{
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#if SOC_INT_CLIC_SUPPORTED
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//TODO: IDF-7848
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RV_WRITE_CSR(mcycle, ccount);
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#else
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RV_WRITE_CSR(CSR_PCCR_MACHINE, ccount);
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#endif
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}
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/* ------------------------------------------------- CPU Interrupts ----------------------------------------------------
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