alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

fix(freertos): Use INTERRUPT_CURRENT_CORE_INT_THRESH_REG for esp32p4

Browse Source
This commit is contained in:
KonstantinKondrashov 2023-09-07 15:25:35 +08:00
parent 02b6c1f0ca
commit 25c7a59e31
10 changed files with 37 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h
View File

@ -193,7 +193,7 @@ extern void vTaskExitCritical( void );
#define portSET_INTERRUPT_MASK_FROM_ISR() ({ \
unsigned int cur_level; \
cur_level = REG_READ(INTERRUPT_CORE0_CPU_INT_THRESH_REG); \
cur_level = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG); \
vTaskEnterCritical(); \
cur_level; \
})
@ -293,7 +293,16 @@ void vPortExitCritical(void);
static inline bool IRAM_ATTR xPortCanYield(void)
{
uint32_t threshold = REG_READ(INTERRUPT_CORE0_CPU_INT_THRESH_REG);
uint32_t threshold = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
#if SOC_INT_CLIC_SUPPORTED
threshold = threshold >> (CLIC_CPU_INT_THRESH_S + (8 - NLBITS));
/* When CLIC is supported, the lowest interrupt threshold level is 0.
* Therefore, an interrupt threshold level above 0 would mean that we
* are either in a critical section or in an ISR.
*/
return (threshold == 0);
#endif /* SOC_INT_CLIC_SUPPORTED */
/* when enter critical code, FreeRTOS will mask threshold to RVHAL_EXCM_LEVEL
* and exit critical code, will recover threshold value (1). so threshold <= 1
* means not in critical code

7
components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c
View File

@ -9,6 +9,7 @@
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "soc/interrupt_reg.h"
#include "hal/systimer_hal.h"
#include "hal/systimer_ll.h"
#include "riscv/rvruntime-frames.h"
@ -122,8 +123,8 @@ UBaseType_t ulPortSetInterruptMask(void)
{
int ret;
unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
ret = REG_READ(INTERRUPT_CORE0_CPU_INT_THRESH_REG);
REG_WRITE(INTERRUPT_CORE0_CPU_INT_THRESH_REG, RVHAL_EXCM_LEVEL);
ret = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, RVHAL_EXCM_LEVEL);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
/**
* In theory, this function should not return immediately as there is a
@ -141,7 +142,7 @@ UBaseType_t ulPortSetInterruptMask(void)
void vPortClearInterruptMask(UBaseType_t mask)
{
REG_WRITE(INTERRUPT_CORE0_CPU_INT_THRESH_REG, mask);
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, mask);
/**
* The delay between the moment we unmask the interrupt threshold register
* and the moment the potential requested interrupt is triggered is not

2
components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h
View File

@ -638,7 +638,7 @@ static inline void __attribute__((always_inline)) vPortExitCriticalSafe(portMUX_
FORCE_INLINE_ATTR bool xPortCanYield(void)
{
uint32_t threshold = REG_READ(INTERRUPT_CORE0_CPU_INT_THRESH_REG);
uint32_t threshold = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
#if SOC_INT_CLIC_SUPPORTED
threshold = threshold >> (CLIC_CPU_INT_THRESH_S + (8 - NLBITS));

7
components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
View File

@ -41,6 +41,7 @@
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "soc/interrupt_reg.h"
#include "hal/systimer_hal.h"
#include "hal/systimer_ll.h"
#include "riscv/rvruntime-frames.h"
@ -367,8 +368,8 @@ UBaseType_t xPortSetInterruptMaskFromISR(void)
#if !SOC_INT_CLIC_SUPPORTED
unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
prev_int_level = REG_READ(INTERRUPT_CORE0_CPU_INT_THRESH_REG);
REG_WRITE(INTERRUPT_CORE0_CPU_INT_THRESH_REG, RVHAL_EXCM_LEVEL);
prev_int_level = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, RVHAL_EXCM_LEVEL);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
#else
/* When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */
@ -391,7 +392,7 @@ UBaseType_t xPortSetInterruptMaskFromISR(void)
void vPortClearInterruptMaskFromISR(UBaseType_t prev_int_level)
{
#if !SOC_INT_CLIC_SUPPORTED
REG_WRITE(INTERRUPT_CORE0_CPU_INT_THRESH_REG, prev_int_level);
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, prev_int_level);
#else
rv_utils_restore_intlevel(prev_int_level);
#endif /* SOC_INIT_CLIC_SUPPORTED */

6
components/riscv/vectors.S
View File

@ -230,7 +230,7 @@ _interrupt_handler:
#if !SOC_INT_HW_NESTED_SUPPORTED
/* Save the interrupt threshold level */
li t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
li t0, INTERRUPT_CURRENT_CORE_INT_THRESH_REG
lw s3, 0(t0)
/* Increase interrupt threshold level */
@ -241,7 +241,7 @@ _interrupt_handler:
add t1, t2, t1 /* t1 = INTC_INT_PRIO_REG + 4 * mcause */
lw t2, 0(t1) /* t2 = INTC_INT_PRIO_REG[mcause] */
addi t2, t2, 1 /* t2 = t2 +1 */
sw t2, 0(t0) /* INTERRUPT_CORE0_CPU_INT_THRESH_REG = t2 */
sw t2, 0(t0) /* INTERRUPT_CURRENT_CORE_INT_THRESH_REG = t2 */
fence
#endif // !SOC_INT_HW_NESTED_SUPPORTED
@ -281,7 +281,7 @@ _interrupt_handler:
#if !SOC_INT_HW_NESTED_SUPPORTED
/* restore the interrupt threshold level */
li t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
li t0, INTERRUPT_CURRENT_CORE_INT_THRESH_REG
sw s3, 0(t0)
fence
#endif // !SOC_INT_HW_NESTED_SUPPORTED

4
components/soc/esp32c2/include/soc/interrupt_reg.h
View File

@ -1,6 +1,8 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "interrupt_core0_reg.h"
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG

7
components/soc/esp32c3/include/soc/interrupt_reg.h
View File

@ -1 +1,8 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "interrupt_core0_reg.h"
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG

3
components/soc/esp32c6/include/soc/interrupt_reg.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,6 +10,7 @@
#include "soc/soc_caps.h"
// ESP32C6 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y)
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG

3
components/soc/esp32h2/include/soc/interrupt_reg.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,6 +9,7 @@
#include "soc/soc_caps.h"
// ESP32H2 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y)
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG

1
tools/ci/check_copyright_ignore.txt
View File

@ -681,7 +681,6 @@ components/soc/esp32c3/include/soc/gpio_struct.h
components/soc/esp32c3/include/soc/i2c_reg.h
components/soc/esp32c3/include/soc/i2c_struct.h
components/soc/esp32c3/include/soc/interrupt_core0_reg.h
components/soc/esp32c3/include/soc/interrupt_reg.h
components/soc/esp32c3/include/soc/ledc_reg.h
components/soc/esp32c3/include/soc/nrx_reg.h
components/soc/esp32c3/include/soc/reset_reasons.h