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riscv: fix trigger add from trap handlers

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This commit is contained in:
Alexey Lapshin 2023-04-19 20:19:40 +08:00
parent d41d12fe7a
commit a89b799642
1 changed files with 1 additions and 1 deletions
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2
components/riscv/include/riscv/rv_utils.h
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@ -132,7 +132,7 @@ FORCE_INLINE_ATTR void rv_utils_set_breakpoint(int bp_num, uint32_t bp_addr)
/* The code bellow sets breakpoint which will trigger `Breakpoint` exception
* instead transfering control to debugger. */
RV_WRITE_CSR(tselect, bp_num);
RV_WRITE_CSR(CSR_TCONTROL, TCONTROL_MTE);
RV_WRITE_CSR(CSR_TCONTROL, TCONTROL_MPTE | TCONTROL_MTE);
RV_WRITE_CSR(CSR_TDATA1, TDATA1_USER | TDATA1_MACHINE | TDATA1_EXECUTE);
RV_WRITE_CSR(tdata2, bp_addr);
}