The requirements of pin capabilites is different for spi master and
slave. The master needs CS, SCLK, MOSI to be output-able, while slave
needs MISO to be output-able.
Previous code is for master only.
This commit allows to place other 3 pins than MISO on input-only pins
for slaves. Refactoring for spi_common is also included.
Resolves https://github.com/espressif/esp-idf/issues/2455
New unit tests added
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**Local:** Local test uses the GPIO matrix to connect the master and the
slave on the same board. When the master needs the iomux, the master
uses the GPIOs of its own, the slave connect to the pins by GPIO matrix;
When the slave needs the iomux, the slave uses the GPIOs of its own, the
master connects to the pins by GPIO matrix.
- Provide a new unit test which performs freq scanning in mode 0. It
scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum
frequency allowed.
**M & S**: Master & slave tests performs the test with two boards. The
master and slave use iomux or gpio matrix according to the config.
- Provide a new unit test which performs freq scanning in mode 0. It
scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum
frequency allowed.
- Provide a new unit test which performs mode test with significant
frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum
frequency allowed.
New unity component can be used for testing other applications.
Upstream version of Unity is included as a submodule.
Utilities specific to ESP-IDF unit tests (partitions, leak checking
setup/teardown functions, etc) are kept only in unit-test-app.
Kconfig options are added to allow disabling certain Unity features.
The test is previously disabled for the requirement of external
connection. Now the signals are connected by internal connections.
Also change the failure logic of the test.
spi test: Prime the flash cache before each test to minimise flash cache misses.
VFS performance test: Increase the number of runs to minimise influence of an isolated bad run.
The address field should be placed at the highest bits of address and slv_wr_status registers. Instead of breaking the address into two parts and fill in each register, move the address to the highest bits and write to the registers respectively.
Breaking change: if you fill-in the SPI address filed in a previous version in some way and it works correctly, you still have to rewrite the address, in a more intuitive way.
