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synced 2024-10-05 20:47:46 -04:00
fix(spi_master): fix the bug that VSPI no respond when host changed
from HSPI to VSPI, and vice versa. fix the SPI control bits written wrong in the headers. TW#12123, Github#477
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@ -259,3 +259,64 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi][ignore]") {
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destroy_spi_bus(handle1);
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}
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TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)", "[spi]")
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{
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//spi config
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spi_bus_config_t bus_config;
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spi_device_interface_config_t device_config;
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spi_device_handle_t spi;
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spi_host_device_t host;
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int dma = 1;
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memset(&bus_config, 0, sizeof(spi_bus_config_t));
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memset(&device_config, 0, sizeof(spi_device_interface_config_t));
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bus_config.miso_io_num = -1;
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bus_config.mosi_io_num = 26;
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bus_config.sclk_io_num = 25;
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bus_config.quadwp_io_num = -1;
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bus_config.quadhd_io_num = -1;
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device_config.clock_speed_hz = 50000;
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device_config.mode = 0;
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device_config.spics_io_num = -1;
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device_config.queue_size = 1;
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device_config.flags = SPI_DEVICE_TXBIT_LSBFIRST | SPI_DEVICE_RXBIT_LSBFIRST;
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struct spi_transaction_t transaction = {
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.flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA,
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.length = 16,
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.tx_buffer = NULL,
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.rx_buffer = NULL,
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.tx_data = {0x04, 0x00}
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};
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//initialize for first host
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host = 1;
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assert(spi_bus_initialize(host, &bus_config, dma) == ESP_OK);
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assert(spi_bus_add_device(host, &device_config, &spi) == ESP_OK);
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printf("before first xmit\n");
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assert(spi_device_transmit(spi, &transaction) == ESP_OK);
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printf("after first xmit\n");
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assert(spi_bus_remove_device(spi) == ESP_OK);
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assert(spi_bus_free(host) == ESP_OK);
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//for second host and failed before
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host = 2;
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assert(spi_bus_initialize(host, &bus_config, dma) == ESP_OK);
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assert(spi_bus_add_device(host, &device_config, &spi) == ESP_OK);
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printf("before second xmit\n");
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// the original version (bit mis-written) stucks here.
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assert(spi_device_transmit(spi, &transaction) == ESP_OK);
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// test case success when see this.
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printf("after second xmit\n");
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}
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@ -958,7 +958,7 @@
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#define DPORT_CAN_CLK_EN (BIT(19))
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#define DPORT_I2C_EXT1_CLK_EN (BIT(18))
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#define DPORT_PWM0_CLK_EN (BIT(17))
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#define DPORT_SPI_CLK_EN (BIT(16))
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#define DPORT_SPI_CLK_EN_2 (BIT(16))
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#define DPORT_TIMERGROUP1_CLK_EN (BIT(15))
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#define DPORT_EFUSE_CLK_EN (BIT(14))
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#define DPORT_TIMERGROUP_CLK_EN (BIT(13))
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@ -968,7 +968,7 @@
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#define DPORT_RMT_CLK_EN (BIT(9))
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#define DPORT_UHCI0_CLK_EN (BIT(8))
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#define DPORT_I2C_EXT0_CLK_EN (BIT(7))
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#define DPORT_SPI_CLK_EN_2 (BIT(6))
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#define DPORT_SPI_CLK_EN (BIT(6))
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#define DPORT_UART1_CLK_EN (BIT(5))
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#define DPORT_I2S0_CLK_EN (BIT(4))
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#define DPORT_WDG_CLK_EN (BIT(3))
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@ -992,7 +992,7 @@
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#define DPORT_CAN_RST (BIT(19))
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#define DPORT_I2C_EXT1_RST (BIT(18))
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#define DPORT_PWM0_RST (BIT(17))
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#define DPORT_SPI_RST (BIT(16))
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#define DPORT_SPI_RST_2 (BIT(16))
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#define DPORT_TIMERGROUP1_RST (BIT(15))
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#define DPORT_EFUSE_RST (BIT(14))
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#define DPORT_TIMERGROUP_RST (BIT(13))
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@ -1002,7 +1002,7 @@
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#define DPORT_RMT_RST (BIT(9))
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#define DPORT_UHCI0_RST (BIT(8))
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#define DPORT_I2C_EXT0_RST (BIT(7))
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#define DPORT_SPI_RST_2 (BIT(6))
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#define DPORT_SPI_RST (BIT(6))
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#define DPORT_UART1_RST (BIT(5))
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#define DPORT_I2S0_RST (BIT(4))
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#define DPORT_WDG_RST (BIT(3))
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