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test(spi_master): add performance display for spi master.
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@ -728,3 +728,76 @@ TEST_CASE("SPI master variable cmd & addr test","[spi]")
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ESP_LOGI(MASTER_TAG, "test passed.");
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}
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#define RECORD_TIME_PREPARE() uint32_t __t1, __t2
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#define RECORD_TIME_START() do {__t1 = xthal_get_ccount();}while(0)
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#define RECORD_TIME_END(p_time) do{__t2 = xthal_get_ccount(); *p_time = (__t2-__t1)/240;}while(0)
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TEST_CASE("spi_speed","[spi]")
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{
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RECORD_TIME_PREPARE();
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uint32_t t_no_dma, t_dma;
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esp_err_t ret;
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spi_device_handle_t spi;
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spi_bus_config_t buscfg={
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.miso_io_num=PIN_NUM_MISO,
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.mosi_io_num=PIN_NUM_MOSI,
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.sclk_io_num=PIN_NUM_CLK,
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.quadwp_io_num=-1,
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.quadhd_io_num=-1
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};
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spi_device_interface_config_t devcfg={
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.clock_speed_hz=10*1000*1000, //currently only up to 4MHz for internel connect
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.mode=0, //SPI mode 0
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.spics_io_num=PIN_NUM_CS, //CS pin
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.queue_size=16, //We want to be able to queue 7 transactions at a time
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.pre_cb=NULL,
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.cs_ena_pretrans = 0,
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};
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//Initialize the SPI bus
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ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1);
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TEST_ASSERT(ret==ESP_OK);
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//Attach the LCD to the SPI bus
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ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi);
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TEST_ASSERT(ret==ESP_OK);
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spi_transaction_t trans = {
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.length = 1*8,
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.flags = SPI_TRANS_USE_TXDATA,
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};
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spi_device_transmit(spi, &trans);
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//only record the second time
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RECORD_TIME_START();
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spi_device_transmit(spi, &trans);
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RECORD_TIME_END(&t_dma);
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TEST_PERFORMANCE_LESS_THAN( SPI_PER_TRANS_NO_POLLING, "%d us", t_dma );
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TEST_ESP_OK( spi_bus_remove_device(spi) );
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TEST_ESP_OK( spi_bus_free(HSPI_HOST) );
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ret=spi_bus_initialize(HSPI_HOST, &buscfg, 0);
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TEST_ASSERT(ret==ESP_OK);
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//Attach the LCD to the SPI bus
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ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi);
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TEST_ASSERT(ret==ESP_OK);
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trans = (spi_transaction_t){
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.length = 1*8,
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.flags = SPI_TRANS_USE_TXDATA,
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};
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spi_device_transmit(spi, &trans);
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//only record the second time
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RECORD_TIME_START();
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spi_device_transmit(spi, &trans);
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RECORD_TIME_END(&t_no_dma);
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TEST_PERFORMANCE_LESS_THAN( SPI_PER_TRANS_NO_POLLING_NO_DMA, "%d us", t_no_dma );
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TEST_ESP_OK( spi_bus_remove_device(spi) );
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TEST_ESP_OK( spi_bus_free(HSPI_HOST) );
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}
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@ -13,3 +13,7 @@
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP 200
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE 130
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#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL 1000
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 30
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 25
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