Memprot functions are no longer placed by default in IRAM,
selecting ESP_PANIC_HANDLER_IRAM will still force panic related memprot
functions to be placed in IRAM.
esp_rom_spiflash_attach is called in cpu_start.c when it's
CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP.
This function will:
- reset MSPI
- configure MSPI IOs
- configure MSPI into slow read mode
Prior to this commit, this function is put quite late. It's OK for chips
earlier than C6. On C6 and H2, MMU registers are in SPI_MEM_x, so
resetting MSPI registers will also reset MMU registers.
After this commit, this funciton is called eariler, before
cpu_start.c: bootloader_init().
esp_execute_shared_stack_function always restored the stack watchpoint
regardless of CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK. This would lead
to an abondoned but active watchpoint on a former stack once the task
calling esp_execute_shared_stack_function is deleted, if
CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is inactive.
This has been fixed now.
Closes https://github.com/espressif/esp-idf/issues/10414
If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
registers (Flashboot protection included) will be re-enabled, and some
seconds later, will trigger an unintended reset.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
usb_serial_jtag: Improve the code for the issue of usb cdc device unable to work during sleep
Closes IDFGH-6887
See merge request espressif/esp-idf!20973
1. Remove RTC_CLOCK_BBPLL_POWER_ON_WITH_USB Kconfig option
During sleep, BBPLL clock always gets disabled
esp_restart does not disable BBPLL clock, so that first stage bootloader log can be printed
2. Add a new Kconfig option PM_NO_AUTO_LS_ON_USJ_CONNECTED
When this option is selected, IDF will constantly monitor USB CDC port connection status.
As long as it gets connected to a HOST, automatic light-sleep will not happen.
Closes https://github.com/espressif/esp-idf/issues/8507
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32h2
Initialize the pmu sleep machine constant when pmu is initialized, and calculate
the pmu sleep time adjustment value and hardware configuration value according
to the machine constant during system sleep.
Calibrate fast OSC before each sleep and use the calibration value to calculate
PMU hardware wait cycles when use the fast OSC as the work clock.
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
1. Fix deep sleep wakeup IOs can not be unhold issue
2. Correct hold related APIs' description
3. Fix gpio_force_hold_all API
docs: Add GPIO wakeup source to sleep_modes doc for ESP32C3 and C2
This commit removes the riscv_interrupts.h header is it has become redundant. The previously
exposed API has been handled as follows:
- "riscv_interrupt_enable()" and "riscv_interrupt_disable()" have been removed. These functions
were declarations only and never had any implementation.
- "riscv_global_interrupts_enable()" and "riscv_global_interrupts_disable()" renamed to
"rv_utils_intr_global_enable()" and "rv_utils_intr_global_disable()" respectively and now
placed in rv_utils.h
ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
For RISC-V and Xtensa targets, in case a panic needs to happen when
Task WDT is triggered (ESP_TASK_WDT_PANIC), the interruptee's stack
is now used for printing the backtrace.
Abort after Task Watchdog is triggered can happen on APP CPU (second core).
Functions used for burning this efuse would log, but at this point
esp_log is not initialized. Moved to a later point in the startup process.
Closes https://github.com/espressif/esp-idf/issues/9457
Blocking read from cdcacm VFS could return less bytes than requested.
This didn’t match the behaviour of other VFS drivers, and higher level
code could misbehave.
Previously, reset over USB CDC was done by calling esp_restart from
an interrupt handler. This works only until some restart hook function
is registered using esp_register_shutdown_handler, and the hook
function tries to do something that isn’t allowed in an interrupt
handler. One such case is with Wi-Fi. When Wi-Fi driver is installed,
it registers esp_wifi_stop as a shutdown handler function. However
esp_wifi_stop cannot be called from an ISR, and hence we shouldn’t
call esp_restart from an ISR either.
This commit modifies USB CDC driver to call esp_restart by posting it
to esp_timer task.
Closes https://github.com/espressif/esp-idf/issues/7404
Spinlocks themselves do not constitute critical sections as after a spinlock is acquired, interrupts
can remain enabled. However, there are some places where spinlocks are used direclty instead of using
the portMUX_TYPE and portENTER_CRITICAL_...() APIs. This commit fixes those calls.
- Remove esp_cpu_in_ocd_mode() from esp_cpu.h. Users should call esp_cpu_dbgr_is_attached() instead.
- Remove esp_cpu_get_ccount() from esp_cpu.h. Users should call esp_cpu_get_cycle_count() instead.
- Remove esp_cpu_set_ccount() from esp_cpu.h. Users should call esp_cpu_set_cycle_count() instead.
- Other IDF components updated to call esp_cpu_dbgr_is_attached(), esp_cpu_get_cycle_count() and esp_cpu_set_cycle_count() as well.
This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
The following two functions in bootloader_support are private now:
* esp_secure_boot_verify_sbv2_signature_block()
* esp_secure_boot_verify_rsa_signature_block()
They have been moved into private header files
inside bootloader_private/
* Removed bootloader_reset_reason.h and
bootloader_common_get_reset_reason() completely.
Alternative in ROM component is available.
* made esp_efuse.h independent of target-specific rom header
1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and clock bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
