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Merge branch 'bugfix/fix_part_of_modem_not_reset_when_power_on' into 'master'

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Coexistence: fix part of modem module not reset when power up

See merge request espressif/esp-idf!19849
This commit is contained in:
Jiang Jiang Jian 2022-10-18 11:13:10 +08:00
commit e08e2f071f
14 changed files with 101 additions and 62 deletions
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16
components/esp_phy/src/phy_init.c
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@ -32,12 +32,9 @@
#include "esp_rom_sys.h"
#include "soc/rtc_cntl_reg.h"
#if CONFIG_IDF_TARGET_ESP32C3
#include "soc/syscon_reg.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "soc/syscon_reg.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "soc/syscon_reg.h"
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#endif
#include "hal/efuse_hal.h"
@ -287,9 +284,12 @@ void IRAM_ATTR esp_wifi_bt_power_domain_on(void)
_lock_acquire(&s_wifi_bt_pd_controller.lock);
if (s_wifi_bt_pd_controller.count++ == 0) {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_WIFIBB_RST | SYSTEM_FE_RST);
CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_WIFIBB_RST | SYSTEM_FE_RST);
#if CONFIG_IDF_TARGET_ESP32
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU);
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU);
#else
SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU);
CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU);
#endif
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
}

16
components/esp_system/port/soc/esp32/system_internal.c
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@ -101,11 +101,17 @@ void IRAM_ATTR esp_restart_noos(void)
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \
DPORT_FE_RST | \
DPORT_WIFIMAC_RST | \
DPORT_BTBB_RST | \
DPORT_BTMAC_RST | \
DPORT_SDIO_RST | \
DPORT_SDIO_HOST_RST | \
DPORT_EMAC_RST | \
DPORT_MACPWR_RST | \
DPORT_RW_BTMAC_RST | \
DPORT_RW_BTLP_RST);
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
// Reset timer/spi/uart

15
components/esp_system/port/soc/esp32s2/system_internal.c
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@ -97,11 +97,16 @@ void IRAM_ATTR esp_restart_noos(void)
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \
DPORT_FE_RST | \
DPORT_WIFIMAC_RST | \
DPORT_BTBB_RST | \
DPORT_BTMAC_RST | \
DPORT_SDIO_RST | \
DPORT_EMAC_RST | \
DPORT_MACPWR_RST | \
DPORT_RW_BTMAC_RST | \
DPORT_RW_BTLP_RST);
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
// Reset timer/spi/uart

4
components/esp_wifi/esp32/esp_adapter.c
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@ -515,8 +515,8 @@ static void IRAM_ATTR timer_arm_us_wrapper(void *ptimer, uint32_t us, bool repea
static void wifi_reset_mac_wrapper(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_MAC_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_MAC_RST);
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIMAC_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIMAC_RST);
}
static void wifi_clock_enable_wrapper(void)

4
components/esp_wifi/esp32s2/esp_adapter.c
View File

@ -504,8 +504,8 @@ static void IRAM_ATTR timer_arm_us_wrapper(void *ptimer, uint32_t us, bool repea
static void wifi_reset_mac_wrapper(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_MAC_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_MAC_RST);
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIMAC_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIMAC_RST);
}
static void wifi_clock_enable_wrapper(void)

30
components/soc/esp32/include/soc/dport_reg.h
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@ -1065,17 +1065,25 @@
#define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0)
/* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_RW_BTLP_RST (BIT(10))
#define DPORT_RW_BTMAC_RST (BIT(9))
#define DPORT_MACPWR_RST (BIT(8))
#define DPORT_EMAC_RST (BIT(7))
#define DPORT_SDIO_HOST_RST (BIT(6))
#define DPORT_SDIO_RST (BIT(5))
#define DPORT_BTMAC_RST (BIT(4))
#define DPORT_BT_RST (BIT(3))
#define DPORT_MAC_RST (BIT(2))
#define DPORT_FE_RST (BIT(1))
#define DPORT_BB_RST (BIT(0))
#define DPORT_WIFIBB_RST BIT(0)
#define DPORT_FE_RST BIT(1)
#define DPORT_WIFIMAC_RST BIT(2)
#define DPORT_BTBB_RST BIT(3)
#define DPORT_BTMAC_RST BIT(4)
#define DPORT_SDIO_RST BIT(5)
#define DPORT_SDIO_HOST_RST BIT(6)
#define DPORT_EMAC_RST BIT(7)
#define DPORT_MACPWR_RST BIT(8)
#define DPORT_RW_BTMAC_RST BIT(9)
#define DPORT_RW_BTLP_RST BIT(10)
#define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \
DPORT_FE_RST | \
DPORT_WIFIMAC_RST | \
DPORT_BTBB_RST | \
DPORT_BTMAC_RST | \
DPORT_RW_BTMAC_RST | \
DPORT_RW_BTLP_RST)
#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4)
/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */

1
components/soc/esp32c2/include/soc/reg_base.h
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@ -14,7 +14,6 @@
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
#define DR_REG_DPORT_END 0x600d3FFC
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000

1
components/soc/esp32c3/include/soc/reg_base.h
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@ -17,7 +17,6 @@
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
#define DR_REG_DPORT_END 0x600d3FFC
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000

12
components/soc/esp32c3/include/soc/syscon_reg.h
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@ -193,6 +193,7 @@ extern "C" {
#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSTEM_WIFIBB_RST BIT(0)
@ -209,6 +210,17 @@ extern "C" {
#define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */
#define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */
#define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \
SYSTEM_FE_RST | \
SYSTEM_WIFIMAC_RST | \
SYSTEM_BTBB_RST | \
SYSTEM_BTMAC_RST | \
SYSTEM_RW_BTMAC_RST | \
SYSTEM_RW_BTLP_RST | \
SYSTEM_RW_BTMAC_REG_RST | \
SYSTEM_RW_BTLP_REG_RST | \
SYSTEM_BTBB_REG_RST)
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */

1
components/soc/esp32s2/include/soc/reg_base.h
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@ -20,7 +20,6 @@
#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
#define DR_REG_INTRUSION_BASE 0x3f4d0000
#define DR_REG_DPORT_END 0x3f4d3FFC
#define DR_REG_UART_BASE 0x3f400000
#define DR_REG_SPI1_BASE 0x3f402000
#define DR_REG_SPI0_BASE 0x3f403000

49
components/soc/esp32s2/include/soc/syscon_reg.h
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@ -1,16 +1,8 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
@ -469,23 +461,32 @@ extern "C" {
#define DPORT_CORE_RST_EN_REG DPORT_WIFI_RST_EN_REG
#define DPORT_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_WIFI_RST 0xFFFFFFFF
#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S))
#define DPORT_WIFI_RST_V 0xFFFFFFFF
#define DPORT_WIFI_RST_S 0
#define DPORT_RW_BTLP_RST (BIT(10))
#define DPORT_RW_BTMAC_RST (BIT(9))
#define DPORT_MACPWR_RST (BIT(8))
#define DPORT_EMAC_RST (BIT(7))
#define DPORT_SDIO_HOST_RST (BIT(6))
#define DPORT_SDIO_RST (BIT(5))
#define DPORT_BTMAC_RST (BIT(4))
#define DPORT_BT_RST (BIT(3))
#define DPORT_MAC_RST (BIT(2))
#define DPORT_FE_RST (BIT(1))
#define DPORT_BB_RST (BIT(0))
#define DPORT_WIFIBB_RST BIT(0)
#define DPORT_FE_RST BIT(1)
#define DPORT_WIFIMAC_RST BIT(2)
#define DPORT_BTBB_RST BIT(3)
#define DPORT_BTMAC_RST BIT(4)
#define DPORT_SDIO_RST BIT(5)
#define DPORT_EMAC_RST BIT(7)
#define DPORT_MACPWR_RST BIT(8)
#define DPORT_RW_BTMAC_RST BIT(9)
#define DPORT_RW_BTLP_RST BIT(10)
#define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \
DPORT_FE_RST | \
DPORT_WIFIMAC_RST | \
DPORT_BTBB_RST | \
DPORT_BTMAC_RST | \
DPORT_RW_BTMAC_RST | \
DPORT_RW_BTLP_RST)
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098)
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */

1
components/soc/esp32s3/include/soc/soc.h
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@ -25,7 +25,6 @@
#define DR_REG_ITAG_TABLE 0x600C6000
#define DR_REG_DTAG_TABLE 0x600C8000
#define DR_REG_EXT_MEM_ENC 0x600CC000
#define DR_REG_DPORT_END 0x600D3FFC
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)

12
components/soc/esp32s3/include/soc/syscon_reg.h
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@ -199,6 +199,7 @@ extern "C" {
#define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S))
#define SYSTEM_WIFI_RST_V 0xFFFFFFFF
#define SYSTEM_WIFI_RST_S 0
#define SYSTEM_WIFIBB_RST BIT(0)
#define SYSTEM_FE_RST BIT(1)
#define SYSTEM_WIFIMAC_RST BIT(2)
@ -213,6 +214,17 @@ extern "C" {
#define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */
#define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */
#define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \
SYSTEM_FE_RST | \
SYSTEM_WIFIMAC_RST | \
SYSTEM_BTBB_RST | \
SYSTEM_BTMAC_RST | \
SYSTEM_RW_BTMAC_RST | \
SYSTEM_RW_BTLP_RST | \
SYSTEM_RW_BTMAC_REG_RST | \
SYSTEM_RW_BTLP_REG_RST | \
SYSTEM_BTBB_REG_RST)
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C)
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: .*/

1
tools/ci/check_copyright_ignore.txt
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@ -1108,7 +1108,6 @@ components/soc/esp32s2/include/soc/soc_ulp.h
components/soc/esp32s2/include/soc/spi_mem_reg.h
components/soc/esp32s2/include/soc/spi_pins.h
components/soc/esp32s2/include/soc/spi_reg.h
components/soc/esp32s2/include/soc/syscon_reg.h
components/soc/esp32s2/include/soc/systimer_reg.h
components/soc/esp32s2/include/soc/systimer_struct.h
components/soc/esp32s2/include/soc/touch_sensor_channel.h