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Merge branch 'feature/c2_systimer_26mhz' into 'master'

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esp32c2: 26 MHz XTAL support: Kconfig option, systimer support

Closes IDF-5412 and IDF-5413

See merge request espressif/esp-idf!18835
This commit is contained in:
Song Ruo Jing 2022-07-11 16:17:25 +08:00
commit ea97cc93ea
34 changed files with 156 additions and 133 deletions
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5
components/bootloader_support/src/bootloader_clock_init.c
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@ -45,7 +45,10 @@ __attribute__((weak)) void bootloader_clock_configure(void)
#if CONFIG_IDF_TARGET_ESP32
clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
#endif
/* Except ESP32, there is no XTAL_FREQ choice */
#if CONFIG_IDF_TARGET_ESP32C2
clk_cfg.xtal_freq = CONFIG_ESP32C2_XTAL_FREQ;
#endif
/* For other chips, there is no XTAL_FREQ choice */
clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {

2
components/bootloader_support/src/bootloader_console.c
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@ -90,7 +90,7 @@ void bootloader_console_init(void)
// Set configured UART console baud rate
uint32_t clock_hz = rtc_clk_apb_freq_get();
#if ESP_ROM_UART_CLK_IS_XTAL
clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM
#endif
esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
}

21
components/esp_hw_support/port/esp32c2/Kconfig.hw_support Normal file
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@ -0,0 +1,21 @@
config ESP32C2_XTAL_FREQ
int
default 40 if ESP32C2_XTAL_FREQ_40
default 26 if ESP32C2_XTAL_FREQ_26
choice ESP32C2_XTAL_FREQ_SEL
prompt "Main XTAL frequency"
default ESP32C2_XTAL_FREQ_40
help
ESP32-C2 currently supports the following XTAL frequencies:
- 26 MHz
- 40 MHz
This option must be set to the correct value for the given hardware.
config ESP32C2_XTAL_FREQ_40 # TODO: IDF-5488
bool "40 MHz"
config ESP32C2_XTAL_FREQ_26
bool "26 MHz"
endchoice

4
components/esp_hw_support/port/esp32c2/rtc_clk.c
View File

@ -297,8 +297,8 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
return RTC_XTAL_FREQ_40M;
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_ESP32C2_XTAL_FREQ);
return CONFIG_ESP32C2_XTAL_FREQ;
}
return (rtc_xtal_freq_t)xtal_freq_mhz;
}

1
components/esp_system/Kconfig
View File

@ -331,6 +331,7 @@ menu "ESP System Settings"
int
prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
depends on ESP_CONSOLE_UART
default 74880 if ESP32C2_XTAL_FREQ_26
default 115200
range 1200 4000000 if !PM_ENABLE
range 1200 1000000 if PM_ENABLE

5
components/esp_system/port/cpu_start.c
View File

@ -21,6 +21,7 @@
#include "esp_rom_efuse.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp_rom_caps.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
@ -516,8 +517,8 @@ void IRAM_ATTR call_start_cpu0(void)
#ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
#ifdef CONFIG_ESP_CONSOLE_UART
uint32_t clock_hz = esp_clk_apb_freq();
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
#if ESP_ROM_UART_CLK_IS_XTAL
clock_hz = esp_clk_xtal_freq(); // From esp32-s3 on, UART clock source is selected to XTAL in ROM
#endif
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);

2
components/esp_system/port/soc/esp32c2/clk.c
View File

@ -71,7 +71,7 @@ static const char *TAG = "clk";
}
rtc_init(cfg);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
assert(rtc_clk_xtal_freq_get() == CONFIG_ESP32C2_XTAL_FREQ);
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);

10
components/esp_timer/src/esp_timer_impl_systimer.c
View File

@ -64,7 +64,7 @@ uint64_t IRAM_ATTR esp_timer_impl_get_counter_reg(void)
int64_t IRAM_ATTR esp_timer_impl_get_time(void)
{
return systimer_hal_get_counter_value(&systimer_hal, SYSTIMER_LL_COUNTER_CLOCK) / SYSTIMER_LL_TICKS_PER_US;
return systimer_hal_get_counter_value(&systimer_hal, SYSTIMER_LL_COUNTER_CLOCK) * SYSTIMER_LL_TICKS_PER_US_DIV / SYSTIMER_LL_TICKS_PER_US;
}
int64_t esp_timer_get_time(void) __attribute__((alias("esp_timer_impl_get_time")));
@ -96,7 +96,7 @@ static void IRAM_ATTR timer_alarm_isr(void *arg)
void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)
{
#if !SOC_SYSTIMER_FIXED_TICKS_US
#if !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
systimer_hal_on_apb_freq_update(&systimer_hal, apb_ticks_per_us);
#endif
}
@ -104,7 +104,9 @@ void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)
void esp_timer_impl_set(uint64_t new_us)
{
portENTER_CRITICAL_SAFE(&s_time_update_lock);
systimer_counter_value_t new_count = { .val = new_us * SYSTIMER_LL_TICKS_PER_US };
systimer_counter_value_t new_count = {
.val = new_us * SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV
};
systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_CLOCK, new_count.val);
systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_CLOCK);
portEXIT_CRITICAL_SAFE(&s_time_update_lock);
@ -121,7 +123,7 @@ esp_err_t esp_timer_impl_early_init(void)
{
systimer_hal_init(&systimer_hal);
#if !SOC_SYSTIMER_FIXED_TICKS_US
#if !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
assert(esp_clk_xtal_freq() == (40 * 1000000) &&
"update the step for xtal to support other XTAL:APB frequency ratios");
systimer_hal_set_steps_per_tick(&systimer_hal, 0, 2); // for xtal

2
components/hal/Kconfig
View File

@ -67,7 +67,7 @@ menu "Hardware Abstraction Layer (HAL) and Low Level (LL)"
config HAL_SYSTIMER_USE_ROM_IMPL
bool "Use ROM implementation of SysTimer HAL driver"
depends on ESP_ROM_HAS_HAL_SYSTIMER
depends on ESP_ROM_HAS_HAL_SYSTIMER && !ESP32C2_XTAL_FREQ_26
default y
help
Enable this flag to use HAL functions from ROM instead of ESP-IDF.

7
components/hal/esp32c2/include/hal/systimer_ll.h
View File

@ -9,13 +9,20 @@
#include <stdbool.h>
#include "soc/systimer_struct.h"
#include "hal/assert.h"
#include "sdkconfig.h"
#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time
#define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick
#define SYSTIMER_LL_ALARM_OS_TICK_CORE0 (0) // Alarm used for OS tick of CPU core 0
#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time
#ifdef CONFIG_ESP32C2_XTAL_FREQ_26
#define SYSTIMER_LL_TICKS_PER_US (52) // (26 / 2.5) = 10.4 = 52/5 systimer ticks per us
#define SYSTIMER_LL_TICKS_PER_US_DIV (5)
#else
#define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us
#define SYSTIMER_LL_TICKS_PER_US_DIV (1)
#endif // ESP32C2_XTAL_FREQ_*
#ifdef __cplusplus
extern "C" {

3
components/hal/esp32c2/include/hal/uart_ll.h
View File

@ -11,6 +11,7 @@
#pragma once
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "hal/clk_tree_ll.h"
#ifdef __cplusplus
extern "C" {
@ -157,7 +158,7 @@ static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
case 2:
return RTC_CLK_FREQ;
case 3:
return XTAL_CLK_FREQ;
return clk_ll_xtal_load_freq_mhz() * MHZ;
}
}

19
components/hal/esp32c3/include/hal/systimer_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
@ -24,6 +16,7 @@
#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time
#define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us
#define SYSTIMER_LL_TICKS_PER_US_DIV (1)
#ifdef __cplusplus
extern "C" {

1
components/hal/esp32h2/include/hal/systimer_ll.h
View File

@ -16,6 +16,7 @@
#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time
#define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us
#define SYSTIMER_LL_TICKS_PER_US_DIV (1)
#ifdef __cplusplus
extern "C" {

19
components/hal/esp32s2/include/hal/systimer_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
@ -22,6 +14,7 @@
#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time
#define SYSTIMER_LL_TICKS_PER_US (80) // 80 systimer ticks == 1us
#define SYSTIMER_LL_TICKS_PER_US_DIV (1)
#ifdef __cplusplus
extern "C" {

19
components/hal/esp32s3/include/hal/systimer_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
@ -25,6 +17,7 @@
#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time
#define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us
#define SYSTIMER_LL_TICKS_PER_US_DIV (1)
#ifdef __cplusplus
extern "C" {

20
components/hal/include/hal/systimer_hal.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -93,7 +85,7 @@ void systimer_hal_connect_alarm_counter(systimer_hal_context_t *hal, uint32_t al
*/
void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t counter_id, uint32_t cpu_id, bool can);
#if !SOC_SYSTIMER_FIXED_TICKS_US
#if !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
/**
* @brief set increase steps for systimer counter on different clock source
*/

13
components/hal/platform_port/include/hal/regi2c_ctrl.h
View File

@ -17,5 +17,16 @@
#include "esp_private/regi2c_ctrl.h"
#else
#include "esp_rom_regi2c.h"
#define REGI2C_WRITE_MASK(block, reg_add, indata) esp_rom_regi2c_write_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
esp_rom_regi2c_write_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_WRITE(block, reg_add, indata) \
esp_rom_regi2c_write(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ_MASK(block, reg_add) \
esp_rom_regi2c_read_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_READ(block, reg_add) \
esp_rom_regi2c_read(block, block##_HOSTID, reg_add)
#endif

28
components/hal/systimer_hal.c
View File

@ -47,19 +47,25 @@ uint64_t systimer_hal_get_counter_value(systimer_hal_context_t *hal, uint32_t co
uint64_t systimer_hal_get_time(systimer_hal_context_t *hal, uint32_t counter_id)
{
return systimer_hal_get_counter_value(hal, counter_id) / SYSTIMER_LL_TICKS_PER_US;
return systimer_hal_get_counter_value(hal, counter_id) * SYSTIMER_LL_TICKS_PER_US_DIV / SYSTIMER_LL_TICKS_PER_US;
}
#if SOC_SYSTIMER_ALARM_MISS_COMPENSATE
void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t target)
{
systimer_counter_value_t alarm = { .val = target * SYSTIMER_LL_TICKS_PER_US};
systimer_counter_value_t alarm = {
.val = target * SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV
};
systimer_ll_enable_alarm(hal->dev, alarm_id, false);
systimer_ll_set_alarm_target(hal->dev, alarm_id, alarm.val);
systimer_ll_apply_alarm_value(hal->dev, alarm_id);
systimer_ll_enable_alarm(hal->dev, alarm_id, true);
}
#else
#else // SOC_SYSTIMER_ALARM_MISS_COMPENSATE
_Static_assert(SYSTIMER_LL_TICKS_PER_US_DIV == 1, "SYSTIMER_LL_TICKS_PER_US_DIV > 1 && !SOC_SYSTIMER_ALARM_MISS_COMPENSATE hasn't been supported");
void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t timestamp)
{
int64_t offset = SYSTIMER_LL_TICKS_PER_US * 2;
@ -81,12 +87,12 @@ void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_i
}
} while (1);
}
#endif
#endif // SOC_SYSTIMER_ALARM_MISS_COMPENSATE
void systimer_hal_set_alarm_period(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t period)
{
systimer_ll_enable_alarm(hal->dev, alarm_id, false);
systimer_ll_set_alarm_period(hal->dev, alarm_id, period * SYSTIMER_LL_TICKS_PER_US);
systimer_ll_set_alarm_period(hal->dev, alarm_id, period * SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV);
systimer_ll_apply_alarm_value(hal->dev, alarm_id);
systimer_ll_enable_alarm(hal->dev, alarm_id, true);
}
@ -103,7 +109,10 @@ void systimer_hal_enable_alarm_int(systimer_hal_context_t *hal, uint32_t alarm_i
void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t counter_id, int64_t time_us)
{
systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(hal, counter_id) + time_us * SYSTIMER_LL_TICKS_PER_US };
systimer_counter_value_t new_count = {
.val = systimer_hal_get_counter_value(hal, counter_id)
+ time_us * SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV
};
systimer_ll_set_counter_value(hal->dev, counter_id, new_count.val);
systimer_ll_apply_counter_value(hal->dev, counter_id);
}
@ -137,7 +146,10 @@ void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t
systimer_ll_counter_can_stall_by_cpu(hal->dev, counter_id, cpu_id, can);
}
#if !SOC_SYSTIMER_FIXED_TICKS_US
#if !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
_Static_assert(SYSTIMER_LL_TICKS_PER_US_DIV == 1, "SYSTIMER_LL_TICKS_PER_US_DIV > 1 && !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US hasn't been supported");
void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps)
{
/* Configure the counter:
@ -171,4 +183,4 @@ void systimer_hal_on_apb_freq_update(systimer_hal_context_t *hal, uint32_t apb_t
systimer_ll_set_step_for_xtal(hal->dev, SYSTIMER_LL_TICKS_PER_US / apb_ticks_per_us);
}
}
#endif
#endif // !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US

6
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@ -411,9 +411,9 @@ config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_TICKS_US
int
default 16
config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
bool
default y
config SOC_SYSTIMER_INT_LEVEL
bool

8
components/soc/esp32c2/include/soc/clk_tree_defs.h
View File

@ -19,7 +19,7 @@ extern "C" {
*
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
*
* 2) External 40MHz Crystal Clock: XTAL
* 2) External 26/40MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
*
@ -50,7 +50,7 @@ extern "C" {
typedef enum {
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
SOC_ROOT_CLK_EXT_XTAL, /*!< External 26/40MHz crystal */
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */
} soc_root_clk_t;
@ -60,7 +60,7 @@ typedef enum {
*/
typedef enum {
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 26/40MHz crystal oscillator frequency multiplier, 480MHz) */
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
@ -108,7 +108,7 @@ typedef enum {
SOC_MOD_CLK_OSC_SLOW, /*!< OSC_SLOW_CLK comes from an external slow clock signal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 26/40MHz crystal */
} soc_module_clk_t;

2
components/soc/esp32c2/include/soc/soc.h
View File

@ -142,13 +142,11 @@
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM ( 40*1000000)
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 )
#define REF_CLK_FREQ ( 1000000 )
#define RTC_CLK_FREQ (20*1000000)
#define XTAL_CLK_FREQ (40*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 4

16
components/soc/esp32c2/include/soc/soc_caps.h
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@ -203,14 +203,14 @@
#define SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us if 40MHz XTAL; 10.4 ticks/us if 26MHz XTAL)
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (1U)

6
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
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@ -603,9 +603,9 @@ config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_TICKS_US
int
default 16
config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
bool
default y
config SOC_SYSTIMER_INT_LEVEL
bool

1
components/soc/esp32c3/include/soc/soc.h
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@ -135,7 +135,6 @@
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM ( 40*1000000)
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#if CONFIG_IDF_ENV_FPGA

16
components/soc/esp32c3/include/soc/soc_caps.h
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@ -283,14 +283,14 @@
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us)
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)

6
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@ -579,9 +579,9 @@ config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_TICKS_US
int
default 16
config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
bool
default y
config SOC_SYSTIMER_INT_LEVEL
bool

1
components/soc/esp32h2/include/soc/soc.h
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@ -135,7 +135,6 @@
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 32*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM ( 32*1000000)
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#if CONFIG_IDF_ENV_FPGA

16
components/soc/esp32h2/include/soc/soc_caps.h
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@ -288,14 +288,14 @@
#define SOC_MEMSPI_SRC_FREQ_12M_SUPPORTED 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us)
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)

1
components/soc/esp32s2/include/soc/soc.h
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@ -142,7 +142,6 @@
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
#define REF_CLK_FREQ ( 1000000 )

6
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
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@ -679,9 +679,9 @@ config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_TICKS_US
int
default 16
config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
bool
default y
config SOC_SYSTIMER_INT_LEVEL
bool

1
components/soc/esp32s3/include/soc/soc.h
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@ -152,7 +152,6 @@
//Periheral Clock {{
#define APB_CLK_FREQ_ROM (40*1000000)
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM (40*1000000)
#define EFUSE_CLK_FREQ_ROM (20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ (80*1000000)

16
components/soc/esp32s3/include/soc/soc_caps.h
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@ -277,14 +277,14 @@
#define SOC_SPIRAM_SUPPORTED 1
/*-------------------------- SYS TIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us)
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
#define SOC_TIMER_GROUPS (2)

4
tools/ci/check_copyright_ignore.txt
View File

@ -758,7 +758,6 @@ components/hal/esp32c3/include/hal/rtc_cntl_ll.h
components/hal/esp32c3/include/hal/sha_ll.h
components/hal/esp32c3/include/hal/sigmadelta_ll.h
components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32c3/include/hal/systimer_ll.h
components/hal/esp32c3/include/hal/uhci_ll.h
components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h
components/hal/esp32c3/rtc_cntl_hal.c
@ -785,7 +784,6 @@ components/hal/esp32s2/include/hal/rtc_io_ll.h
components/hal/esp32s2/include/hal/sha_ll.h
components/hal/esp32s2/include/hal/sigmadelta_ll.h
components/hal/esp32s2/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32s2/include/hal/systimer_ll.h
components/hal/esp32s2/include/hal/trace_ll.h
components/hal/esp32s2/include/hal/usb_ll.h
components/hal/esp32s2/touch_sensor_hal.c
@ -795,7 +793,6 @@ components/hal/esp32s3/include/hal/rwdt_ll.h
components/hal/esp32s3/include/hal/sha_ll.h
components/hal/esp32s3/include/hal/sigmadelta_ll.h
components/hal/esp32s3/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32s3/include/hal/systimer_ll.h
components/hal/esp32s3/include/hal/uhci_ll.h
components/hal/esp32s3/include/hal/usb_ll.h
components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
@ -815,7 +812,6 @@ components/hal/include/hal/sigmadelta_hal.h
components/hal/include/hal/spi_flash_encrypt_hal.h
components/hal/include/hal/spi_slave_hal.h
components/hal/include/hal/spi_slave_hd_hal.h
components/hal/include/hal/systimer_hal.h
components/hal/include/hal/twai_types.h
components/hal/include/hal/uhci_types.h
components/hal/include/hal/usb_hal.h

2
tools/test_apps/system/build_test/sdkconfig.ci.esp32c2_26mhz_xtal Normal file
View File

@ -0,0 +1,2 @@
CONFIG_IDF_TARGET="esp32c2"
CONFIG_ESP32C2_XTAL_FREQ_26=y