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https://github.com/espressif/esp-idf.git
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clk: Add basic clock support for esp32h2
This commit is contained in:
Song Ruo Jing
parent
b23eb428d1
commit
981d6a67b0
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -31,14 +31,13 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
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uint32_t rtc_clk_slow_freq_get_hz(void)
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{
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// ESP32H2-TODO: IDF-6254
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switch (rtc_clk_slow_freq_get()) {
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case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
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case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
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case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
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default: return 0;
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX;
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default: return 0;
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}
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return 0;
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}
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void rtc_clk_cpu_freq_set_xtal(void)
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -34,28 +34,7 @@
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#define MHZ (1000000)
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/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL.
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* The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6.
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*/
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#define MIN_32K_XTAL_CAL_VAL 15000000L
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/* Indicates that this 32k oscillator gets input from external oscillator, rather
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* than a crystal.
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*/
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#define EXT_OSC_FLAG BIT(3)
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/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define
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* an extra enum member for the external 32k oscillator.
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* For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values.
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*/
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typedef enum {
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SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator
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SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL
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SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256
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SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
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} slow_clk_sel_t;
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static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
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static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
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static const char *TAG = "clk";
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@ -100,13 +79,13 @@ static const char *TAG = "clk";
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#endif
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#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
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select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
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select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
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#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
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select_rtc_slow_clk(SLOW_CLK_8MD256);
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
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#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC32K);
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#else
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select_rtc_slow_clk(SLOW_CLK_RTC);
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
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#endif
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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@ -138,7 +117,7 @@ static const char *TAG = "clk";
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esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
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}
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static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
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static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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{
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ESP_EARLY_LOGW(TAG, "select_rtc_slow_clk() has not been implemented yet");
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#if 0// ESP32H2-TODO : IDF-5645
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@ -197,7 +176,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
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void rtc_clk_select_rtc_slow_clk(void)
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{
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select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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}
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/* This function is not exposed as an API at this point.
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -120,7 +120,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
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{
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switch (source_clk) {
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default:
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case UART_SCLK_APB:
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case UART_SCLK_PLL_F48M:
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hw->clk_conf.sclk_sel = 1;
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break;
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case UART_SCLK_RTC:
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@ -145,7 +145,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
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switch (hw->clk_conf.sclk_sel) {
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default:
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case 1:
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*source_clk = UART_SCLK_APB;
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*source_clk = UART_SCLK_PLL_F48M;
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break;
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case 2:
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*source_clk = UART_SCLK_RTC;
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -63,7 +63,7 @@ typedef enum {
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SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
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SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
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SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
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SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0, only support 32.768 kHz currently */
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SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */
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} soc_root_clk_t;
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/**
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@ -113,11 +113,11 @@ typedef enum {
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SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
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// For RTC domain
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SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
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SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
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SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
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// For digital domain: peripherals, WIFI, BLE
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SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
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SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
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SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL, and has a fixed frequency of 240MHz */
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SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 80MHz */
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SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 160MHz */
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SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 240MHz */
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SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
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SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -164,7 +164,7 @@ typedef enum {
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RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator
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RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock
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RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock
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RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External 32kHz clk signal input by lp_pad_gpio0, as one type of 32k clock
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RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
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RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator
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} rtc_cal_sel_t;
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@ -793,7 +793,7 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
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*/
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typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
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#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL
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#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M or 320M)
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#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M)
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#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
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/**
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@ -802,7 +802,6 @@ typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
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typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
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#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator
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#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL
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#define RTC_SLOW_FREQ_8MD256 SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 //!< Internal 17.5 MHz RC oscillator, divided by 256
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/**
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* @brief RTC FAST_CLK frequency values
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@ -815,7 +814,6 @@ typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
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#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
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#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX
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#define RTC_SLOW_CLK_FREQ_8MD256 SOC_CLK_RC_FAST_D256_FREQ_APPROX
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#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX
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/* Alias of deprecated function names */
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@ -703,10 +703,6 @@ config SOC_UART_BITRATE_MAX
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int
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default 5000000
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config SOC_UART_SUPPORT_APB_CLK
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bool
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default y
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config SOC_UART_SUPPORT_RTC_CLK
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bool
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default n
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -11,38 +11,46 @@
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extern "C" {
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#endif
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// TODO: IDF-6265 Copied from C6, need to update
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/*
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************************* ESP32H2 Root Clock Source ****************************
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* 1) Internal 17.5MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description)
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* 1) Internal 8MHz RC Oscillator: RC_FAST (usually referred as FOSC in TRM and reg. description)
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*
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* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
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* The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock
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* frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description).
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* This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK.
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*
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* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
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* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
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*
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* 2) External 40MHz Crystal Clock: XTAL
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* 2) External 32MHz Crystal Clock: XTAL
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*
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* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
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* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as SOSC in TRM or reg. description)
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*
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* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
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* can be computed in runtime through calibration.
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*
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* 4) External 32kHz Crystal Clock (optional): XTAL32K
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* 4) Internal 32kHz RC Oscillator: RC32K
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*
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* The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
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* pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the
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* XTAL_32K_P pin.
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* The exact frequency of this clock can be computed in runtime through calibration.
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*
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* 5) External 32kHz Crystal Clock (optional): XTAL32K
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*
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* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
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* pins.
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*
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* XTAL32K_CLK can also be calibrated to get its exact frequency.
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*
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* 6) External Slow Clock (optional): OSC_SLOW
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*
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* A slow clock signal generated by an external circuit can be connected to GPIO13 to be the clock source for the
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* RTC_SLOW_CLK.
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*
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* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
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*/
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/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
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#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
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/* With the default value of CK8M_DFREQ = 600, RC_FAST clock frequency is 7 MHz +/- 7% */
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#define SOC_CLK_RC_FAST_FREQ_APPROX 7000000 /*!< Approximate RC_FAST_CLK frequency in Hz */
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#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
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#define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */
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#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
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#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
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#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
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// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
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// {loc}: EXT, INT
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@ -52,10 +60,12 @@ extern "C" {
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* @brief Root clock
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*/
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typedef enum {
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SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
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SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 8.5MHz RC oscillator */
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SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
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SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
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SOC_ROOT_CLK_EXT_XTAL, /*!< External 32MHz crystal */
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SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */
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SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
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SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin13 */
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} soc_root_clk_t;
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/**
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@ -64,8 +74,9 @@ typedef enum {
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*/
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typedef enum {
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SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */
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SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
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SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_PLL2 = 3, /*!< Select PLL2_CLK as CPU_CLK source (PLL2_CLK is the output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
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SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
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} soc_cpu_clk_src_t;
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@ -76,7 +87,8 @@ typedef enum {
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typedef enum {
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SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 2, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_RC32K = 3, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
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} soc_rtc_slow_clk_src_t;
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@ -85,14 +97,14 @@ typedef enum {
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
|
||||
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: APB, (BB)PLL, etc.
|
||||
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
/**
|
||||
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
|
||||
@ -101,18 +113,16 @@ typedef enum {
|
||||
*/
|
||||
typedef enum {
|
||||
// For CPU domain
|
||||
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
|
||||
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or PLL2 by configuring soc_cpu_clk_src_t */
|
||||
// For RTC domain
|
||||
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
|
||||
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
|
||||
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */
|
||||
// For digital domain: peripherals, WIFI, BLE
|
||||
SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
|
||||
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
|
||||
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
|
||||
SOC_MOD_CLK_PLL_D2, /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */
|
||||
SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 48MHz */
|
||||
SOC_MOD_CLK_PLL_F64M, /*!< PLL_F64M_CLK is derived from PLL2 (w/ CG), and has a fixed frequency of 64MHz */
|
||||
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 96MHz */
|
||||
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
|
||||
} soc_module_clk_t;
|
||||
|
||||
@ -144,19 +154,20 @@ typedef enum {
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL}
|
||||
#else
|
||||
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
|
||||
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of GPTimer clock source
|
||||
*/
|
||||
typedef enum {
|
||||
GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
|
||||
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
GPTIMER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
|
||||
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
|
||||
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
|
||||
#else
|
||||
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
|
||||
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */
|
||||
#endif
|
||||
} soc_periph_gptimer_clk_src_t;
|
||||
|
||||
@ -164,9 +175,9 @@ typedef enum {
|
||||
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
|
||||
*/
|
||||
typedef enum {
|
||||
TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group clock source is APB */
|
||||
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
|
||||
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group clock source default choice is APB */
|
||||
TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source is PLL_F48M */
|
||||
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
|
||||
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */
|
||||
} soc_periph_tg_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
|
||||
@ -177,29 +188,24 @@ typedef enum {
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL}
|
||||
#else
|
||||
#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
|
||||
#define SOC_RMT_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of RMT clock source
|
||||
*/
|
||||
typedef enum {
|
||||
RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
|
||||
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
|
||||
#else
|
||||
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
|
||||
#endif
|
||||
} soc_periph_rmt_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Type of RMT clock source, reserved for the legacy RMT driver
|
||||
*/
|
||||
typedef enum {
|
||||
RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB */
|
||||
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
|
||||
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
|
||||
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
|
||||
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
|
||||
} soc_periph_rmt_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
|
||||
@ -224,10 +230,10 @@ typedef enum {
|
||||
* @brief Type of UART clock source, reserved for the legacy UART driver
|
||||
*/
|
||||
typedef enum {
|
||||
UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */
|
||||
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
|
||||
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
|
||||
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
|
||||
UART_SCLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock is PLL_F48M */
|
||||
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
|
||||
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
|
||||
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock default choice is PLL_F48M */
|
||||
} soc_periph_uart_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
|
||||
@ -235,36 +241,36 @@ typedef enum {
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of MCPWM Timer
|
||||
*/
|
||||
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
|
||||
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of MCPWM timer clock source
|
||||
*/
|
||||
typedef enum {
|
||||
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
|
||||
MCPWM_TIMER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
|
||||
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
|
||||
#else
|
||||
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
|
||||
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
|
||||
#endif
|
||||
} soc_periph_mcpwm_timer_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
|
||||
*/
|
||||
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
|
||||
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of MCPWM capture clock source
|
||||
*/
|
||||
typedef enum {
|
||||
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
|
||||
MCPWM_CAPTURE_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
|
||||
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
|
||||
#else
|
||||
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
|
||||
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
|
||||
#endif
|
||||
} soc_periph_mcpwm_capture_clk_src_t;
|
||||
|
||||
@ -276,7 +282,7 @@ typedef enum {
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL}
|
||||
#else
|
||||
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
|
||||
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_XTAL}
|
||||
#endif
|
||||
|
||||
/**
|
||||
@ -286,9 +292,10 @@ typedef enum {
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
|
||||
#else
|
||||
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
|
||||
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */
|
||||
#endif
|
||||
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
|
||||
I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
|
||||
I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */
|
||||
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
} soc_periph_i2s_clk_src_t;
|
||||
|
||||
@ -313,14 +320,15 @@ typedef enum {
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of SDM
|
||||
*/
|
||||
#define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
|
||||
#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Sigma Delta Modulator clock source
|
||||
*/
|
||||
typedef enum {
|
||||
SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
|
||||
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
|
||||
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
|
||||
SDM_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
|
||||
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the default clock choice */
|
||||
} soc_periph_sdm_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
|
||||
@ -328,7 +336,7 @@ typedef enum {
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of Glitch Filter
|
||||
*/
|
||||
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
|
||||
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Glitch filter clock source
|
||||
@ -336,8 +344,8 @@ typedef enum {
|
||||
|
||||
typedef enum {
|
||||
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
|
||||
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
|
||||
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
|
||||
GLITCH_FILTER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
|
||||
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the default clock choice */
|
||||
} soc_periph_glitch_filter_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
|
||||
@ -361,7 +369,7 @@ typedef enum {
|
||||
* @brief Array initializer for all supported clock sources of ADC digital controller
|
||||
*/
|
||||
// TODO: temporary support, need to check while supporting
|
||||
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M}
|
||||
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M}
|
||||
|
||||
/**
|
||||
* @brief ADC digital controller clock source
|
||||
@ -369,11 +377,11 @@ typedef enum {
|
||||
// TODO: temporary support, need to check while supporting
|
||||
typedef enum {
|
||||
ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
|
||||
ADC_DIGI_CLK_SRC_PLL_F96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
|
||||
#else
|
||||
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
|
||||
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
|
||||
#endif
|
||||
} soc_periph_adc_digi_clk_src_t;
|
||||
|
||||
|
||||
@ -46,13 +46,14 @@ extern "C" {
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
|
||||
#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
// TODO: IDF-6254
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
*/
|
||||
@ -74,9 +75,10 @@ extern "C" {
|
||||
#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300
|
||||
#define SOC_DELAY_RC_FAST_ENABLE 50
|
||||
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
|
||||
#define SOC_DELAY_RC32K_ENABLE 300
|
||||
|
||||
/* Core voltage:
|
||||
* Currently, ESP32C3 never adjust its wake voltage in runtime
|
||||
/* Core voltage: //TODO: IDF-6254
|
||||
* Currently, ESP32H2 never adjust its wake voltage in runtime
|
||||
* Only sets dig/rtc voltage dbias at startup time
|
||||
*/
|
||||
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
|
||||
@ -89,8 +91,9 @@ extern "C" {
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 600
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
@ -132,7 +135,6 @@ storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_32M = 32,
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
@ -152,12 +154,18 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
/**
|
||||
* @brief Clock source to be calibrated using rtc_clk_cal function
|
||||
*
|
||||
* @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL
|
||||
* However, this is not true on ESP32H2. The conversion to register field values is explicitly done in
|
||||
* rtc_clk_cal_internal
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
|
||||
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
|
||||
RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
|
||||
RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
|
||||
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
|
||||
RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator
|
||||
RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock
|
||||
RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock
|
||||
RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpiox, as one type of 32k clock
|
||||
RTC_CAL_RC_FAST //!< Internal 8MHz RC oscillator
|
||||
} rtc_cal_sel_t;
|
||||
|
||||
/**
|
||||
@ -167,25 +175,27 @@ typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose
|
||||
uint32_t clk_rtc_clk_div : 8;
|
||||
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
|
||||
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
|
||||
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
|
||||
uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~8MHz frequency)
|
||||
uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency)
|
||||
uint32_t clk_8m_dfreq : 10; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
|
||||
uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency)
|
||||
} rtc_clk_config_t;
|
||||
|
||||
/**
|
||||
* Default initializer for rtc_clk_config_t
|
||||
*/
|
||||
#define RTC_CLK_CONFIG_DEFAULT() { \
|
||||
.xtal_freq = RTC_XTAL_FREQ_40M, \
|
||||
.cpu_freq_mhz = 80, \
|
||||
.xtal_freq = RTC_XTAL_FREQ_32M, \
|
||||
.cpu_freq_mhz = 96, \
|
||||
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
|
||||
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
|
||||
.clk_rtc_clk_div = 0, \
|
||||
.clk_8m_clk_div = 0, \
|
||||
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
|
||||
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
|
||||
.rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
@ -798,8 +808,8 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
|
||||
*/
|
||||
typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
|
||||
#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL
|
||||
#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M or 320M)
|
||||
#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
|
||||
#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (96M)
|
||||
#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 8M RTC oscillator
|
||||
|
||||
/**
|
||||
* @brief RTC SLOW_CLK frequency values
|
||||
@ -807,20 +817,18 @@ typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
|
||||
typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
|
||||
#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator
|
||||
#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL
|
||||
#define RTC_SLOW_FREQ_8MD256 SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 //!< Internal 17.5 MHz RC oscillator, divided by 256
|
||||
|
||||
/**
|
||||
* @brief RTC FAST_CLK frequency values
|
||||
*/
|
||||
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
||||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX
|
||||
#define RTC_SLOW_CLK_FREQ_8MD256 SOC_CLK_RC_FAST_D256_FREQ_APPROX
|
||||
#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX
|
||||
|
||||
/* Alias of deprecated function names */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -383,7 +383,7 @@
|
||||
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
|
||||
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
|
||||
|
||||
#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
|
||||
// #define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
|
||||
#define SOC_UART_SUPPORT_RTC_CLK (0) /*!< Support RTC clock as the clock source */ // TODO: IDF-6249
|
||||
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
|
||||
// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: IDF-6249
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user