alex/esp-idf
alex/esp-idf
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Merge branch 'refactor/rename_h2_to_h4' into 'master'

Browse Source 
esp32h2: renaming esp32h2 to esp32h4

Closes IDF-6098

See merge request espressif/esp-idf!20676
This commit is contained in:
Kevin (Lao Kaiyao) 2022-11-09 19:19:43 +08:00
commit 5bed8fab49
539 changed files with 1679 additions and 2126 deletions
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18
.gitlab/ci/build.yml
View File

@ -155,20 +155,20 @@ build_pytest_examples_esp32c2:
IDF_TARGET: esp32c2
TEST_DIR: examples
build_pytest_examples_esp32h2:
build_pytest_examples_esp32h4:
extends:
- .build_pytest_template
- .rules:build:example_test-esp32h2
- .rules:build:example_test-esp32h4
variables:
IDF_TARGET: esp32h2
IDF_TARGET: esp32h4
TEST_DIR: examples
build_pytest_components_esp32h2:
build_pytest_components_esp32h4:
extends:
- .build_pytest_template
- .rules:build:component_ut-esp32h2
- .rules:build:component_ut-esp32h4
variables:
IDF_TARGET: esp32h2
IDF_TARGET: esp32h4
TEST_DIR: components
build_pytest_examples_esp32c6:
@ -526,12 +526,12 @@ build_examples_cmake_esp32c3:
IDF_TARGET: esp32c3
TEST_DIR: examples
build_examples_cmake_esp32h2:
build_examples_cmake_esp32h4:
extends:
- .build_cmake_template
- .rules:build:example_test-esp32h2
- .rules:build:example_test-esp32h4
variables:
IDF_TARGET: esp32h2
IDF_TARGET: esp32h4
TEST_DIR: examples
build_examples_cmake_esp32c6:

4
.gitlab/ci/dependencies/dependencies.yml
View File

@ -3,7 +3,7 @@
- esp32s2
- esp32s3
- esp32c3
- esp32h2
- esp32h4
- esp32c2
- esp32c6
@ -173,7 +173,7 @@ build:integration_test:
- target_test
- example_test
included_in:
- "build:example_test-esp32h2"
- "build:example_test-esp32h4"
- "build:example_test-esp32s3"
- "build:example_test"
- build:target_test

4
.gitlab/ci/host-test.yml
View File

@ -260,10 +260,10 @@ test_efuse_table_on_host_esp32c3:
variables:
IDF_TARGET: esp32c3
test_efuse_table_on_host_esp32h2:
test_efuse_table_on_host_esp32h4:
extends: .test_efuse_table_on_host_template
variables:
IDF_TARGET: esp32h2
IDF_TARGET: esp32h4
test_espcoredump:
extends: .host_test_template

48
.gitlab/ci/rules.yml
View File

@ -387,8 +387,8 @@
.if-label-component_ut_esp32c6: &if-label-component_ut_esp32c6
if: '$BOT_LABEL_COMPONENT_UT_ESP32C6 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32c6(?:,[^,\n\r]+)*$/i'
.if-label-component_ut_esp32h2: &if-label-component_ut_esp32h2
if: '$BOT_LABEL_COMPONENT_UT_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h2(?:,[^,\n\r]+)*$/i'
.if-label-component_ut_esp32h4: &if-label-component_ut_esp32h4
if: '$BOT_LABEL_COMPONENT_UT_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h4(?:,[^,\n\r]+)*$/i'
.if-label-component_ut_esp32s2: &if-label-component_ut_esp32s2
if: '$BOT_LABEL_COMPONENT_UT_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32s2(?:,[^,\n\r]+)*$/i'
@ -411,8 +411,8 @@
.if-label-custom_test_esp32c6: &if-label-custom_test_esp32c6
if: '$BOT_LABEL_CUSTOM_TEST_ESP32C6 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32c6(?:,[^,\n\r]+)*$/i'
.if-label-custom_test_esp32h2: &if-label-custom_test_esp32h2
if: '$BOT_LABEL_CUSTOM_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h2(?:,[^,\n\r]+)*$/i'
.if-label-custom_test_esp32h4: &if-label-custom_test_esp32h4
if: '$BOT_LABEL_CUSTOM_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h4(?:,[^,\n\r]+)*$/i'
.if-label-custom_test_esp32s2: &if-label-custom_test_esp32s2
if: '$BOT_LABEL_CUSTOM_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32s2(?:,[^,\n\r]+)*$/i'
@ -438,8 +438,8 @@
.if-label-example_test_esp32c6: &if-label-example_test_esp32c6
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32C6 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32c6(?:,[^,\n\r]+)*$/i'
.if-label-example_test_esp32h2: &if-label-example_test_esp32h2
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h2(?:,[^,\n\r]+)*$/i'
.if-label-example_test_esp32h4: &if-label-example_test_esp32h4
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h4(?:,[^,\n\r]+)*$/i'
.if-label-example_test_esp32s2: &if-label-example_test_esp32s2
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32s2(?:,[^,\n\r]+)*$/i'
@ -492,8 +492,8 @@
.if-label-unit_test_esp32c6: &if-label-unit_test_esp32c6
if: '$BOT_LABEL_UNIT_TEST_ESP32C6 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32c6(?:,[^,\n\r]+)*$/i'
.if-label-unit_test_esp32h2: &if-label-unit_test_esp32h2
if: '$BOT_LABEL_UNIT_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h2(?:,[^,\n\r]+)*$/i'
.if-label-unit_test_esp32h4: &if-label-unit_test_esp32h4
if: '$BOT_LABEL_UNIT_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h4(?:,[^,\n\r]+)*$/i'
.if-label-unit_test_esp32s2: &if-label-unit_test_esp32s2
if: '$BOT_LABEL_UNIT_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32s2(?:,[^,\n\r]+)*$/i'
@ -531,7 +531,7 @@
- <<: *if-label-component_ut_esp32c2
- <<: *if-label-component_ut_esp32c3
- <<: *if-label-component_ut_esp32c6
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-component_ut_esp32h4
- <<: *if-label-component_ut_esp32s2
- <<: *if-label-component_ut_esp32s3
- <<: *if-label-lan8720
@ -541,7 +541,7 @@
- <<: *if-label-unit_test_esp32c2
- <<: *if-label-unit_test_esp32c3
- <<: *if-label-unit_test_esp32c6
- <<: *if-label-unit_test_esp32h2
- <<: *if-label-unit_test_esp32h4
- <<: *if-label-unit_test_esp32s2
- <<: *if-label-unit_test_esp32s3
- <<: *if-dev-push
@ -651,17 +651,17 @@
- <<: *if-dev-push
changes: *patterns-target_test-i154
.rules:build:component_ut-esp32h2:
.rules:build:component_ut-esp32h4:
rules:
- <<: *if-revert-branch
when: never
- <<: *if-protected
- <<: *if-label-build
- <<: *if-label-component_ut
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-component_ut_esp32h4
- <<: *if-label-target_test
- <<: *if-label-unit_test
- <<: *if-label-unit_test_esp32h2
- <<: *if-label-unit_test_esp32h4
- <<: *if-dev-push
changes: *patterns-build_components
- <<: *if-dev-push
@ -734,7 +734,7 @@
- <<: *if-label-custom_test_esp32c2
- <<: *if-label-custom_test_esp32c3
- <<: *if-label-custom_test_esp32c6
- <<: *if-label-custom_test_esp32h2
- <<: *if-label-custom_test_esp32h4
- <<: *if-label-custom_test_esp32s2
- <<: *if-label-custom_test_esp32s3
- <<: *if-label-target_test
@ -897,7 +897,7 @@
- <<: *if-label-example_test_esp32c2
- <<: *if-label-example_test_esp32c3
- <<: *if-label-example_test_esp32c6
- <<: *if-label-example_test_esp32h2
- <<: *if-label-example_test_esp32h4
- <<: *if-label-example_test_esp32s2
- <<: *if-label-example_test_esp32s3
- <<: *if-label-iperf_stress_test
@ -1042,14 +1042,14 @@
- <<: *if-dev-push
changes: *patterns-target_test-i154
.rules:build:example_test-esp32h2:
.rules:build:example_test-esp32h4:
rules:
- <<: *if-revert-branch
when: never
- <<: *if-protected
- <<: *if-label-build
- <<: *if-label-example_test
- <<: *if-label-example_test_esp32h2
- <<: *if-label-example_test_esp32h4
- <<: *if-label-target_test
- <<: *if-dev-push
changes: *patterns-build-example_test
@ -1172,7 +1172,7 @@
- <<: *if-label-component_ut_esp32c2
- <<: *if-label-component_ut_esp32c3
- <<: *if-label-component_ut_esp32c6
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-component_ut_esp32h4
- <<: *if-label-component_ut_esp32s2
- <<: *if-label-component_ut_esp32s3
- <<: *if-label-custom_test
@ -1180,7 +1180,7 @@
- <<: *if-label-custom_test_esp32c2
- <<: *if-label-custom_test_esp32c3
- <<: *if-label-custom_test_esp32c6
- <<: *if-label-custom_test_esp32h2
- <<: *if-label-custom_test_esp32h4
- <<: *if-label-custom_test_esp32s2
- <<: *if-label-custom_test_esp32s3
- <<: *if-label-example_test
@ -1188,7 +1188,7 @@
- <<: *if-label-example_test_esp32c2
- <<: *if-label-example_test_esp32c3
- <<: *if-label-example_test_esp32c6
- <<: *if-label-example_test_esp32h2
- <<: *if-label-example_test_esp32h4
- <<: *if-label-example_test_esp32s2
- <<: *if-label-example_test_esp32s3
- <<: *if-label-integration_test
@ -1200,7 +1200,7 @@
- <<: *if-label-unit_test_esp32c2
- <<: *if-label-unit_test_esp32c3
- <<: *if-label-unit_test_esp32c6
- <<: *if-label-unit_test_esp32h2
- <<: *if-label-unit_test_esp32h4
- <<: *if-label-unit_test_esp32s2
- <<: *if-label-unit_test_esp32s3
- <<: *if-label-weekend_test
@ -1252,7 +1252,7 @@
- <<: *if-label-unit_test_esp32c2
- <<: *if-label-unit_test_esp32c3
- <<: *if-label-unit_test_esp32c6
- <<: *if-label-unit_test_esp32h2
- <<: *if-label-unit_test_esp32h4
- <<: *if-label-unit_test_esp32s2
- <<: *if-label-unit_test_esp32s3
- <<: *if-dev-push
@ -1524,7 +1524,7 @@
- <<: *if-dev-push
changes: *patterns-component_ut-adc
.rules:test:component_ut-esp32h2-i154:
.rules:test:component_ut-esp32h4-i154:
rules:
- <<: *if-revert-branch
when: never
@ -1532,7 +1532,7 @@
- <<: *if-label-build-only
when: never
- <<: *if-label-component_ut
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-component_ut_esp32h4
- <<: *if-label-target_test
- <<: *if-dev-push
changes: *patterns-target_test-i154

12
.gitlab/ci/target-test.yml
View File

@ -532,13 +532,13 @@ component_ut_pytest_esp32c3_sdspi:
- build_pytest_components_esp32c3
tags: [ esp32c3, sdcard_spimode ]
component_ut_pytest_esp32h2_i154:
component_ut_pytest_esp32h4_i154:
extends:
- .pytest_components_dir_template
- .rules:test:component_ut-esp32h2-i154
- .rules:test:component_ut-esp32h4-i154
needs:
- build_pytest_components_esp32h2
tags: [ esp32h2, ieee802154 ]
- build_pytest_components_esp32h4
tags: [ esp32h4, ieee802154 ]
example_test_pytest_openthread_br:
extends:
@ -546,9 +546,9 @@ example_test_pytest_openthread_br:
- .rules:test:example_test-i154
needs:
- build_pytest_examples_esp32s3
- build_pytest_examples_esp32h2
- build_pytest_examples_esp32h4
tags:
- esp32h2
- esp32h4
- i154_multi_dut
.pytest_test_apps_dir_template:

26
Kconfig
View File

@ -67,26 +67,26 @@ mainmenu "Espressif IoT Development Framework Configuration"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
config IDF_TARGET_ESP32H2
config IDF_TARGET_ESP32H4
bool
default "y" if IDF_TARGET="esp32h2"
default "y" if IDF_TARGET="esp32h4"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
choice IDF_TARGET_ESP32H2_BETA_VERSION
prompt "ESP32-H2 beta version"
depends on IDF_TARGET_ESP32H2
default IDF_TARGET_ESP32H2_BETA_VERSION_2
choice IDF_TARGET_ESP32H4_BETA_VERSION
prompt "ESP32-H4 beta version"
depends on IDF_TARGET_ESP32H4
default IDF_TARGET_ESP32H4_BETA_VERSION_2
help
Currently ESP32-H2 has several beta versions for internal use only.
Currently ESP32-H4 has several beta versions for internal use only.
Select the one that matches your chip model.
config IDF_TARGET_ESP32H2_BETA_VERSION_1
config IDF_TARGET_ESP32H4_BETA_VERSION_1
bool
prompt "ESP32-H2 beta1"
config IDF_TARGET_ESP32H2_BETA_VERSION_2
prompt "ESP32-H4 beta1"
config IDF_TARGET_ESP32H4_BETA_VERSION_2
bool
prompt "ESP32-H2 beta2"
prompt "ESP32-H4 beta2"
endchoice
config IDF_TARGET_ESP32C2
@ -111,10 +111,10 @@ mainmenu "Espressif IoT Development Framework Configuration"
default 0x0002 if IDF_TARGET_ESP32S2
default 0x0005 if IDF_TARGET_ESP32C3
default 0x0009 if IDF_TARGET_ESP32S3
default 0x000A if IDF_TARGET_ESP32H2_BETA_VERSION_1
default 0x000A if IDF_TARGET_ESP32H4_BETA_VERSION_1
default 0x000C if IDF_TARGET_ESP32C2
default 0x000D if IDF_TARGET_ESP32C6
default 0x000E if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3475
default 0x000E if IDF_TARGET_ESP32H4_BETA_VERSION_2 # ESP32-TODO: IDF-3475
default 0xFFFF

2
README.md
View File

@ -23,7 +23,7 @@ The following table shows ESP-IDF support of Espressif SoCs where ![alt text][pr
|ESP32-S3 | | | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
|ESP32-C2 | | | | | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
|ESP32-C6 | | | | | | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
|ESP32-H2 | | | | ![alt text][preview] | ![alt text][preview] | ![alt text][preview] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
|ESP32-H2 beta1/2| | | | ![alt text][preview] | ![alt text][preview] | ![alt text][preview] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
[supported]: https://img.shields.io/badge/-supported-green "supported"
[preview]: https://img.shields.io/badge/-preview-orange "preview"

2
README_CN.md
View File

@ -23,7 +23,7 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux
|ESP32-S3 | | | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
|ESP32-C2 | | | | | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
|ESP32-C6 | | | | | | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
|ESP32-H2 | | | | ![alt text][preview] | ![alt text][preview] | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
|ESP32-H2 beta1/2| | | | ![alt text][preview] | ![alt text][preview] | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
[supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
[preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"

2
components/app_trace/Kconfig
View File

@ -47,7 +47,7 @@ menu "Application Level Tracing"
select APPTRACE_ENABLE
select APPTRACE_DEST_UART
select APPTRACE_DEST_UART_NOUSB
depends on (ESP_CONSOLE_UART_NUM !=2) && !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32S2 && !IDF_TARGET_ESP32H2
depends on (ESP_CONSOLE_UART_NUM !=2) && (SOC_UART_NUM > 2)
config APPTRACE_DEST_USB_CDC
bool "USB_CDC"

4
components/app_update/esp_ota_ops.c
View File

@ -37,8 +37,8 @@
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/secure_boot.h"
#endif

2
components/app_update/include/esp_ota_ops.h
View File

@ -334,7 +334,7 @@ typedef enum {
/**
* @brief Revokes the old signature digest. To be called in the application after the rollback logic.
*
* Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-H2 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1).
* Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-H4 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1).
* When key \#N-1 used to sign an app is invalidated, an OTA update is to be sent with an app signed with key \#N-1 & Key \#N.
* After successfully booting the OTA app should call this function to revoke Key \#N-1.
*

6
components/bootloader/subproject/main/ld/esp32h2/bootloader.rom.ld
View File

@ -1,6 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* No definition for ESP32-H2 target */

2
components/bootloader/subproject/main/ld/esp32h2/bootloader.ld → components/bootloader/subproject/main/ld/esp32h4/bootloader.ld
View File

@ -6,7 +6,7 @@
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-H2 ROM static data usage is as follows:
* ESP32-H4 ROM static data usage is as follows:
* - 0x3fccb900 - 0x3fcdd210: Shared buffers, used in UART/USB/SPI download mode only
* - 0x3fcdd210 - 0x3fcdf210: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x3fcdf210 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)

6
components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld Normal file
View File

@ -0,0 +1,6 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* No definition for ESP32-H4 target */

6
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c → components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c
View File

@ -9,9 +9,9 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp32h2/rom/gpio.h"
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/efuse.h"
#include "esp32h4/rom/gpio.h"
#include "esp32h4/rom/spi_flash.h"
#include "esp32h4/rom/efuse.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"

8
components/bootloader_support/include/esp_app_format.h
View File

@ -17,10 +17,10 @@ typedef enum {
ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
ESP_CHIP_ID_ESP32C2 = 0x000C, /*!< chip ID: ESP32-C2 */
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
ESP_CHIP_ID_ESP32H2 = 0x000E, /*!< chip ID: ESP32-H2 Beta2*/ // ESP32H2-TODO: IDF-3475
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 Beta1 */
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
ESP_CHIP_ID_ESP32H4 = 0x000E, /*!< chip ID: ESP32-H4 Beta2*/ // ESP32H4-TODO: IDF-3475
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
ESP_CHIP_ID_ESP32H4 = 0x000A, /*!< chip ID: ESP32-H4 Beta1 */
#endif
ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */

4
components/bootloader_support/private_include/bootloader_signature.h
View File

@ -17,8 +17,8 @@
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C6

2
components/bootloader_support/src/bootloader_clock_init.c
View File

@ -46,7 +46,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
clk_ll_cpu_get_freq_mhz_from_pll() == CLK_LL_PLL_240M_FREQ_MHZ) {
cpu_freq_mhz = 240;
}
#elif CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32H4
cpu_freq_mhz = 64;
#endif

6
components/bootloader_support/src/bootloader_console.c
View File

@ -22,9 +22,9 @@
#include "esp32c3/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/ets_sys.h"
#include "esp32h4/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/ets_sys.h"
#include "esp32c2/rom/uart.h"

2
components/bootloader_support/src/bootloader_efuse.c
View File

@ -27,7 +27,7 @@ int bootloader_clock_get_rated_freq_mhz(void)
#elif CONFIG_IDF_TARGET_ESP32C3
return 160;
#elif CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32H4
return 96;
#elif CONFIG_IDF_TARGET_ESP32C6

2
components/bootloader_support/src/bootloader_random_esp32h2.c → components/bootloader_support/src/bootloader_random_esp32h4.c
View File

@ -12,7 +12,7 @@
#include "soc/system_reg.h"
#include "esp_private/regi2c_ctrl.h"
// ESP32H2-TODO: IDF-3381
// ESP32H4-TODO: IDF-3381
void bootloader_random_enable(void)
{

12
components/bootloader_support/src/bootloader_utility.c
View File

@ -28,12 +28,12 @@
#include "esp32c3/rom/uart.h"
#include "esp32c3/rom/gpio.h"
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/efuse.h"
#include "esp32h2/rom/crc.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
#include "esp32h2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/efuse.h"
#include "esp32h4/rom/crc.h"
#include "esp32h4/rom/uart.h"
#include "esp32h4/rom/gpio.h"
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/efuse.h"
#include "esp32c2/rom/crc.h"

6
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c → components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
View File

@ -25,8 +25,8 @@
#include "soc/extmem_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/system_reg.h"
#include "esp32h2/rom/efuse.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h4/rom/efuse.h"
#include "esp32h4/rom/ets_sys.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
#include "bootloader_clock.h"
@ -38,7 +38,7 @@
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
static const char *TAG = "boot.esp32h2";
static const char *TAG = "boot.esp32h4";
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{

2
components/bootloader_support/src/esp32h2/bootloader_sha.c → components/bootloader_support/src/esp32h4/bootloader_sha.c
View File

@ -9,7 +9,7 @@
#include <assert.h>
#include <sys/param.h>
#include "esp32h2/rom/sha.h"
#include "esp32h4/rom/sha.h"
static SHA_CTX ctx;

0
components/bootloader_support/src/esp32h2/bootloader_soc.c → components/bootloader_support/src/esp32h4/bootloader_soc.c
View File

0
components/bootloader_support/src/esp32h2/flash_encryption_secure_features.c → components/bootloader_support/src/esp32h4/flash_encryption_secure_features.c
View File

0
components/bootloader_support/src/esp32h2/secure_boot_secure_features.c → components/bootloader_support/src/esp32h4/secure_boot_secure_features.c
View File

4
components/bootloader_support/src/esp_image_format.c
View File

@ -29,8 +29,8 @@
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/rtc.h"
#include "esp32c2/rom/secure_boot.h"

4
components/bootloader_support/src/flash_encrypt.c
View File

@ -142,7 +142,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) {
mode = ESP_FLASH_ENC_MODE_RELEASE;
}
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C6
bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
bool dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
if (dis_dl_enc && dis_dl_icache) {
@ -191,7 +191,7 @@ void esp_flash_encryption_set_release_mode(void)
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C6
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
#ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED

4
components/bootloader_support/src/secure_boot_v2/secure_boot.c
View File

@ -23,8 +23,8 @@
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/secure_boot.h"
#endif

4
components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h
View File

@ -13,8 +13,8 @@
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/secure_boot.h"
#endif

14
components/bt/CMakeLists.txt
View File

@ -17,9 +17,9 @@ if(CONFIG_BT_ENABLED)
list(APPEND srcs "controller/esp32s3/bt.c")
list(APPEND include_dirs include/esp32s3/include)
elseif(CONFIG_IDF_TARGET_ESP32H2)
list(APPEND srcs "controller/esp32h2/bt.c")
list(APPEND include_dirs include/esp32h2/include)
elseif(CONFIG_IDF_TARGET_ESP32H4)
list(APPEND srcs "controller/esp32h4/bt.c")
list(APPEND include_dirs include/esp32h4/include)
elseif(CONFIG_IDF_TARGET_ESP32C2)
list(APPEND srcs "controller/esp32c2/bt.c")
@ -699,10 +699,12 @@ if(CONFIG_BT_ENABLED)
target_link_directories(${COMPONENT_LIB} INTERFACE
"${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
elseif(CONFIG_IDF_TARGET_ESP32H2)
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
elseif(CONFIG_IDF_TARGET_ESP32H4)
if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1)
# TODO: rename esp32h2 to esp32h4 [BT-2875]
add_prebuilt_library(nimblelib "controller/lib_esp32h2/esp32h2-bt-lib/beta1/libble_app.a")
elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2)
# TODO: rename esp32h2 to esp32h4 [BT-2875]
add_prebuilt_library(nimblelib "controller/lib_esp32h2/esp32h2-bt-lib/beta2/libble_app.a")
endif()
target_link_libraries(${COMPONENT_LIB} PRIVATE nimblelib)

0
components/bt/controller/esp32h2/Kconfig.in → components/bt/controller/esp32h4/Kconfig.in
View File

8
components/bt/controller/esp32h2/bt.c → components/bt/controller/esp32h4/bt.c
View File

@ -567,10 +567,10 @@ void controller_sleep_deinit(void)
}
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
void periph_module_etm_active(void)
{
/*This part for esp32h2 beta2*/
/*This part for esp32h4 beta2*/
REG_SET_BIT(SYSTEM_MODCLK_CONF_REG, SYSTEM_ETM_CLK_SEL | SYSTEM_ETM_CLK_ACTIVE ); //Active ETM clock
}
#endif
@ -625,8 +625,8 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
#endif
periph_module_enable(PERIPH_BT_MODULE);
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
// only use for esp32h2 beta2
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
// only use for esp32h4 beta2
periph_module_etm_active();
#endif

2
components/bt/host/bluedroid/Kconfig.in
View File

@ -1096,7 +1096,7 @@ config BT_BLE_RPA_SUPPORTED
cannot be used. This option is disabled by default on ESP32, please enable or disable this option according
to your own needs.
For ESP32C3, ESP32S3, ESP32H2 and ESP32C2, devices support network privacy mode and device privacy mode,
For ESP32C3, ESP32S3, ESP32H4 and ESP32C2, devices support network privacy mode and device privacy mode,
users can switch the two modes according to their own needs. So this option is enabled by default.
config BT_BLE_50_FEATURES_SUPPORTED

8
components/bt/host/nimble/Kconfig.in
View File

@ -64,10 +64,10 @@ config BT_NIMBLE_LOG_LEVEL
config BT_NIMBLE_MAX_CONNECTIONS
int "Maximum number of concurrent connections"
range 1 8 if (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32H2)
range 1 8 if (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32H4)
range 1 2 if IDF_TARGET_ESP32C2
range 1 9 if IDF_TARGET_ESP32
default 3 if (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32H2)
default 3 if (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32H4)
default 2 if IDF_TARGET_ESP32C2
depends on BT_NIMBLE_ENABLED
help
@ -483,7 +483,7 @@ config BT_NIMBLE_HOST_BASED_PRIVACY
config BT_NIMBLE_ENABLE_CONN_REATTEMPT
bool "Enable connection reattempts on connection establishment error"
default y if (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C2)
default y if (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32C2)
default n if IDF_TARGET_ESP32
help
Enable to make the NimBLE host to reattempt GAP connection on connection
@ -579,7 +579,7 @@ config BT_NIMBLE_MAX_PERIODIC_SYNCS
config BT_NIMBLE_MAX_PERIODIC_ADVERTISER_LIST
int "Maximum number of periodic advertiser list"
depends on BT_NIMBLE_50_FEATURE_SUPPORT && (IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2)
depends on BT_NIMBLE_50_FEATURE_SUPPORT && (IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4)
range 1 5
default 5 if BT_NIMBLE_50_FEATURE_SUPPORT
help

0
components/bt/include/esp32h2/include/esp_bt.h → components/bt/include/esp32h4/include/esp_bt.h
View File

0
components/bt/include/esp32h2/include/esp_bt_cfg.h → components/bt/include/esp32h4/include/esp_bt_cfg.h
View File

2
components/bt/porting/nimble/include/nimble/ble_hci_trans.h
View File

@ -66,7 +66,7 @@ struct os_mbuf;
typedef int ble_hci_trans_rx_cmd_fn(uint8_t *cmd, void *arg);
typedef int ble_hci_trans_rx_acl_fn(struct os_mbuf *om, void *arg);
#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
#if CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2
struct ble_hci_trans_funcs_t {
int(*_ble_hci_trans_hs_acl_tx)(struct os_mbuf *om);
int(*_ble_hci_trans_hs_cmd_tx)(uint8_t *cmd);

2
components/bt/porting/nimble/include/nimble/nimble_port.h
View File

@ -27,7 +27,7 @@
#define NIMBLE_HS_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE
#if (CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2)
#if (CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2)
#define NIMBLE_LL_STACK_SIZE CONFIG_BT_LE_CONTROLLER_TASK_STACK_SIZE
#endif

0
components/bt/sdkconfig.rename.esp32h2
View File

4
components/driver/deprecated/driver/adc_types_legacy.h
View File

@ -61,7 +61,7 @@ typedef enum {
ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */
ADC1_CHANNEL_MAX,
} adc1_channel_t;
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310
typedef enum {
ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */
@ -86,7 +86,7 @@ typedef enum {
ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */
ADC2_CHANNEL_MAX,
} adc2_channel_t;
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310
typedef enum {
ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */
ADC2_CHANNEL_MAX,

2
components/driver/test/include/test/test_common_spi.h
View File

@ -86,7 +86,7 @@
#define ESP_SPI_SLAVE_TV 0
#define WIRE_DELAY 12.5
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4
//NOTE: On these chips, there is only 1 GPSPI controller, so master-slave test on single board should be disabled
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI2_HOST

4
components/driver/test/test_i2c.c
View File

@ -32,7 +32,7 @@
#define RW_TEST_LENGTH 129 /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
#define DELAY_TIME_BETWEEN_ITEMS_MS 1234 /*!< delay time between different test items */
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H4
#define I2C_SLAVE_SCL_IO 5 /*!<gpio number for i2c slave clock */
#define I2C_SLAVE_SDA_IO 6 /*!<gpio number for i2c slave data */
#else
@ -44,7 +44,7 @@
#define I2C_SLAVE_TX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave tx buffer size */
#define I2C_SLAVE_RX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave rx buffer size */
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4
#define I2C_MASTER_SCL_IO 5 /*!<gpio number for i2c master clock */
#define I2C_MASTER_SDA_IO 6 /*!<gpio number for i2c master data */
#elif CONFIG_IDF_TARGET_ESP32S3

2
components/driver/test/test_ledc.c
View File

@ -399,7 +399,7 @@ TEST_CASE("LEDC fade stop test", "[ledc]")
}
#endif // SOC_LEDC_SUPPORT_FADE_STOP
#if SOC_PCNT_SUPPORTED // Note. C3, C2, H2 do not have PCNT peripheral, the following test cases cannot be tested
#if SOC_PCNT_SUPPORTED // Note. C3, C2, H4 do not have PCNT peripheral, the following test cases cannot be tested
#include "driver/pulse_cnt.h"

2
components/driver/test/test_rs485.c
View File

@ -32,7 +32,7 @@
#define TEST_ALLOW_PROC_FAIL (10)
#define TEST_CHECK_PROC_FAIL(fails, threshold) TEST_ASSERT((fails * 100 / PACKETS_NUMBER) <= threshold)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H4)
//No runners
static const char *TAG = "rs485_test";

4
components/driver/test/test_spi_bus_lock.c
View File

@ -33,7 +33,7 @@
#endif
// H2 and C2 will not support external flash.
// H4 and C2 will not support external flash.
#define TEST_FLASH_FREQ_MHZ 5
typedef struct {
@ -298,7 +298,7 @@ TEST_CASE("spi bus lock","[spi]")
test_bus_lock(false);
}
#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32C3, ESP32S3, ESP32C2, ESP32H2, ESP32C6)
#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32C3, ESP32S3, ESP32C2, ESP32H4, ESP32C6)
//disable, SPI1 is not available for GPSPI usage on chips later than ESP32
static IRAM_ATTR esp_err_t test_polling_send(spi_device_handle_t handle)
{

2
components/driver/test/test_spi_slave.c
View File

@ -267,7 +267,7 @@ TEST_CASE("test slave send unaligned","[spi]")
/********************************************************************************
* Test By Master & Slave (2 boards)
*
* Master (C3, C2, H2) && Slave (C3, C2, H2):
* Master (C3, C2, H4) && Slave (C3, C2, H4):
* PIN | Master | Slave |
* ----| --------- | --------- |
* CS | 10 | 10 |

2
components/driver/test/test_spi_slave_hd.c
View File

@ -600,7 +600,7 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
/********************************************************************************
* Test By Master & Slave (2 boards)
*
* Master (C3, C2, H2) && Slave (C3, C2, H2):
* Master (C3, C2, H4) && Slave (C3, C2, H4):
* PIN | Master | Slave |
* ----| --------- | --------- |
* CS | 10 | 10 |

2
components/driver/test_apps/gpio/main/test_gpio.h
View File

@ -36,7 +36,7 @@ extern "C" {
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC97_IDX)
#elif CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32H4
#define TEST_GPIO_EXT_OUT_IO (6)
#define TEST_GPIO_EXT_IN_IO (7)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)

2
components/driver/test_apps/i2s_test_apps/test_inc/test_i2s.h
View File

@ -44,7 +44,7 @@ extern "C" {
#define SLAVE_WS_IO 15
#define DATA_IN_IO 19
#define DATA_OUT_IO 18
#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
#elif CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C6
#define MASTER_MCK_IO 0
#define MASTER_BCK_IO 4
#define MASTER_WS_IO 5

2
components/driver/uart.c
View File

@ -210,7 +210,7 @@ esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t* out_freq_hz)
#endif
#if SOC_UART_SUPPORT_AHB_CLK
case UART_SCLK_AHB:
freq = APB_CLK_FREQ; //This only exist on H2. Fix this when H2 MP is supported.
freq = APB_CLK_FREQ; //This only exist on H4. Fix this when H2 MP is supported.
break;
#endif
#if SOC_UART_SUPPORT_PLL_F40M_CLK

2
components/efuse/efuse_table_gen.py
View File

@ -488,7 +488,7 @@ def main():
parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3',
'esp32h2', 'esp32c2', 'esp32c6'], default='esp32')
'esp32h4', 'esp32c2', 'esp32c6'], default='esp32')
parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false')
parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true')

2
components/efuse/esp32h2/esp_efuse_fields.c → components/efuse/esp32h4/esp_efuse_fields.c
View File

@ -9,7 +9,7 @@
#include "esp_efuse_table.h"
#include "stdlib.h"
#include "esp_types.h"
#include "esp32h2/rom/efuse.h"
#include "esp32h4/rom/efuse.h"
#include "assert.h"
#include "esp_err.h"
#include "esp_log.h"

0
components/efuse/esp32h2/esp_efuse_rtc_calib.c → components/efuse/esp32h4/esp_efuse_rtc_calib.c
View File

6
components/efuse/esp32h2/esp_efuse_table.c → components/efuse/esp32h4/esp_efuse_table.c
View File

@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 4ff665f7ab2f32b83f2b5b232bcdeac8
// md5_digest_table b9e60ac2d8c534764d7bee10063617aa
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -378,7 +378,7 @@ static const esp_efuse_desc_t WAFER_VERSION[] = {
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 117, 3}, // Package version 0:ESP32H2,
{EFUSE_BLK1, 117, 3}, // Package version 0:ESP32H4,
};
static const esp_efuse_desc_t BLOCK1_VERSION[] = {
@ -925,7 +925,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
};
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
&PKG_VERSION[0], // Package version 0:ESP32H2
&PKG_VERSION[0], // Package version 0:ESP32H4
NULL
};

4
components/efuse/esp32h2/esp_efuse_table.csv → components/efuse/esp32h4/esp_efuse_table.csv
View File

@ -10,7 +10,7 @@
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# ESP32H2-TODO: IDF-3390
# ESP32H4-TODO: IDF-3390
# EFUSE_RD_REPEAT_DATA BLOCK #
##############################
# EFUSE_RD_WR_DIS_REG #
@ -123,7 +123,7 @@
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32H2
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32H4
BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version
# SYS_DATA_PART1 BLOCK# - System configuration
Can't render this file because it contains an unexpected character in line 7 and column 87.

0
components/efuse/esp32h2/esp_efuse_utility.c → components/efuse/esp32h4/esp_efuse_utility.c
View File

2
components/efuse/esp32h2/include/esp_efuse_chip.h → components/efuse/esp32h4/include/esp_efuse_chip.h
View File

@ -11,7 +11,7 @@ extern "C" {
#endif
/**
* @brief Type of eFuse blocks ESP32H2
* @brief Type of eFuse blocks ESP32H4
*/
typedef enum {
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */

0
components/efuse/esp32h2/include/esp_efuse_rtc_calib.h → components/efuse/esp32h4/include/esp_efuse_rtc_calib.h
View File

2
components/efuse/esp32h2/include/esp_efuse_table.h → components/efuse/esp32h4/include/esp_efuse_table.h
View File

@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table 4ff665f7ab2f32b83f2b5b232bcdeac8
// md5_digest_table b9e60ac2d8c534764d7bee10063617aa
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.

0
components/efuse/esp32h2/private_include/esp_efuse_utility.h → components/efuse/esp32h4/private_include/esp_efuse_utility.h
View File

0
components/efuse/esp32h2/sources.cmake → components/efuse/esp32h4/sources.cmake
View File

0
components/esp_adc/esp32h2/include/adc_cali_schemes.h → components/esp_adc/esp32h4/include/adc_cali_schemes.h
View File

0
components/esp_gdbstub/esp32h2/gdbstub_esp32h2.c → components/esp_gdbstub/esp32h4/gdbstub_esp32h4.c
View File

0
components/esp_gdbstub/esp32h2/gdbstub_target_config.h → components/esp_gdbstub/esp32h4/gdbstub_target_config.h
View File

4
components/esp_hw_support/cpu.c
View File

@ -303,12 +303,12 @@ void esp_cpu_configure_region_protection(void)
mpu_hal_set_region_access(1, MPU_REGION_RW); // 0x20000000
}
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4
void esp_cpu_configure_region_protection(void)
{
/* Notes on implementation:
*
* 1) Note: ESP32-C3/H2 CPU doesn't support overlapping PMP regions
* 1) Note: ESP32-C3/H4 CPU doesn't support overlapping PMP regions
*
* 2) Therefore, we use TOR (top of range) entries to map the whole address
* space, bottom to top.

6
components/esp_hw_support/esp_clk.c
View File

@ -29,9 +29,9 @@
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#include "esp32c3/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/rtc.h"
#include "esp32h4/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/rtc.h"
#include "esp32c2/rtc.h"

2
components/esp_hw_support/include/esp_chip_info.h
View File

@ -24,7 +24,7 @@ typedef enum {
CHIP_ESP32S2 = 2, //!< ESP32-S2
CHIP_ESP32S3 = 9, //!< ESP32-S3
CHIP_ESP32C3 = 5, //!< ESP32-C3
CHIP_ESP32H2 = 6, //!< ESP32-H2
CHIP_ESP32H4 = 6, //!< ESP32-H4
CHIP_ESP32C2 = 12, //!< ESP32-C2
CHIP_ESP32C6 = 13, //!< ESP32-C6
} esp_chip_model_t;

4
components/esp_hw_support/include/esp_mac.h
View File

@ -37,8 +37,8 @@ typedef enum {
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32C3
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32H2
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H2_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32H4
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H4_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32C2
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32C6

2
components/esp_hw_support/include/esp_private/esp_sleep_internal.h
View File

@ -22,7 +22,7 @@ extern "C" {
void esp_sleep_enable_adc_tsens_monitor(bool enable);
// TODO: IDF-6051, IDF-6052
#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6
#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6
/**
* @brief Isolate all digital IOs except those that are held during deep sleep
*

0
components/esp_hw_support/include/soc/esp32h2/esp_crypto_lock.h → components/esp_hw_support/include/soc/esp32h4/esp_crypto_lock.h
View File

0
components/esp_hw_support/include/soc/esp32h2/esp_ds.h → components/esp_hw_support/include/soc/esp32h4/esp_ds.h
View File

2
components/esp_hw_support/include/soc/esp32h2/rtc.h → components/esp_hw_support/include/soc/esp32h4/rtc.h
View File

@ -13,7 +13,7 @@ extern "C" {
#endif
/**
* @file esp32h2/rtc.h
* @file esp32h4/rtc.h
*
* This file contains declarations of rtc related functions.
*/

2
components/esp_hw_support/include/soc/esp32h2/soc_memprot_types.h → components/esp_hw_support/include/soc/esp32h4/soc_memprot_types.h
View File

@ -5,7 +5,7 @@
*/
//////////////////////////////////////////////////////////
// ESP32-H2 PMS memory protection types
// ESP32-H4 PMS memory protection types
//
#pragma once

6
components/esp_hw_support/mac_addr.c
View File

@ -221,10 +221,10 @@ esp_err_t esp_read_mac(uint8_t *mac, esp_mac_type_t type)
case ESP_MAC_BT:
#if CONFIG_ESP_MAC_ADDR_UNIVERSE_BT
memcpy(mac, efuse_mac, 6);
#if !CONFIG_IDF_TARGET_ESP32H2
// esp32h2 chips do not have wifi module, so the mac address do not need to add the BT offset
#if !CONFIG_IDF_TARGET_ESP32H4
// esp32h4 chips do not have wifi module, so the mac address do not need to add the BT offset
mac[5] += MAC_ADDR_UNIVERSE_BT_OFFSET;
#endif //!CONFIG_IDF_TARGET_ESP32H2
#endif //!CONFIG_IDF_TARGET_ESP32H4
#else
return ESP_ERR_NOT_SUPPORTED;
#endif // CONFIG_ESP_MAC_ADDR_UNIVERSE_BT

0
components/esp_hw_support/port/esp32h2/CMakeLists.txt → components/esp_hw_support/port/esp32h4/CMakeLists.txt
View File

22
components/esp_hw_support/port/esp32h2/Kconfig.hw_support → components/esp_hw_support/port/esp32h4/Kconfig.hw_support
View File

@ -1,6 +1,6 @@
choice ESP32H2_REV_MIN
prompt "Minimum Supported ESP32-H2 Revision"
default ESP32H2_REV_MIN_0
choice ESP32H4_REV_MIN
prompt "Minimum Supported ESP32-H4 Revision"
default ESP32H4_REV_MIN_0
help
Required minimum chip revision. ESP-IDF will check for it and
reject to boot if the chip revision fails the check.
@ -9,33 +9,33 @@ choice ESP32H2_REV_MIN
The complied binary will only support chips above this revision,
this will also help to reduce binary size.
config ESP32H2_REV_MIN_0
config ESP32H4_REV_MIN_0
bool "Rev v0.0 (ECO0)"
endchoice
config ESP32H2_REV_MIN_FULL
config ESP32H4_REV_MIN_FULL
int
default 0 if ESP32H2_REV_MIN_0
default 0 if ESP32H4_REV_MIN_0
config ESP_REV_MIN_FULL
int
default ESP32H2_REV_MIN_FULL
default ESP32H4_REV_MIN_FULL
#
# MAX Revision
#
comment "Maximum Supported ESP32-H2 Revision (Rev v1.99)"
comment "Maximum Supported ESP32-H4 Revision (Rev v1.99)"
# Maximum revision that IDF supports.
# It can not be changed by user.
# Only Espressif can change it when a new version will be supported in IDF.
# Supports all chips starting from ESP32H2_REV_MIN_FULL to ESP32H2_REV_MAX_FULL
# Supports all chips starting from ESP32H4_REV_MIN_FULL to ESP32H4_REV_MAX_FULL
config ESP32H2_REV_MAX_FULL
config ESP32H4_REV_MAX_FULL
int
default 199
# keep in sync the "Maximum Supported Revision" description with this value
config ESP_REV_MAX_FULL
int
default ESP32H2_REV_MAX_FULL
default ESP32H4_REV_MAX_FULL

12
components/esp_hw_support/port/esp32h2/Kconfig.mac → components/esp_hw_support/port/esp32h4/Kconfig.mac
View File

@ -1,18 +1,18 @@
# ESP32H2-TODO: IDF-3390
choice ESP32H2_UNIVERSAL_MAC_ADDRESSES
# ESP32H4-TODO: IDF-3390
choice ESP32H4_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
default ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
config ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
config ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_ADDR_UNIVERSE_IEEE802154
select ESP_MAC_ADDR_UNIVERSE_BT
endchoice
config ESP32H2_UNIVERSAL_MAC_ADDRESSES
config ESP32H4_UNIVERSAL_MAC_ADDRESSES
int
default 2 if ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
default 2 if ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO

0
components/esp_hw_support/port/esp32h2/Kconfig.rtc → components/esp_hw_support/port/esp32h4/Kconfig.rtc
View File

2
components/esp_hw_support/port/esp32h2/chip_info.c → components/esp_hw_support/port/esp32h4/chip_info.c
View File

@ -11,7 +11,7 @@
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32H2;
out_info->model = CHIP_ESP32H4;
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE;

0
components/esp_hw_support/port/esp32h2/esp_crypto_lock.c → components/esp_hw_support/port/esp32h4/esp_crypto_lock.c
View File

2
components/esp_hw_support/port/esp32h2/esp_ds.c → components/esp_hw_support/port/esp32h4/esp_ds.c
View File

@ -15,7 +15,7 @@
#include "hal/ds_hal.h"
#include "hal/ds_ll.h"
#include "hal/hmac_hal.h"
#include "esp32h2/rom/digital_signature.h"
#include "esp32h4/rom/digital_signature.h"
#include "esp_timer.h"
#include "esp_ds.h"

0
components/esp_hw_support/port/esp32h2/esp_memprot.c → components/esp_hw_support/port/esp32h4/esp_memprot.c
View File

0
components/esp_hw_support/port/esp32h2/i2c_brownout.h → components/esp_hw_support/port/esp32h4/i2c_brownout.h
View File

10
components/esp_hw_support/port/esp32h2/rtc_clk.c → components/esp_hw_support/port/esp32h4/rtc_clk.c
View File

@ -10,10 +10,10 @@
#include <assert.h>
#include <stdlib.h>
#include "sdkconfig.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
#include "esp32h4/rom/ets_sys.h"
#include "esp32h4/rom/rtc.h"
#include "esp32h4/rom/uart.h"
#include "esp32h4/rom/gpio.h"
#include "soc/rtc.h"
#include "soc/io_mux_reg.h"
#include "hal/clk_tree_ll.h"
@ -61,7 +61,7 @@ void rtc_clk_32k_enable_external(void)
void rtc_clk_32k_bootstrap(uint32_t cycle)
{
/* No special bootstrapping needed for ESP32-H2, 'cycle' argument is to keep the signature
/* No special bootstrapping needed for ESP32-H4, 'cycle' argument is to keep the signature
* same as for the ESP32. Just enable the XTAL here.
*/
(void)cycle;

12
components/esp_hw_support/port/esp32h2/rtc_clk_init.c → components/esp_hw_support/port/esp32h4/rtc_clk_init.c
View File

@ -9,10 +9,10 @@
#include <stddef.h>
#include <stdlib.h>
#include "sdkconfig.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
#include "esp32h4/rom/ets_sys.h"
#include "esp32h4/rom/rtc.h"
#include "esp32h4/rom/uart.h"
#include "esp32h4/rom/gpio.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/rtc_cntl_reg.h"
@ -38,9 +38,9 @@ void rtc_clk_init(rtc_clk_config_t cfg)
* - CK8M_DFREQ value controls tuning of 8M clock.
* CLK_8M_DFREQ constant gives the best temperature characteristics.
*/
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
REG_SET_FIELD(RTC_CNTL_REGULATOR_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
#endif
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);

4
components/esp_hw_support/port/esp32h2/rtc_init.c → components/esp_hw_support/port/esp32h4/rtc_init.c
View File

@ -81,10 +81,10 @@ void rtc_init(rtc_config_t cfg)
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
}
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_DBOOST_FORCE_PU);
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
#endif

2
components/esp_hw_support/port/esp32h2/rtc_pm.c → components/esp_hw_support/port/esp32h4/rtc_pm.c
View File

@ -44,7 +44,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
switch (sleep_mode) {
case PM_LIGHT_SLEEP:
// cfg.wifi_pd_en = 1; // ESP32-H2 TO-DO: IDF-3693
// cfg.wifi_pd_en = 1; // ESP32-H4 TO-DO: IDF-3693
cfg.dig_dbias_wak = 4;
cfg.dig_dbias_slp = 0;
cfg.rtc_dbias_wak = 0;

10
components/esp_hw_support/port/esp32h2/rtc_sleep.c → components/esp_hw_support/port/esp32h4/rtc_sleep.c
View File

@ -16,8 +16,8 @@
#include "soc/fe_reg.h"
#include "soc/timer_group_reg.h"
#include "soc/system_reg.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/rtc.h"
#include "esp32h4/rom/ets_sys.h"
#include "esp32h4/rom/rtc.h"
#include "regi2c_ctrl.h"
#include "soc/regi2c_bias.h"
#include "soc/regi2c_ulp.h"
@ -26,10 +26,10 @@
#include "esp_hw_log.h"
#include "esp_rom_uart.h"
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIG_REGULATOR_REG
#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_DIG_REGULATOR_REG
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIGULATOR_REG
#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_REG
#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG RTC_CNTL_DIGULATOR1_DBIAS_REG
@ -244,7 +244,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
// ESP32-H2 TO-DO: IDF-3693
// ESP32-H4 TO-DO: IDF-3693
if (cfg.deep_slp) {
// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);

4
components/esp_hw_support/port/esp32h2/rtc_time.c → components/esp_hw_support/port/esp32h4/rtc_time.c
View File

@ -5,7 +5,7 @@
*/
#include <stdint.h>
#include "esp32h2/rom/ets_sys.h"
#include "esp32h4/rom/ets_sys.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
@ -32,7 +32,7 @@
*/
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
{
/* On ESP32H2, choosing RTC_CAL_RTC_MUX results in calibration of
/* On ESP32H4, choosing RTC_CAL_RTC_MUX results in calibration of
* the 150k RTC clock regardless of the currenlty selected SLOW_CLK.
* On the ESP32, it used the currently selected SLOW_CLK.
* The following code emulates ESP32 behavior:

0
components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c → components/esp_hw_support/port/esp32h4/sar_periph_ctrl.c
View File

0
components/esp_hw_support/port/esp32h2/systimer.c → components/esp_hw_support/port/esp32h4/systimer.c
View File

7
components/esp_hw_support/sdkconfig.rename.esp32h2
View File

@ -1,7 +0,0 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_ESP32H2_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC
CONFIG_ESP32H2_RTC_CLK_SRC_EXT_CRYS CONFIG_RTC_CLK_SRC_EXT_CRYS
CONFIG_ESP32H2_RTC_CLK_SRC_EXT_OSC CONFIG_RTC_CLK_SRC_EXT_OSC
CONFIG_ESP32H2_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES

2
components/esp_hw_support/sleep_gpio.c
View File

@ -105,7 +105,7 @@ void esp_sleep_enable_gpio_switch(bool enable)
#endif // SOC_GPIO_SUPPORT_SLP_SWITCH
// TODO: IDF-6051, IDF-6052
#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6
#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6
IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
{
gpio_hal_context_t gpio_hal = {

10
components/esp_hw_support/sleep_modes.c
View File

@ -71,9 +71,9 @@
#include "esp32c3/rom/rtc.h"
#include "soc/extmem_reg.h"
#include "esp_private/sleep_mac_bb.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/cache.h"
#include "esp32h4/rom/rtc.h"
#include "soc/extmem_reg.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
@ -106,7 +106,7 @@
#elif CONFIG_IDF_TARGET_ESP32C3
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (105)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37)
#elif CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32H4
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (105)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37)
#elif CONFIG_IDF_TARGET_ESP32C2
@ -510,7 +510,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
uint32_t result;
if (deep_sleep) {
// TODO: IDF-6051, IDF-6052
#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6
#if !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C6
esp_sleep_isolate_digital_gpio();
#endif

6
components/esp_hw_support/test/test_rtc_clk.c
View File

@ -40,9 +40,9 @@
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rtc.h"
#include "esp32c3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rtc.h"
#include "esp32h2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rtc.h"
#include "esp32h4/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rtc.h"
#include "esp32c2/rom/rtc.h"

16
components/esp_phy/CMakeLists.txt
View File

@ -15,7 +15,7 @@ else()
set(ldfragments "linker.lf")
endif()
if(IDF_TARGET STREQUAL "esp32h2")
if(IDF_TARGET STREQUAL "esp32h4")
list(APPEND srcs "src/phy_init_esp32hxx.c")
else()
list(APPEND srcs "src/phy_init.c")
@ -42,12 +42,14 @@ idf_component_register(SRCS "${srcs}"
)
set(target_name "${idf_target}")
if(IDF_TARGET STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/rev2")
if(IDF_TARGET STREQUAL "esp32h4")
if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2)
# TODO: rename esp32h2 to esp32h4 [WIFI-4956]
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h2/rev2")
endif()
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/rev1")
if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1)
# TODO: rename esp32h2 to esp32h4 [WIFI-4956]
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h2/rev1")
endif()
else()
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}")
@ -73,7 +75,7 @@ if(link_binary_libs)
endif()
if(CONFIG_IDF_TARGET_ESP32C3 OR CONFIG_IDF_TARGET_ESP32S3
OR CONFIG_IDF_TARGET_ESP32H2 OR CONFIG_IDF_TARGET_ESP32C2)
OR CONFIG_IDF_TARGET_ESP32H4 OR CONFIG_IDF_TARGET_ESP32C2)
target_link_libraries(${COMPONENT_LIB} PUBLIC btbb)
target_link_libraries(${COMPONENT_LIB} INTERFACE $<TARGET_FILE:${esp_phy_lib}> libphy.a libbtbb.a
$<TARGET_FILE:${esp_phy_lib}>)

30
components/esp_phy/esp32h2/include/phy_init_data.h
View File

@ -1,30 +0,0 @@
// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef PHY_INIT_DATA_H
#define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
#include "esp_phy_init.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
// There is no init data for H2 right now, could be added when necessary.
#ifdef __cplusplus
}
#endif
#endif /* PHY_INIT_DATA_H */

22
components/esp_phy/esp32h4/include/phy_init_data.h Normal file
View File

@ -0,0 +1,22 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef PHY_INIT_DATA_H
#define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
#include "esp_phy_init.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
// There is no init data for H4 right now, could be added when necessary.
#ifdef __cplusplus
}
#endif
#endif /* PHY_INIT_DATA_H */

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